J. Baer, Meei-Chiueh Liem, L. McMurchie, R. Nottrott, L. Snyder, Wayne Winder
A declaration hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the notation in a way that emphasizes common elements. The notation is the basic of a structured environment for developing design generators as well as capturing design expertise.<>
{"title":"A notation for describing multiple views of VLSI circuits","authors":"J. Baer, Meei-Chiueh Liem, L. McMurchie, R. Nottrott, L. Snyder, Wayne Winder","doi":"10.1109/DAC.1988.14743","DOIUrl":"https://doi.org/10.1109/DAC.1988.14743","url":null,"abstract":"A declaration hierarchical notation is introduced that allows the parametric representation of entire families of VLSI circuits. Layout, schematic diagrams and network structure are all accommodated by the notation in a way that emphasizes common elements. The notation is the basic of a structured environment for developing design generators as well as capturing design expertise.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130251204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A report is presented on the results of a first controlled experiment comparing formalisms and systems that are currently used for formally specifying and verifying both hardware and software systems. The strategy consists of working with incrementally harder test cases, which are used to investigate the characteristics and thus the pros and cons of each formalism. The example used is a purely combinational device.<>
{"title":"Formal specification and verification of hardware: a comparative case study","authors":"V. Stavridou, H. Barringer, D. A. Edwards","doi":"10.1109/DAC.1988.14758","DOIUrl":"https://doi.org/10.1109/DAC.1988.14758","url":null,"abstract":"A report is presented on the results of a first controlled experiment comparing formalisms and systems that are currently used for formally specifying and verifying both hardware and software systems. The strategy consists of working with incrementally harder test cases, which are used to investigate the characteristics and thus the pros and cons of each formalism. The example used is a purely combinational device.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128237130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A study is made of a pin assignment for macrocells, motivated by the goal of integrating the placement and routing steps in the physical design of VLSI circuits. The authors assume that the macrocells have already been placed and that the design of the macrocells is still 'soft' in that, although the pins in a cell have a fixed relative order, they can be shifted around the boundary of the cell. An algorithm is developed to determine the optimal shiftings of the pins so that a weighted sum of the lengths of the connecting wires is minimum. Good experimental results have been obtained.<>
{"title":"A new approach to the pin assignment problem","authors":"Xianjin Yao, M. Yamada, C. Liu","doi":"10.1109/DAC.1988.14817","DOIUrl":"https://doi.org/10.1109/DAC.1988.14817","url":null,"abstract":"A study is made of a pin assignment for macrocells, motivated by the goal of integrating the placement and routing steps in the physical design of VLSI circuits. The authors assume that the macrocells have already been placed and that the design of the macrocells is still 'soft' in that, although the pins in a cell have a fixed relative order, they can be shifted around the boundary of the cell. An algorithm is developed to determine the optimal shiftings of the pins so that a weighted sum of the lengths of the connecting wires is minimum. Good experimental results have been obtained.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115280231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present an incremental-in-time algorithm for incremental simulation of digital circuits. In contrast to the incremental-in-space algorithm, which pessimistically resimulates the circuit components that could be affected by design changes throughout the simulation time frames, the incremental-in-time algorithm resimulates a circuit component only for the simulation time frames when its inputs or internal state variable make different state transitions from the previous simulation run. It maximally utilizes the past history, thereby reducing the number of component evaluations to a minimum. Experimental results obtained for several practical circuits show speedups up to 30 times faster than conventional event-driven stimulation.<>
{"title":"Incremental-in-time algorithm for digital simulation","authors":"Kiyoung Choi, Sun-Young Hwang, T. Blank","doi":"10.1109/DAC.1988.14806","DOIUrl":"https://doi.org/10.1109/DAC.1988.14806","url":null,"abstract":"The authors present an incremental-in-time algorithm for incremental simulation of digital circuits. In contrast to the incremental-in-space algorithm, which pessimistically resimulates the circuit components that could be affected by design changes throughout the simulation time frames, the incremental-in-time algorithm resimulates a circuit component only for the simulation time frames when its inputs or internal state variable make different state transitions from the previous simulation run. It maximally utilizes the past history, thereby reducing the number of component evaluations to a minimum. Experimental results obtained for several practical circuits show speedups up to 30 times faster than conventional event-driven stimulation.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132862326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A technique is described for maintaining very-fine-grained links between a behavioral specification and an automatically generated VLSI structural implementation. CORAL II exceed previous systems in the scope of design representations involved and the complexity of the relationships handled. The design representations used are described, as are the behavioral transformations that can be applied and the types of design choices that can be made. The complications introduced by these transformations and design decisions are discussed. Some possible applications of CORAL II are outlined and an existing graphical interface for examining the synthesized design and its relationship to the behavioral specification is described.<>
{"title":"CORAL II: linking behavior and structure in an IC design system","authors":"R. Blackburn, D. E. Thomas, Patti M. Koenig","doi":"10.1109/DAC.1988.14811","DOIUrl":"https://doi.org/10.1109/DAC.1988.14811","url":null,"abstract":"A technique is described for maintaining very-fine-grained links between a behavioral specification and an automatically generated VLSI structural implementation. CORAL II exceed previous systems in the scope of design representations involved and the complexity of the relationships handled. The design representations used are described, as are the behavioral transformations that can be applied and the types of design choices that can be made. The complications introduced by these transformations and design decisions are discussed. Some possible applications of CORAL II are outlined and an existing graphical interface for examining the synthesized design and its relationship to the behavioral specification is described.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114798370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Parallel mask verification algorithms have been developed for the Connection Machine, a massively parallel processor with up to 64K processors. A discussion is presented of the design and implementation of algorithms for several essential primitives: generation of completely intersected mask data, mask-to-mask Boolean operations, labeling of connected regions, and identification of width and spacing violations. Performance results from experiments on a 16K-processor machine are presented. Speedups between 40 and 240 over a VAX 11/785 have been measured.<>
{"title":"Mask verification on the Connection Machine","authors":"E. Carlson, Rob A. Rutenbar","doi":"10.1109/DAC.1988.14748","DOIUrl":"https://doi.org/10.1109/DAC.1988.14748","url":null,"abstract":"Parallel mask verification algorithms have been developed for the Connection Machine, a massively parallel processor with up to 64K processors. A discussion is presented of the design and implementation of algorithms for several essential primitives: generation of completely intersected mask data, mask-to-mask Boolean operations, labeling of connected regions, and identification of width and spacing violations. Performance results from experiments on a 16K-processor machine are presented. Speedups between 40 and 240 over a VAX 11/785 have been measured.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121341484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments.<>
{"title":"Fault simulation in a distributed environment","authors":"P. Duba, R. Roy, J. Abraham, W. A. Rogers","doi":"10.1109/DAC.1988.14843","DOIUrl":"https://doi.org/10.1109/DAC.1988.14843","url":null,"abstract":"Fault simulation of VLSI circuits takes considerable computing resources and there have been significant efforts to speed up the fault simulation process. A distributed fault simulator implemented on a loosely-coupled network of general-purpose computers is described. The techniques used result in a close to linear speedup and can be used effectively in most industrial VLSI CAD (computer-aided design) environments.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116610916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Hill, Eltayeb Abuelyamen, Wei-Kang Huang, Guo-Qiang Shen
A novel approach to clock-mode simulation of sequential circuits is introduced. Surrogate fault propagation is used for processing stored faults and extracting new faults from combinational logic. Problem fault types are analyzed and treated as exceptions.<>
{"title":"A new two task algorithm for clock mode fault simulation in sequential circuits","authors":"F. Hill, Eltayeb Abuelyamen, Wei-Kang Huang, Guo-Qiang Shen","doi":"10.1109/DAC.1988.14820","DOIUrl":"https://doi.org/10.1109/DAC.1988.14820","url":null,"abstract":"A novel approach to clock-mode simulation of sequential circuits is introduced. Surrogate fault propagation is used for processing stored faults and extracting new faults from combinational logic. Problem fault types are analyzed and treated as exceptions.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131724831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Three parallel algorithms for logic simulation have been developed and implemented on a general-purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speedups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled-mode algorithm which achieves speedups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between speeds one to three times faster than the conventional event-driven algorithm using one processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors.<>
{"title":"Parallel logic simulation on general purpose machines","authors":"Larry Soulé, T. Blank","doi":"10.1109/DAC.1988.14753","DOIUrl":"https://doi.org/10.1109/DAC.1988.14753","url":null,"abstract":"Three parallel algorithms for logic simulation have been developed and implemented on a general-purpose shared-memory parallel machine. The first algorithm is a synchronous version of a traditional event-driven algorithm which achieves speedups of 6 to 9 with 15 processors. The second algorithm is a synchronous unit-delay compiled-mode algorithm which achieves speedups of 10 to 13 with 15 processors. The third algorithm is totally asynchronous with no synchronization locks or barriers between processors and the problems of massive state storage and deadlock that are traditionally associated with asynchronous simulation have been eliminated. The processors work independently at their own speed on different elements and at different times. When simulating circuits with little or no feedback, the asynchronous simulation technique varies between speeds one to three times faster than the conventional event-driven algorithm using one processor and depending on the circuit, achieves 10 to 20% better utilization using 15 processors.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123499298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A collection of tools that support the construction and analysis of Petri-net models is described. These models are particularly well-suited to modeling hardware systems, such as pipelined processors. The focus is on a subset of the tools that comprise the P-NUT system. The features of the particular Petri-net model used which make the modeling of pipelining easy are highlighted. An example of a pipelined processor of moderate complexity is presented, and extensions needed to model even more complex systems are discussed. The types of analyses need to evaluate pipelined processors effectively are discussed.<>
{"title":"The use of Petri nets for modeling pipelined processors","authors":"R. Razouk","doi":"10.1109/DAC.1988.14814","DOIUrl":"https://doi.org/10.1109/DAC.1988.14814","url":null,"abstract":"A collection of tools that support the construction and analysis of Petri-net models is described. These models are particularly well-suited to modeling hardware systems, such as pipelined processors. The focus is on a subset of the tools that comprise the P-NUT system. The features of the particular Petri-net model used which make the modeling of pipelining easy are highlighted. An example of a pipelined processor of moderate complexity is presented, and extensions needed to model even more complex systems are discussed. The types of analyses need to evaluate pipelined processors effectively are discussed.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125945284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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