A determination is made of the best micro-operation perturbation for modeling faults at the chip level. The measure used is the gate level stuck-at-fault coverage achieved by the tests derived to cover the micro-operation perturbation faults. For small combination circuits, it is shown that perturbing the elements into the logic dual is a good choice. For large combinational circuits, it is shown that there is very little variation in the gate level coverage achieved by the various microoperation faults. In this case, if coverage is to be improved, the micro-operation perturbation method must be augmented by other techniques.<>
{"title":"Micro-operation perturbations in chip level fault modeling","authors":"Chien-Hung Chao, F. G. Gray","doi":"10.1109/DAC.1988.14819","DOIUrl":"https://doi.org/10.1109/DAC.1988.14819","url":null,"abstract":"A determination is made of the best micro-operation perturbation for modeling faults at the chip level. The measure used is the gate level stuck-at-fault coverage achieved by the tests derived to cover the micro-operation perturbation faults. For small combination circuits, it is shown that perturbing the elements into the logic dual is a good choice. For large combinational circuits, it is shown that there is very little variation in the gate level coverage achieved by the various microoperation faults. In this case, if coverage is to be improved, the micro-operation perturbation method must be augmented by other techniques.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122877323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A design browser is a tool for exploring the interconnected web of design objects managed by a CAD (computer-aided design) database. The browser described here presents this information graphically-directed graphs are drawn to show the relationships that exist between objects in the database. Since graphs can become very large, techniques referred to as rectangular and hourglass pruning have been developed to reduce the information displayed to a manageable level. This browser allows designers to visualize the rich, multidimensional structure of their designs.<>
{"title":"Browsing the chip design database","authors":"D. Gedye, R. Katz","doi":"10.1109/DAC.1988.14769","DOIUrl":"https://doi.org/10.1109/DAC.1988.14769","url":null,"abstract":"A design browser is a tool for exploring the interconnected web of design objects managed by a CAD (computer-aided design) database. The browser described here presents this information graphically-directed graphs are drawn to show the relationships that exist between objects in the database. Since graphs can become very large, techniques referred to as rectangular and hourglass pruning have been developed to reduce the information displayed to a manageable level. This browser allows designers to visualize the rich, multidimensional structure of their designs.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126537512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A behavioral and logic simulation system which uses extensive optimization and compilation techniques to obtain high performance is described. It incorporates data-flow analysis to optimize the evaluation of unordered assignment statements that define a hardware structure, and to extract clocking rules. An integral code generator produces efficient assembly code for three different machines, and an associated run-time library provides a flexible interactive debugging environment.<>
{"title":"Hardware logic simulation by compilation","authors":"Craig Hansen","doi":"10.1109/DAC.1988.14848","DOIUrl":"https://doi.org/10.1109/DAC.1988.14848","url":null,"abstract":"A behavioral and logic simulation system which uses extensive optimization and compilation techniques to obtain high performance is described. It incorporates data-flow analysis to optimize the evaluation of unordered assignment statements that define a hardware structure, and to extract clocking rules. An integral code generator produces efficient assembly code for three different machines, and an associated run-time library provides a flexible interactive debugging environment.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129855181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors have built a prototype object-oriented database system called ORION to support applications from the CAD/CAM (computer-aided-design/computer-aided-manufacturing), AI (artificial-intelligence), and office-information-system domains. Advanced functions supported in ORION include versions, change notification, composite objects, dynamic schema evolution, and multimedia data. The versions and change notification features are based on a model that the authors developed earlier. They have integrated their model of versions and change notification into the ORION object-oriented data model, and also provide an insight into system overhead that versions and change notification incur.<>
{"title":"Versions and change notification in an object-oriented database system","authors":"H. Chou, Won Kim","doi":"10.1109/DAC.1988.14770","DOIUrl":"https://doi.org/10.1109/DAC.1988.14770","url":null,"abstract":"The authors have built a prototype object-oriented database system called ORION to support applications from the CAD/CAM (computer-aided-design/computer-aided-manufacturing), AI (artificial-intelligence), and office-information-system domains. Advanced functions supported in ORION include versions, change notification, composite objects, dynamic schema evolution, and multimedia data. The versions and change notification features are based on a model that the authors developed earlier. They have integrated their model of versions and change notification into the ORION object-oriented data model, and also provide an insight into system overhead that versions and change notification incur.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129009661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A high-performance hardware accelerator is described for electrical simulation, with a speedup of over 500 for a uniprocessor. The processor addresses a variety of problems ranging from timing simulation to circuit simulation. The accelerator combines special purpose units, such as a high-speed device evaluator, with a fully programmable general-purpose processor. The specialized processors offer extremely high speed for performance-critical parts of the simulation. The general-purpose processors are optimized for compiled electrical simulation, and use a very long instruction word (VLIW) architecture. The network solution is compiled into VLIW code. The author concentrates on those features of the machine that are designed for circuit simulation algorithms, such as SPICE. A simplified example is used to expose the hardware and software techniques used to attack the problem, and estimate the performance improvement due to each technique.<>
{"title":"A programmable hardware accelerator for compiled electrical simulation","authors":"D. Lewis","doi":"10.1109/DAC.1988.14754","DOIUrl":"https://doi.org/10.1109/DAC.1988.14754","url":null,"abstract":"A high-performance hardware accelerator is described for electrical simulation, with a speedup of over 500 for a uniprocessor. The processor addresses a variety of problems ranging from timing simulation to circuit simulation. The accelerator combines special purpose units, such as a high-speed device evaluator, with a fully programmable general-purpose processor. The specialized processors offer extremely high speed for performance-critical parts of the simulation. The general-purpose processors are optimized for compiled electrical simulation, and use a very long instruction word (VLIW) architecture. The network solution is compiled into VLIW code. The author concentrates on those features of the machine that are designed for circuit simulation algorithms, such as SPICE. A simplified example is used to expose the hardware and software techniques used to attack the problem, and estimate the performance improvement due to each technique.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132458706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A number of techniques are presented for the construction and ordering of routing channels for building-block layout. Before the routing channels are defined, the placement is modified so that proper routing space is assigned between the circuit blocks. A channel graph is then constructed on which the global routing will be performed. After the global routing a feasible routing order is assigned to the channels., In contrast to other approaches, the algorithms use both the geometrical data (the placement) and the topological data (the connectivity) to decide which channel structure should be chosen from the feasible set.<>
{"title":"Connectivity biased channel construction and ordering for building-block layout","authors":"H. Cai","doi":"10.1109/DAC.1988.14816","DOIUrl":"https://doi.org/10.1109/DAC.1988.14816","url":null,"abstract":"A number of techniques are presented for the construction and ordering of routing channels for building-block layout. Before the routing channels are defined, the placement is modified so that proper routing space is assigned between the circuit blocks. A channel graph is then constructed on which the global routing will be performed. After the global routing a feasible routing order is assigned to the channels., In contrast to other approaches, the algorithms use both the geometrical data (the placement) and the topological data (the connectivity) to decide which channel structure should be chosen from the feasible set.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128285416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An approach for timing simulation of bipolar ECL (emitter-coupled-logic) digital circuits is described. The approach is based on the development of a switch-level model of the transistor and on the representation of the circuit by a switch graph. The circuit is partitioned into subcircuits, and symbolic logic expressions are generated which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions. Timing information is computed using an analytical delay model which relates outputs of a subcircuit to its input waveforms. The model includes the effects of the transistor SPICE parameter model as well as the circuit parameters. The combination of the switch-level graph model and the delay model provides fast and accurate timing simulation of ECL circuits. In addition, the switch-graph model provides a unified way for simulating BIMOS circuits.<>
{"title":"Delay modeling and timing of bipolar digital circuits","authors":"D. Saab, A. Yang, I. Hajj","doi":"10.1109/DAC.1988.14772","DOIUrl":"https://doi.org/10.1109/DAC.1988.14772","url":null,"abstract":"An approach for timing simulation of bipolar ECL (emitter-coupled-logic) digital circuits is described. The approach is based on the development of a switch-level model of the transistor and on the representation of the circuit by a switch graph. The circuit is partitioned into subcircuits, and symbolic logic expressions are generated which represent the logic states of the nodes in terms of subcircuit inputs and initial conditions. Timing information is computed using an analytical delay model which relates outputs of a subcircuit to its input waveforms. The model includes the effects of the transistor SPICE parameter model as well as the circuit parameters. The combination of the switch-level graph model and the delay model provides fast and accurate timing simulation of ECL circuits. In addition, the switch-graph model provides a unified way for simulating BIMOS circuits.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"3 23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134421559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A program for automatic extraction of a gate-level description from a transistor-level description based on the layout of a CMOS VLSI circuit is presented. The extraction algorithm combines transistors to gates to arbitrary complexity without the help of any cell library. The resulting gate-level description provides the input for a digital logic simulator for further investigations.<>
{"title":"LOGEX-an automatic logic extractor from transistor to gate level for CMOS technology","authors":"M. Boehner","doi":"10.1109/DAC.1988.14809","DOIUrl":"https://doi.org/10.1109/DAC.1988.14809","url":null,"abstract":"A program for automatic extraction of a gate-level description from a transistor-level description based on the layout of a CMOS VLSI circuit is presented. The extraction algorithm combines transistors to gates to arbitrary complexity without the help of any cell library. The resulting gate-level description provides the input for a digital logic simulator for further investigations.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132947918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present a self-learning algorithm using a dynamic testability measure to accelerate test generation. They introduce the concepts of full-logic-value label-backward implication, dependent backtrack, and K-limited backtracks. Results indicating a high fault coverage are presented for ten benchmark combinational circuits.<>
{"title":"DYTEST: a self-learning algorithm using dynamic testability measures to accelerate test generation","authors":"W. Mao, M. Ciletti","doi":"10.1109/DAC.1988.14822","DOIUrl":"https://doi.org/10.1109/DAC.1988.14822","url":null,"abstract":"The authors present a self-learning algorithm using a dynamic testability measure to accelerate test generation. They introduce the concepts of full-logic-value label-backward implication, dependent backtrack, and K-limited backtracks. Results indicating a high fault coverage are presented for ten benchmark combinational circuits.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133181510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pearl is a timing analyzer that has been used to verify both full-custom VLSI and gate array designs. Rather than verify that a design meets a given clock timing, Pearl automatically determines the minimum error-free clock period and duty cycles. The author describes the mechanism used to determine the timing relationship each node in the circuit has with respect to the clock edges. He then shows how these dependencies, together with the setup and hold time requirements of latches and registers in the circuit, are used to formulate timing constraints between the clock edges. These timing requirements are solved using a linear programming algorithm to determine the minimum time of each clock edge. The algorithm is first described for the case of a circuit composed of functional models and then applied to MOS switch circuits. The author also describes transistor signal-flow direction rules for CMOS circuits used to eliminate false paths.<>
{"title":"Pearl: a CMOS timing analyzer","authors":"J. J. Cherry","doi":"10.1109/DAC.1988.14750","DOIUrl":"https://doi.org/10.1109/DAC.1988.14750","url":null,"abstract":"Pearl is a timing analyzer that has been used to verify both full-custom VLSI and gate array designs. Rather than verify that a design meets a given clock timing, Pearl automatically determines the minimum error-free clock period and duty cycles. The author describes the mechanism used to determine the timing relationship each node in the circuit has with respect to the clock edges. He then shows how these dependencies, together with the setup and hold time requirements of latches and registers in the circuit, are used to formulate timing constraints between the clock edges. These timing requirements are solved using a linear programming algorithm to determine the minimum time of each clock edge. The algorithm is first described for the case of a circuit composed of functional models and then applied to MOS switch circuits. The author also describes transistor signal-flow direction rules for CMOS circuits used to eliminate false paths.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121232129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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