A method for efficient complication of circuits which is used in a commercially available fault grader is described. Data structures and algorithms are presented which can be used in processing circuits in a textural or schematic format. Performance is documented by showing the results for various circuits. It is shown that on the average, the compiler can process 2000 lines of CDL text per minute, and the loader and flattener process 10300 flattened nets per minute. These times show that incremental circuit changes can be performed in analysis tools without using a separate complication procedure. This efficiency is possible by creating data structures which require minimal manipulation and by the organization of data in the circuit library. Memory utilization is kept to a minimum by optimizing the location of circuit information on the data structures.<>
{"title":"Circuit compilers don't have to be slow","authors":"William C. Diss","doi":"10.1109/DAC.1988.14829","DOIUrl":"https://doi.org/10.1109/DAC.1988.14829","url":null,"abstract":"A method for efficient complication of circuits which is used in a commercially available fault grader is described. Data structures and algorithms are presented which can be used in processing circuits in a textural or schematic format. Performance is documented by showing the results for various circuits. It is shown that on the average, the compiler can process 2000 lines of CDL text per minute, and the loader and flattener process 10300 flattened nets per minute. These times show that incremental circuit changes can be performed in analysis tools without using a separate complication procedure. This efficiency is possible by creating data structures which require minimal manipulation and by the organization of data in the circuit library. Memory utilization is kept to a minimum by optimizing the location of circuit information on the data structures.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126597351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present the Irouter, an interactive maze router for the Magic IC layout editor that takes hints. The Irouter is a flexible tool intended to be useful wherever tight or unusual constraints do not permit automatic routing. It has already been used in the layout of an 80000-transistor CMOS chip and is currently being used to route the control signals of a 100000 transistor, high-performance FPU (floating-point unit) chip. Several novel ideas for maze routing have been developed in the Irouter. Hint layers permit the user to map out the general path of a route and pull the route in desired directions, while leaving details to the router. The gross structure of the layout is preprocessed to facilitate accurate estimates of cost to completion during routing and hence effective pruning of misdirected partial routes. A windowed search strategy slowly shifts the focus from the start point towards the goal. This permits the consideration of alternatives at all stages of routing without blowing up into an exhaustive search.<>
{"title":"An interactive maze router with hints","authors":"Michael H. Arnold, Walter S. Scott","doi":"10.1109/DAC.1988.14840","DOIUrl":"https://doi.org/10.1109/DAC.1988.14840","url":null,"abstract":"The authors present the Irouter, an interactive maze router for the Magic IC layout editor that takes hints. The Irouter is a flexible tool intended to be useful wherever tight or unusual constraints do not permit automatic routing. It has already been used in the layout of an 80000-transistor CMOS chip and is currently being used to route the control signals of a 100000 transistor, high-performance FPU (floating-point unit) chip. Several novel ideas for maze routing have been developed in the Irouter. Hint layers permit the user to map out the general path of a route and pull the route in desired directions, while leaving details to the router. The gross structure of the layout is preprocessed to facilitate accurate estimates of cost to completion during routing and hence effective pruning of misdirected partial routes. A windowed search strategy slowly shifts the focus from the start point towards the goal. This permits the consideration of alternatives at all stages of routing without blowing up into an exhaustive search.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130629972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Beece, George Deibert, G. Papp, Francis J. Villante
A description is given of IBM's engineering verification engine, EVE, a special-purpose, highly-parallel programmable machine for the simulation of computer logic. EVE, which is based on the architecture of the Yorktown simulation engine, can simulate two million gates at a speed of more than two billion gate evaluations per second, far beyond the capabilities of existing software simulators. An overview is given of the EVE architecture, hardware and software, and some current applications are described.<>
{"title":"The IBM engineering verification engine","authors":"D. Beece, George Deibert, G. Papp, Francis J. Villante","doi":"10.1109/DAC.1988.14761","DOIUrl":"https://doi.org/10.1109/DAC.1988.14761","url":null,"abstract":"A description is given of IBM's engineering verification engine, EVE, a special-purpose, highly-parallel programmable machine for the simulation of computer logic. EVE, which is based on the architecture of the Yorktown simulation engine, can simulate two million gates at a speed of more than two billion gate evaluations per second, far beyond the capabilities of existing software simulators. An overview is given of the EVE architecture, hardware and software, and some current applications are described.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132014370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of a suite of utilities for manipulating VHDL (VHSIC Hardware Description Language) designs that has been developed and integrated into a CAD (Computer-aided design) system. The system is a tightly integrated environment supporting the sharing of design information between heterogeneous tools, using an underlying knowledge base built on top of an object-orientated distributed database. The VHDL utilities include an editing mode to provide syntactic assistance for writing VHDL an analyzer to produce intermediate representations, a compiler to translate the intermediate representations into directly executable Lisp functions, an elaborator for generating simulation models from complete design, and a simulator for these models. Experimentation, continued development, and several important extensions to the CAD System VHDL utilities are in progress.<>
{"title":"The role of VHDL in the MCC CAD system","authors":"R. D. Acosta, Mark Alexandre, Gary Imken, B. Read","doi":"10.1109/DAC.1988.14731","DOIUrl":"https://doi.org/10.1109/DAC.1988.14731","url":null,"abstract":"A description is given of a suite of utilities for manipulating VHDL (VHSIC Hardware Description Language) designs that has been developed and integrated into a CAD (Computer-aided design) system. The system is a tightly integrated environment supporting the sharing of design information between heterogeneous tools, using an underlying knowledge base built on top of an object-orientated distributed database. The VHDL utilities include an editing mode to provide syntactic assistance for writing VHDL an analyzer to produce intermediate representations, a compiler to translate the intermediate representations into directly executable Lisp functions, an elaborator for generating simulation models from complete design, and a simulator for these models. Experimentation, continued development, and several important extensions to the CAD System VHDL utilities are in progress.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132836070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A data structure for representing the structure of VLSI circuits and basic operations for manipulating this data structure are presented. Its features include conceptual integrity, rich expressive power, and high extensibility. This device forms the nucleus of a design analysis and synthesis system which has been used to design several major chips.<>
{"title":"A structural representation for VLSI design","authors":"R. Barth, B. Serlet","doi":"10.1109/DAC.1988.14764","DOIUrl":"https://doi.org/10.1109/DAC.1988.14764","url":null,"abstract":"A data structure for representing the structure of VLSI circuits and basic operations for manipulating this data structure are presented. Its features include conceptual integrity, rich expressive power, and high extensibility. This device forms the nucleus of a design analysis and synthesis system which has been used to design several major chips.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132895841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
VHDL (VHSIC Hardware Description Language) is such an extremely flexible and versatile language, that the language reference documentation is not sufficient to ensure that models written by one hardware designer will be compatible with another's models. What is required is a set of VHDL modeling conventions and standard packages which structure the usage of VHDL modeling approaches. The issues inherent in VHDL in regards to model compatibility are discussed, and a number of solutions to this problem.<>
{"title":"VHDL: a call for standards","authors":"David R. Coelho","doi":"10.1109/DAC.1988.14732","DOIUrl":"https://doi.org/10.1109/DAC.1988.14732","url":null,"abstract":"VHDL (VHSIC Hardware Description Language) is such an extremely flexible and versatile language, that the language reference documentation is not sufficient to ensure that models written by one hardware designer will be compatible with another's models. What is required is a set of VHDL modeling conventions and standard packages which structure the usage of VHDL modeling approaches. The issues inherent in VHDL in regards to model compatibility are discussed, and a number of solutions to this problem.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117181681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A model for MOS transistors suitable for logic simulation of VLSI circuits is presented based on the concept of a dynamically directed switch (DDS). In this model, transistors are represented by directed edges in a graph that are capable of changing their direction dynamically. A distributed algorithm for switch-level simulation is presented that is based on an incremental graph algorithm in which edge and vertex labels are updated as a consequence of circuit events. The result is a switch-level algorithm that runs at speeds approaching gate-level logic simulators, while dealing with all the features associated with switch-level simulation: bidirectional signal flow, ratioed logic, RC-tree timing, and correct handling of transistor signal propagation in the presence of unknown signals. The implementation of this algorithm in the Lsim mixed-mode analog and digital simulator is described, and some results and examples are presented.<>
{"title":"A dynamically-directed switch model for MOS logic simulation","authors":"Dan Adler","doi":"10.1109/DAC.1988.14807","DOIUrl":"https://doi.org/10.1109/DAC.1988.14807","url":null,"abstract":"A model for MOS transistors suitable for logic simulation of VLSI circuits is presented based on the concept of a dynamically directed switch (DDS). In this model, transistors are represented by directed edges in a graph that are capable of changing their direction dynamically. A distributed algorithm for switch-level simulation is presented that is based on an incremental graph algorithm in which edge and vertex labels are updated as a consequence of circuit events. The result is a switch-level algorithm that runs at speeds approaching gate-level logic simulators, while dealing with all the features associated with switch-level simulation: bidirectional signal flow, ratioed logic, RC-tree timing, and correct handling of transistor signal propagation in the presence of unknown signals. The implementation of this algorithm in the Lsim mixed-mode analog and digital simulator is described, and some results and examples are presented.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122111703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Takashima, A. Ikeuchi, S. Kojima, Toshikazu Tanaka, T. Saitou, Jun-ichi Sakata
A circuit comparison system is described which compares two networks and points out inconsistencies. A novel approach is used to handle functionally isomorphic circuits which most conventional programs can not handle. Three techniques are included: network reduction, graph isomorphism-based comparison, and rule-based functional isomorphism checking for inconsistencies. The system is efficient even for large networks and can eliminate false errors in flexible manner.<>
{"title":"A circuit comparison system with rule-based functional isomorphism checking","authors":"M. Takashima, A. Ikeuchi, S. Kojima, Toshikazu Tanaka, T. Saitou, Jun-ichi Sakata","doi":"10.1109/DAC.1988.14808","DOIUrl":"https://doi.org/10.1109/DAC.1988.14808","url":null,"abstract":"A circuit comparison system is described which compares two networks and points out inconsistencies. A novel approach is used to handle functionally isomorphic circuits which most conventional programs can not handle. Three techniques are included: network reduction, graph isomorphism-based comparison, and rule-based functional isomorphism checking for inconsistencies. The system is efficient even for large networks and can eliminate false errors in flexible manner.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114912393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The global effect problem is introduced in the context of adapting min-cut partitioning for min-cut placement. A simplified version of the problem is solved in linear time by using a novel algorithm called the min-cut shuffle. A detailed analysis and implementation for the algorithm is presented.<>
{"title":"The min-cut shuffle: toward a solution for the global effect problem of min-cut placement","authors":"I. Bhandari, Mark Hirsch, D. Siewiorek","doi":"10.1109/DAC.1988.14842","DOIUrl":"https://doi.org/10.1109/DAC.1988.14842","url":null,"abstract":"The global effect problem is introduced in the context of adapting min-cut partitioning for min-cut placement. A simplified version of the problem is solved in linear time by using a novel algorithm called the min-cut shuffle. A detailed analysis and implementation for the algorithm is presented.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114562952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors' layout area estimates are very close to those of manually laid out modules.<>
{"title":"A module area estimator for VLSI layout","authors":"Xinghao Chen, M. Bushnell","doi":"10.1109/DAC.1988.14734","DOIUrl":"https://doi.org/10.1109/DAC.1988.14734","url":null,"abstract":"An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors' layout area estimates are very close to those of manually laid out modules.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"39 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120821926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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