A method for efficient complication of circuits which is used in a commercially available fault grader is described. Data structures and algorithms are presented which can be used in processing circuits in a textural or schematic format. Performance is documented by showing the results for various circuits. It is shown that on the average, the compiler can process 2000 lines of CDL text per minute, and the loader and flattener process 10300 flattened nets per minute. These times show that incremental circuit changes can be performed in analysis tools without using a separate complication procedure. This efficiency is possible by creating data structures which require minimal manipulation and by the organization of data in the circuit library. Memory utilization is kept to a minimum by optimizing the location of circuit information on the data structures.<>
{"title":"Circuit compilers don't have to be slow","authors":"William C. Diss","doi":"10.1109/DAC.1988.14829","DOIUrl":"https://doi.org/10.1109/DAC.1988.14829","url":null,"abstract":"A method for efficient complication of circuits which is used in a commercially available fault grader is described. Data structures and algorithms are presented which can be used in processing circuits in a textural or schematic format. Performance is documented by showing the results for various circuits. It is shown that on the average, the compiler can process 2000 lines of CDL text per minute, and the loader and flattener process 10300 flattened nets per minute. These times show that incremental circuit changes can be performed in analysis tools without using a separate complication procedure. This efficiency is possible by creating data structures which require minimal manipulation and by the organization of data in the circuit library. Memory utilization is kept to a minimum by optimizing the location of circuit information on the data structures.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126597351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The authors present the Irouter, an interactive maze router for the Magic IC layout editor that takes hints. The Irouter is a flexible tool intended to be useful wherever tight or unusual constraints do not permit automatic routing. It has already been used in the layout of an 80000-transistor CMOS chip and is currently being used to route the control signals of a 100000 transistor, high-performance FPU (floating-point unit) chip. Several novel ideas for maze routing have been developed in the Irouter. Hint layers permit the user to map out the general path of a route and pull the route in desired directions, while leaving details to the router. The gross structure of the layout is preprocessed to facilitate accurate estimates of cost to completion during routing and hence effective pruning of misdirected partial routes. A windowed search strategy slowly shifts the focus from the start point towards the goal. This permits the consideration of alternatives at all stages of routing without blowing up into an exhaustive search.<>
{"title":"An interactive maze router with hints","authors":"Michael H. Arnold, Walter S. Scott","doi":"10.1109/DAC.1988.14840","DOIUrl":"https://doi.org/10.1109/DAC.1988.14840","url":null,"abstract":"The authors present the Irouter, an interactive maze router for the Magic IC layout editor that takes hints. The Irouter is a flexible tool intended to be useful wherever tight or unusual constraints do not permit automatic routing. It has already been used in the layout of an 80000-transistor CMOS chip and is currently being used to route the control signals of a 100000 transistor, high-performance FPU (floating-point unit) chip. Several novel ideas for maze routing have been developed in the Irouter. Hint layers permit the user to map out the general path of a route and pull the route in desired directions, while leaving details to the router. The gross structure of the layout is preprocessed to facilitate accurate estimates of cost to completion during routing and hence effective pruning of misdirected partial routes. A windowed search strategy slowly shifts the focus from the start point towards the goal. This permits the consideration of alternatives at all stages of routing without blowing up into an exhaustive search.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130629972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Beece, George Deibert, G. Papp, Francis J. Villante
A description is given of IBM's engineering verification engine, EVE, a special-purpose, highly-parallel programmable machine for the simulation of computer logic. EVE, which is based on the architecture of the Yorktown simulation engine, can simulate two million gates at a speed of more than two billion gate evaluations per second, far beyond the capabilities of existing software simulators. An overview is given of the EVE architecture, hardware and software, and some current applications are described.<>
{"title":"The IBM engineering verification engine","authors":"D. Beece, George Deibert, G. Papp, Francis J. Villante","doi":"10.1109/DAC.1988.14761","DOIUrl":"https://doi.org/10.1109/DAC.1988.14761","url":null,"abstract":"A description is given of IBM's engineering verification engine, EVE, a special-purpose, highly-parallel programmable machine for the simulation of computer logic. EVE, which is based on the architecture of the Yorktown simulation engine, can simulate two million gates at a speed of more than two billion gate evaluations per second, far beyond the capabilities of existing software simulators. An overview is given of the EVE architecture, hardware and software, and some current applications are described.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132014370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A description is given of a suite of utilities for manipulating VHDL (VHSIC Hardware Description Language) designs that has been developed and integrated into a CAD (Computer-aided design) system. The system is a tightly integrated environment supporting the sharing of design information between heterogeneous tools, using an underlying knowledge base built on top of an object-orientated distributed database. The VHDL utilities include an editing mode to provide syntactic assistance for writing VHDL an analyzer to produce intermediate representations, a compiler to translate the intermediate representations into directly executable Lisp functions, an elaborator for generating simulation models from complete design, and a simulator for these models. Experimentation, continued development, and several important extensions to the CAD System VHDL utilities are in progress.<>
{"title":"The role of VHDL in the MCC CAD system","authors":"R. D. Acosta, Mark Alexandre, Gary Imken, B. Read","doi":"10.1109/DAC.1988.14731","DOIUrl":"https://doi.org/10.1109/DAC.1988.14731","url":null,"abstract":"A description is given of a suite of utilities for manipulating VHDL (VHSIC Hardware Description Language) designs that has been developed and integrated into a CAD (Computer-aided design) system. The system is a tightly integrated environment supporting the sharing of design information between heterogeneous tools, using an underlying knowledge base built on top of an object-orientated distributed database. The VHDL utilities include an editing mode to provide syntactic assistance for writing VHDL an analyzer to produce intermediate representations, a compiler to translate the intermediate representations into directly executable Lisp functions, an elaborator for generating simulation models from complete design, and a simulator for these models. Experimentation, continued development, and several important extensions to the CAD System VHDL utilities are in progress.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132836070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A data structure for representing the structure of VLSI circuits and basic operations for manipulating this data structure are presented. Its features include conceptual integrity, rich expressive power, and high extensibility. This device forms the nucleus of a design analysis and synthesis system which has been used to design several major chips.<>
{"title":"A structural representation for VLSI design","authors":"R. Barth, B. Serlet","doi":"10.1109/DAC.1988.14764","DOIUrl":"https://doi.org/10.1109/DAC.1988.14764","url":null,"abstract":"A data structure for representing the structure of VLSI circuits and basic operations for manipulating this data structure are presented. Its features include conceptual integrity, rich expressive power, and high extensibility. This device forms the nucleus of a design analysis and synthesis system which has been used to design several major chips.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132895841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors' layout area estimates are very close to those of manually laid out modules.<>
{"title":"A module area estimator for VLSI layout","authors":"Xinghao Chen, M. Bushnell","doi":"10.1109/DAC.1988.14734","DOIUrl":"https://doi.org/10.1109/DAC.1988.14734","url":null,"abstract":"An efficient module area estimator for VLSI chip layout has been developed to reduce the number of design iterations required to develop a chip floor plan. Module area is estimated for standard-cell and full-custom layout methodologies. The structure of the estimator and its algorithms are discussed. The authors' layout area estimates are very close to those of manually laid out modules.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"39 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120821926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A tool is described for constructing the connectivity between components given a state graph into which the components are to be mapped. Examples taken from previous papers in the field are used to demonstrate this connectivity binder. The results point to heuristics that are used to generate solutions to the problem. Questions addressed include how much of the state graph must be considered at one time to give reasonable results and how the search space can be prune to achieve good solutions quicker. The code for this project is written in C and runs under 4.2 BSD Unix.<>
{"title":"Splicer: a heuristic approach to connectivity binding","authors":"B. Pangrle","doi":"10.1109/DAC.1988.14812","DOIUrl":"https://doi.org/10.1109/DAC.1988.14812","url":null,"abstract":"A tool is described for constructing the connectivity between components given a state graph into which the components are to be mapped. Examples taken from previous papers in the field are used to demonstrate this connectivity binder. The results point to heuristics that are used to generate solutions to the problem. Questions addressed include how much of the state graph must be considered at one time to give reasonable results and how the search space can be prune to achieve good solutions quicker. The code for this project is written in C and runs under 4.2 BSD Unix.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122999602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel via minimization approach is presented for two-layer routing of printed-circuit boards and VLSI chips. The authors have analyzed and characterized different aspects of the problem and derived an equivalent graph model for the problem from the linear-programming formulation. Based on the analysis of their unified formulation, the authors pose a practical heuristic algorithm. The algorithm can handle both grid-based and gridless routing. Also, an arbitrary number of wires is allowed to intersect at a via, and both Manhattan and knock-knee routings are allowed.<>
{"title":"The constrained via minimization problem for PCB and VLSI design","authors":"X. Xiong, E. Kuh","doi":"10.1109/DAC.1988.14818","DOIUrl":"https://doi.org/10.1109/DAC.1988.14818","url":null,"abstract":"A novel via minimization approach is presented for two-layer routing of printed-circuit boards and VLSI chips. The authors have analyzed and characterized different aspects of the problem and derived an equivalent graph model for the problem from the linear-programming formulation. Based on the analysis of their unified formulation, the authors pose a practical heuristic algorithm. The algorithm can handle both grid-based and gridless routing. Also, an arbitrary number of wires is allowed to intersect at a via, and both Manhattan and knock-knee routings are allowed.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124809186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Accurate and efficient expected current is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A pattern-independent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts are presented which allow an efficient and accurate estimation of expected current waveforms. They are: probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis. This approach is considerably faster than traditional methods and yields comparable results.<>
{"title":"Pattern-independent current estimation for reliability analysis of CMOS circuits","authors":"R. Burch, F. Najm, Ping Yang, D. Hocevar","doi":"10.1109/DAC.1988.14773","DOIUrl":"https://doi.org/10.1109/DAC.1988.14773","url":null,"abstract":"Accurate and efficient expected current is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A pattern-independent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts are presented which allow an efficient and accurate estimation of expected current waveforms. They are: probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis. This approach is considerably faster than traditional methods and yields comparable results.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126457915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A discussion is presented of the problem of selecting an optimal implementation for each building block so that the area of the final layout is minimised. A polynomial algorithm that solves this problem for slicing floorplans was presented elsewhere, and it has been proved that for general (nonslicing) floorplans the problem is NP-complete. The authors suggest a branch-and-bound algorithm which proves to be very efficient and can handle successfully large general nonslicing floorplans. They show also how the nonslicing and slicing algorithms can be combined to handle very large general floorplans efficiently.<>
{"title":"Optimal aspect ratios of building blocks in VLSI","authors":"S. Wimer, I. Koren, I. Cederbaum","doi":"10.1109/DAC.1988.14736","DOIUrl":"https://doi.org/10.1109/DAC.1988.14736","url":null,"abstract":"A discussion is presented of the problem of selecting an optimal implementation for each building block so that the area of the final layout is minimised. A polynomial algorithm that solves this problem for slicing floorplans was presented elsewhere, and it has been proved that for general (nonslicing) floorplans the problem is NP-complete. The authors suggest a branch-and-bound algorithm which proves to be very efficient and can handle successfully large general nonslicing floorplans. They show also how the nonslicing and slicing algorithms can be combined to handle very large general floorplans efficiently.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116986744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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