M. Takashima, A. Ikeuchi, S. Kojima, Toshikazu Tanaka, T. Saitou, Jun-ichi Sakata
A circuit comparison system is described which compares two networks and points out inconsistencies. A novel approach is used to handle functionally isomorphic circuits which most conventional programs can not handle. Three techniques are included: network reduction, graph isomorphism-based comparison, and rule-based functional isomorphism checking for inconsistencies. The system is efficient even for large networks and can eliminate false errors in flexible manner.<>
{"title":"A circuit comparison system with rule-based functional isomorphism checking","authors":"M. Takashima, A. Ikeuchi, S. Kojima, Toshikazu Tanaka, T. Saitou, Jun-ichi Sakata","doi":"10.1109/DAC.1988.14808","DOIUrl":"https://doi.org/10.1109/DAC.1988.14808","url":null,"abstract":"A circuit comparison system is described which compares two networks and points out inconsistencies. A novel approach is used to handle functionally isomorphic circuits which most conventional programs can not handle. Three techniques are included: network reduction, graph isomorphism-based comparison, and rule-based functional isomorphism checking for inconsistencies. The system is efficient even for large networks and can eliminate false errors in flexible manner.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114912393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The author introduces timing requirement analysis and two algorithms for its implementation. The first uses a prioritization scheme to generate an approximate solution, which may result in violation. The second uses a depth-first search to find a solution that does not result in violation. Together, these algorithms are useful for timing-requirement analysis and generation and in pattern-timing generation.<>
{"title":"Algorithms for timing requirement analysis and generation","authors":"S. K. Sherman","doi":"10.1109/DAC.1988.14851","DOIUrl":"https://doi.org/10.1109/DAC.1988.14851","url":null,"abstract":"The author introduces timing requirement analysis and two algorithms for its implementation. The first uses a prioritization scheme to generate an approximate solution, which may result in violation. The second uses a depth-first search to find a solution that does not result in violation. Together, these algorithms are useful for timing-requirement analysis and generation and in pattern-timing generation.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116945117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
VHDL (VHSIC Hardware Description Language) is such an extremely flexible and versatile language, that the language reference documentation is not sufficient to ensure that models written by one hardware designer will be compatible with another's models. What is required is a set of VHDL modeling conventions and standard packages which structure the usage of VHDL modeling approaches. The issues inherent in VHDL in regards to model compatibility are discussed, and a number of solutions to this problem.<>
{"title":"VHDL: a call for standards","authors":"David R. Coelho","doi":"10.1109/DAC.1988.14732","DOIUrl":"https://doi.org/10.1109/DAC.1988.14732","url":null,"abstract":"VHDL (VHSIC Hardware Description Language) is such an extremely flexible and versatile language, that the language reference documentation is not sufficient to ensure that models written by one hardware designer will be compatible with another's models. What is required is a set of VHDL modeling conventions and standard packages which structure the usage of VHDL modeling approaches. The issues inherent in VHDL in regards to model compatibility are discussed, and a number of solutions to this problem.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117181681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Bergstraesser, J. Gessner, K. Hafner, S. Wallstab
A design environment supporting processor synthesis in data-path style is presented. The programming model of a processor described in Common Lisp is transformed into a hardware structure by tools integrated into this environment. The generation of alternative designs is supported by the interactive graphical manipulation of behaviour and hardware structure representations and their correspondences. The synthesis procedure is explained using an example.<>
{"title":"SMART: tools and methods for synthesis of VLSI chips with processor architecture","authors":"T. Bergstraesser, J. Gessner, K. Hafner, S. Wallstab","doi":"10.1109/DAC.1988.14836","DOIUrl":"https://doi.org/10.1109/DAC.1988.14836","url":null,"abstract":"A design environment supporting processor synthesis in data-path style is presented. The programming model of a processor described in Common Lisp is transformed into a hardware structure by tools integrated into this environment. The generation of alternative designs is supported by the interactive graphical manipulation of behaviour and hardware structure representations and their correspondences. The synthesis procedure is explained using an example.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121572034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A model for MOS transistors suitable for logic simulation of VLSI circuits is presented based on the concept of a dynamically directed switch (DDS). In this model, transistors are represented by directed edges in a graph that are capable of changing their direction dynamically. A distributed algorithm for switch-level simulation is presented that is based on an incremental graph algorithm in which edge and vertex labels are updated as a consequence of circuit events. The result is a switch-level algorithm that runs at speeds approaching gate-level logic simulators, while dealing with all the features associated with switch-level simulation: bidirectional signal flow, ratioed logic, RC-tree timing, and correct handling of transistor signal propagation in the presence of unknown signals. The implementation of this algorithm in the Lsim mixed-mode analog and digital simulator is described, and some results and examples are presented.<>
{"title":"A dynamically-directed switch model for MOS logic simulation","authors":"Dan Adler","doi":"10.1109/DAC.1988.14807","DOIUrl":"https://doi.org/10.1109/DAC.1988.14807","url":null,"abstract":"A model for MOS transistors suitable for logic simulation of VLSI circuits is presented based on the concept of a dynamically directed switch (DDS). In this model, transistors are represented by directed edges in a graph that are capable of changing their direction dynamically. A distributed algorithm for switch-level simulation is presented that is based on an incremental graph algorithm in which edge and vertex labels are updated as a consequence of circuit events. The result is a switch-level algorithm that runs at speeds approaching gate-level logic simulators, while dealing with all the features associated with switch-level simulation: bidirectional signal flow, ratioed logic, RC-tree timing, and correct handling of transistor signal propagation in the presence of unknown signals. The implementation of this algorithm in the Lsim mixed-mode analog and digital simulator is described, and some results and examples are presented.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122111703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An improved algorithm is presented for identifying redundant faults and finding tests for hard faults in combination circuits. A concurrent approach is proposed which is based on the concepts of functional decomposition, explicit representation of fanout stems, and the Boolean difference. The data structure used is the binary decision diagram. The algorithm operates as a back end to test generators which use random patterns or heuristics or a combination of the two.<>
{"title":"CATAPULT: concurrent automatic testing allowing parallelization and using limited topology","authors":"R. Gaede, D. Ross, M. R. Mercer, K. Butler","doi":"10.1109/DAC.1988.14823","DOIUrl":"https://doi.org/10.1109/DAC.1988.14823","url":null,"abstract":"An improved algorithm is presented for identifying redundant faults and finding tests for hard faults in combination circuits. A concurrent approach is proposed which is based on the concepts of functional decomposition, explicit representation of fanout stems, and the Boolean difference. The data structure used is the binary decision diagram. The algorithm operates as a back end to test generators which use random patterns or heuristics or a combination of the two.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128063956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fast and easily parallelizable global routing algorithm for standard cells and its parallel implementation are presented. LocusRoute is meant to be used as the cost function for a placement algorithm, and so this context constrains the structure of the global routing algorithm and its parallel implementation. The router is based on enumerating a subset of all two-bend routes between two points, and results in 16% to 37% fewer total number of tracks than the Timber Wolf global router for standard cells. It is comparable in quality to a maze router and an industrial router, but is ten times or more faster. Three approaches to parallelizing the router are implemented: wire-by-wire parallelism, segment-by-segment and route-by-route. Two of these approaches achieve significant speedup; route-by-route achieves up to 4.6 using eight processors, and wire-by-wire achieves from 5.8 to 7.6 on eight processors.<>
{"title":"LocusRoute: a parallel global router for standard cells","authors":"Jonathan Rose","doi":"10.1109/DAC.1988.14757","DOIUrl":"https://doi.org/10.1109/DAC.1988.14757","url":null,"abstract":"A fast and easily parallelizable global routing algorithm for standard cells and its parallel implementation are presented. LocusRoute is meant to be used as the cost function for a placement algorithm, and so this context constrains the structure of the global routing algorithm and its parallel implementation. The router is based on enumerating a subset of all two-bend routes between two points, and results in 16% to 37% fewer total number of tracks than the Timber Wolf global router for standard cells. It is comparable in quality to a maze router and an industrial router, but is ten times or more faster. Three approaches to parallelizing the router are implemented: wire-by-wire parallelism, segment-by-segment and route-by-route. Two of these approaches achieve significant speedup; route-by-route achieves up to 4.6 using eight processors, and wire-by-wire achieves from 5.8 to 7.6 on eight processors.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"336 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114235615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The global effect problem is introduced in the context of adapting min-cut partitioning for min-cut placement. A simplified version of the problem is solved in linear time by using a novel algorithm called the min-cut shuffle. A detailed analysis and implementation for the algorithm is presented.<>
{"title":"The min-cut shuffle: toward a solution for the global effect problem of min-cut placement","authors":"I. Bhandari, Mark Hirsch, D. Siewiorek","doi":"10.1109/DAC.1988.14842","DOIUrl":"https://doi.org/10.1109/DAC.1988.14842","url":null,"abstract":"The global effect problem is introduced in the context of adapting min-cut partitioning for min-cut placement. A simplified version of the problem is solved in linear time by using a novel algorithm called the min-cut shuffle. A detailed analysis and implementation for the algorithm is presented.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114562952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A parallel algorithm is proposed for the problem of channel and switchbox routing in the design of VLSI chips. The algorithm is suitable for implementation on a shared-memory multiprocessor environment. The approach does not impose restrictions on the channel type (such as fixed or variable channel widths) and the number of available layers. The algorithm contains three major phases: (1) dividing the channel into several regions by selecting some columns, (2) assigning tracks to nets of the selected columns, and (3) assigning tracks to nets of the columns in each region.<>
{"title":"Parallel channel routing","authors":"M. Zargham","doi":"10.1109/DAC.1988.14747","DOIUrl":"https://doi.org/10.1109/DAC.1988.14747","url":null,"abstract":"A parallel algorithm is proposed for the problem of channel and switchbox routing in the design of VLSI chips. The algorithm is suitable for implementation on a shared-memory multiprocessor environment. The approach does not impose restrictions on the channel type (such as fixed or variable channel widths) and the number of available layers. The algorithm contains three major phases: (1) dividing the channel into several regions by selecting some columns, (2) assigning tracks to nets of the selected columns, and (3) assigning tracks to nets of the columns in each region.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133523712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A special-purpose database management system for VLSI design environment is presented. Besides supporting design data management and tools integration, the system provides lots of facilities for supporting fast development of efficient and powerful VLSI CAD tools. This system could simplify the task and reduce errors made in implementing an integrated VLSI design system.<>
{"title":"A database management system for a VLSI design system","authors":"Gwo-Dong Chen, T. Parng","doi":"10.1109/DAC.1988.14767","DOIUrl":"https://doi.org/10.1109/DAC.1988.14767","url":null,"abstract":"A special-purpose database management system for VLSI design environment is presented. Besides supporting design data management and tools integration, the system provides lots of facilities for supporting fast development of efficient and powerful VLSI CAD tools. This system could simplify the task and reduce errors made in implementing an integrated VLSI design system.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134218867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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