The author introduces timing requirement analysis and two algorithms for its implementation. The first uses a prioritization scheme to generate an approximate solution, which may result in violation. The second uses a depth-first search to find a solution that does not result in violation. Together, these algorithms are useful for timing-requirement analysis and generation and in pattern-timing generation.<>
{"title":"Algorithms for timing requirement analysis and generation","authors":"S. K. Sherman","doi":"10.1109/DAC.1988.14851","DOIUrl":"https://doi.org/10.1109/DAC.1988.14851","url":null,"abstract":"The author introduces timing requirement analysis and two algorithms for its implementation. The first uses a prioritization scheme to generate an approximate solution, which may result in violation. The second uses a depth-first search to find a solution that does not result in violation. Together, these algorithms are useful for timing-requirement analysis and generation and in pattern-timing generation.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116945117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A discussion is presented of the problem of selecting an optimal implementation for each building block so that the area of the final layout is minimised. A polynomial algorithm that solves this problem for slicing floorplans was presented elsewhere, and it has been proved that for general (nonslicing) floorplans the problem is NP-complete. The authors suggest a branch-and-bound algorithm which proves to be very efficient and can handle successfully large general nonslicing floorplans. They show also how the nonslicing and slicing algorithms can be combined to handle very large general floorplans efficiently.<>
{"title":"Optimal aspect ratios of building blocks in VLSI","authors":"S. Wimer, I. Koren, I. Cederbaum","doi":"10.1109/DAC.1988.14736","DOIUrl":"https://doi.org/10.1109/DAC.1988.14736","url":null,"abstract":"A discussion is presented of the problem of selecting an optimal implementation for each building block so that the area of the final layout is minimised. A polynomial algorithm that solves this problem for slicing floorplans was presented elsewhere, and it has been proved that for general (nonslicing) floorplans the problem is NP-complete. The authors suggest a branch-and-bound algorithm which proves to be very efficient and can handle successfully large general nonslicing floorplans. They show also how the nonslicing and slicing algorithms can be combined to handle very large general floorplans efficiently.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116986744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Bergstraesser, J. Gessner, K. Hafner, S. Wallstab
A design environment supporting processor synthesis in data-path style is presented. The programming model of a processor described in Common Lisp is transformed into a hardware structure by tools integrated into this environment. The generation of alternative designs is supported by the interactive graphical manipulation of behaviour and hardware structure representations and their correspondences. The synthesis procedure is explained using an example.<>
{"title":"SMART: tools and methods for synthesis of VLSI chips with processor architecture","authors":"T. Bergstraesser, J. Gessner, K. Hafner, S. Wallstab","doi":"10.1109/DAC.1988.14836","DOIUrl":"https://doi.org/10.1109/DAC.1988.14836","url":null,"abstract":"A design environment supporting processor synthesis in data-path style is presented. The programming model of a processor described in Common Lisp is transformed into a hardware structure by tools integrated into this environment. The generation of alternative designs is supported by the interactive graphical manipulation of behaviour and hardware structure representations and their correspondences. The synthesis procedure is explained using an example.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121572034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A tool is described for constructing the connectivity between components given a state graph into which the components are to be mapped. Examples taken from previous papers in the field are used to demonstrate this connectivity binder. The results point to heuristics that are used to generate solutions to the problem. Questions addressed include how much of the state graph must be considered at one time to give reasonable results and how the search space can be prune to achieve good solutions quicker. The code for this project is written in C and runs under 4.2 BSD Unix.<>
{"title":"Splicer: a heuristic approach to connectivity binding","authors":"B. Pangrle","doi":"10.1109/DAC.1988.14812","DOIUrl":"https://doi.org/10.1109/DAC.1988.14812","url":null,"abstract":"A tool is described for constructing the connectivity between components given a state graph into which the components are to be mapped. Examples taken from previous papers in the field are used to demonstrate this connectivity binder. The results point to heuristics that are used to generate solutions to the problem. Questions addressed include how much of the state graph must be considered at one time to give reasonable results and how the search space can be prune to achieve good solutions quicker. The code for this project is written in C and runs under 4.2 BSD Unix.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122999602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fast and easily parallelizable global routing algorithm for standard cells and its parallel implementation are presented. LocusRoute is meant to be used as the cost function for a placement algorithm, and so this context constrains the structure of the global routing algorithm and its parallel implementation. The router is based on enumerating a subset of all two-bend routes between two points, and results in 16% to 37% fewer total number of tracks than the Timber Wolf global router for standard cells. It is comparable in quality to a maze router and an industrial router, but is ten times or more faster. Three approaches to parallelizing the router are implemented: wire-by-wire parallelism, segment-by-segment and route-by-route. Two of these approaches achieve significant speedup; route-by-route achieves up to 4.6 using eight processors, and wire-by-wire achieves from 5.8 to 7.6 on eight processors.<>
{"title":"LocusRoute: a parallel global router for standard cells","authors":"Jonathan Rose","doi":"10.1109/DAC.1988.14757","DOIUrl":"https://doi.org/10.1109/DAC.1988.14757","url":null,"abstract":"A fast and easily parallelizable global routing algorithm for standard cells and its parallel implementation are presented. LocusRoute is meant to be used as the cost function for a placement algorithm, and so this context constrains the structure of the global routing algorithm and its parallel implementation. The router is based on enumerating a subset of all two-bend routes between two points, and results in 16% to 37% fewer total number of tracks than the Timber Wolf global router for standard cells. It is comparable in quality to a maze router and an industrial router, but is ten times or more faster. Three approaches to parallelizing the router are implemented: wire-by-wire parallelism, segment-by-segment and route-by-route. Two of these approaches achieve significant speedup; route-by-route achieves up to 4.6 using eight processors, and wire-by-wire achieves from 5.8 to 7.6 on eight processors.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"336 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114235615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Accurate and efficient expected current is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A pattern-independent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts are presented which allow an efficient and accurate estimation of expected current waveforms. They are: probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis. This approach is considerably faster than traditional methods and yields comparable results.<>
{"title":"Pattern-independent current estimation for reliability analysis of CMOS circuits","authors":"R. Burch, F. Najm, Ping Yang, D. Hocevar","doi":"10.1109/DAC.1988.14773","DOIUrl":"https://doi.org/10.1109/DAC.1988.14773","url":null,"abstract":"Accurate and efficient expected current is required in circuit designs to analyze electromigration failure rate, power consumption, voltage drop, etc. A pattern-independent simulation approach for estimating this expected current waveform drawn by CMOS circuitry has been developed. Four original concepts are presented which allow an efficient and accurate estimation of expected current waveforms. They are: probability waveforms, probability waveform propagation, probabilistic circuit models, and statistical timing analysis. This approach is considerably faster than traditional methods and yields comparable results.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126457915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel via minimization approach is presented for two-layer routing of printed-circuit boards and VLSI chips. The authors have analyzed and characterized different aspects of the problem and derived an equivalent graph model for the problem from the linear-programming formulation. Based on the analysis of their unified formulation, the authors pose a practical heuristic algorithm. The algorithm can handle both grid-based and gridless routing. Also, an arbitrary number of wires is allowed to intersect at a via, and both Manhattan and knock-knee routings are allowed.<>
{"title":"The constrained via minimization problem for PCB and VLSI design","authors":"X. Xiong, E. Kuh","doi":"10.1109/DAC.1988.14818","DOIUrl":"https://doi.org/10.1109/DAC.1988.14818","url":null,"abstract":"A novel via minimization approach is presented for two-layer routing of printed-circuit boards and VLSI chips. The authors have analyzed and characterized different aspects of the problem and derived an equivalent graph model for the problem from the linear-programming formulation. Based on the analysis of their unified formulation, the authors pose a practical heuristic algorithm. The algorithm can handle both grid-based and gridless routing. Also, an arbitrary number of wires is allowed to intersect at a via, and both Manhattan and knock-knee routings are allowed.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124809186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A special-purpose database management system for VLSI design environment is presented. Besides supporting design data management and tools integration, the system provides lots of facilities for supporting fast development of efficient and powerful VLSI CAD tools. This system could simplify the task and reduce errors made in implementing an integrated VLSI design system.<>
{"title":"A database management system for a VLSI design system","authors":"Gwo-Dong Chen, T. Parng","doi":"10.1109/DAC.1988.14767","DOIUrl":"https://doi.org/10.1109/DAC.1988.14767","url":null,"abstract":"A special-purpose database management system for VLSI design environment is presented. Besides supporting design data management and tools integration, the system provides lots of facilities for supporting fast development of efficient and powerful VLSI CAD tools. This system could simplify the task and reduce errors made in implementing an integrated VLSI design system.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134218867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A parallel algorithm is proposed for the problem of channel and switchbox routing in the design of VLSI chips. The algorithm is suitable for implementation on a shared-memory multiprocessor environment. The approach does not impose restrictions on the channel type (such as fixed or variable channel widths) and the number of available layers. The algorithm contains three major phases: (1) dividing the channel into several regions by selecting some columns, (2) assigning tracks to nets of the selected columns, and (3) assigning tracks to nets of the columns in each region.<>
{"title":"Parallel channel routing","authors":"M. Zargham","doi":"10.1109/DAC.1988.14747","DOIUrl":"https://doi.org/10.1109/DAC.1988.14747","url":null,"abstract":"A parallel algorithm is proposed for the problem of channel and switchbox routing in the design of VLSI chips. The algorithm is suitable for implementation on a shared-memory multiprocessor environment. The approach does not impose restrictions on the channel type (such as fixed or variable channel widths) and the number of available layers. The algorithm contains three major phases: (1) dividing the channel into several regions by selecting some columns, (2) assigning tracks to nets of the selected columns, and (3) assigning tracks to nets of the columns in each region.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133523712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
At the third High-Level Synthesis Workshop held in January 1988 at Orcas Island, Washington, participants were asked to submit papers describing the application of their systems and algorithms to set of benchmarks. The authors briefly describe the benchmarks and use them as a foundation for outlining the major themes in the research work presented at the workshop. They conclude with a summary of the discussions held during the course of the workshop on the future development of the high-level synthesis benchmark suite.<>
{"title":"High-level synthesis: current status and future directions","authors":"G. Borriello, E. Detjens","doi":"10.1109/DAC.1988.14802","DOIUrl":"https://doi.org/10.1109/DAC.1988.14802","url":null,"abstract":"At the third High-Level Synthesis Workshop held in January 1988 at Orcas Island, Washington, participants were asked to submit papers describing the application of their systems and algorithms to set of benchmarks. The authors briefly describe the benchmarks and use them as a foundation for outlining the major themes in the research work presented at the workshop. They conclude with a summary of the discussions held during the course of the workshop on the future development of the high-level synthesis benchmark suite.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130382781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：