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Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems最新文献

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Object-oriented video coding algorithm for very low bit-rate system 面向对象的极低比特率系统视频编码算法
Pub Date : 1994-12-05 DOI: 10.1109/APCCAS.1994.514622
Liang-Gee Chen, You-Ming Chiu, T. Chiueh, H. Jong
In this paper, a video coding method based on region segmentation is proposed. It is designed for very low bit-rate systems such as video-phone and video-conferencing. Instead of block-based coding, we adopt an object-oriented approach, which first calculates the motion vector of each pixel using a modified optical flow approach, then segments the motion field into circumscribed rectangular regions that can be efficiently coded. Simulation results of several typical image sequences reveal that the proposed algorithm is both effective and of high performance.
提出了一种基于区域分割的视频编码方法。它是专为非常低的比特率系统,如视频电话和视频会议。我们采用面向对象的方法代替基于块的编码,首先使用改进的光流方法计算每个像素的运动向量,然后将运动场分割成可以有效编码的限定矩形区域。几个典型图像序列的仿真结果表明,该算法是有效的,具有较高的性能。
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引用次数: 7
A new concept of a Gm tuning circuit for voltage- or current-controlled transconductance circuits 一种用于电压或电流控制跨导电路的Gm调谐电路的新概念
Pub Date : 1994-12-05 DOI: 10.1109/APCCAS.1994.514616
A. Hyogo, K. Sekine
A new concept of a transconductance (Gm) tuning circuit using switched-capacitor (SC) circuits for voltage- or current-controlled transconductance circuits is proposed. This concept uses an integrator which is controlled by time (or frequency) as a current-to-voltage converter for tuning. The Gm can be determined by the integrated time of the current from the transconductance circuit, the integration capacitor and the reference voltage(s). Moreover, the Gm control voltage produced by the proposed circuit has no ripple. The proposed circuit can tune operational transconductance amplifiers, MOS resistive circuits and so on. Finally, an offset voltage cancellation technique for the integrator is shown. SPICE simulations are performed to verify the performance of the proposed circuits.
提出了一种利用开关电容(SC)电路控制电压或电流的跨导调谐电路的新概念。这个概念使用由时间(或频率)控制的积分器作为电流-电压转换器进行调谐。Gm可以由来自跨导电路的电流、积分电容和参考电压的积分时间来确定。此外,该电路产生的Gm控制电压无纹波。该电路可调谐跨导放大器、MOS电阻电路等。最后,给出了一种用于积分器的偏置电压抵消技术。通过SPICE仿真验证了所提电路的性能。
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引用次数: 0
Fast inverters and dividers for finite field GF(2/sup m/) 有限域GF(2/sup m/)快速逆变器和分频器
Pub Date : 1994-12-05 DOI: 10.1109/APCCAS.1994.514550
Y. Horng, Shyue-Win Wei
Based on Euclid's algorithm, two architectures for performing rapid inversions and divisions in finite field GF(2/sup m/) with the standard basis representation are presented. Both architectures have regularity and modularity and are well suited for VLSI implementation. These circuits can be easily expanded to any finite field size because they are independent of the primitive polynomial used to generate the field. The proposed inverter and divider take exactly 2(m-1) clock cycles for each inversion and division operation, and the clock period is independent of the field size m.
基于欧几里得算法,提出了在有限域GF(2/sup m/)上用标准基表示进行快速反演和除法的两种体系结构。这两种架构都具有规律性和模块化,非常适合VLSI实现。这些电路可以很容易地扩展到任何有限的域大小,因为它们独立于用于产生域的原始多项式。所提出的逆变器和分频器每次反转和除法操作正好需要2(m-1)个时钟周期,并且时钟周期与场大小m无关。
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引用次数: 7
Optical fiber digital picture code and supervisory signal transmission system 光纤数字图像编码与监控信号传输系统
Pub Date : 1994-12-05 DOI: 10.1109/APCCAS.1994.514575
H. Asada, H. Ikeda, H. Yoshida
This paper describes a digital signal transmission system using nine optical fibers for the picture code of 5 bits and supervisory signal of 3 bits, and using one optical fiber for the clock at 14.32 MHz, which is built based on the conventional digital TV signal transmission system consisting of a picture code of 8 bits with the clock at 14.32 MHz. Since the picture code and supervisory signals are transmitted at the same time, the system can be used for industrial applications in an inferior environment. Even if the environment is dangerous for human beings, the system can be operated satisfactorily. The experimental system succeeded in transmitting the TV signal, and the picture quality was almost the same as that operating at 8 quantizational bits. Since the TV and supervisory signals are digitized in the same sequence, these signals are suitable for computer processing.
本文在传统的8位图像码和14.32 MHz时钟组成的数字电视信号传输系统的基础上,提出了一种采用9根光纤传输5位图像码和3位监控信号,使用1根光纤传输14.32 MHz时钟的数字信号传输系统。由于图像编码和监控信号同时传输,因此该系统可用于恶劣环境下的工业应用。即使环境对人类来说是危险的,系统也能令人满意地运行。实验系统成功地传输了电视信号,图像质量与8个量化比特的图像质量基本一致。由于电视信号和监控信号是按相同的顺序数字化的,因此这些信号适合计算机处理。
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引用次数: 6
Channel noise filtering for subband image coding using vector quantization 信道噪声滤波的子带图像编码使用矢量量化
Pub Date : 1994-12-05 DOI: 10.1109/APCCAS.1994.514625
C. Kuo, J. H. Leu
In this paper, we design a post-filter for the subband coding of images using vector quantization. The purpose of this filter is to remove the inevitable channel noise after the compressed image is transmitted across a channel. We first proposed two simple schemes to detect the edges and channel noises in the subbands based on the image and subband characteristics. Then the noise corrupted subbands at the uniform, edge, and texture region are then adaptively low-pass filtered. After noise filtering, the image is then reconstructed from all its subbands. Since the proposed filter does not assume any knowledge about the quantization, it can be used for any subband coding schemes. The experimental results show that the proposed filter always improves the coding performance when the channel bit error rate is greater than 0.01%. The largest gain (5.7 dB) occurs when the bit error rate is 1%.
本文采用矢量量化的方法设计了一种用于图像子带编码的后置滤波器。该滤波器的目的是去除压缩图像通过信道传输后不可避免的信道噪声。首先根据图像和子带的特性,提出了两种检测子带边缘和信道噪声的简单方案。然后对均匀区、边缘区和纹理区的噪声破坏子带进行自适应低通滤波。经过噪声滤波后,从其所有子带重构图像。由于所提出的滤波器不假设任何量化知识,它可以用于任何子带编码方案。实验结果表明,当信道误码率大于0.01%时,所提出的滤波器总能提高编码性能。误码率为1%时,增益最大,为5.7 dB。
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引用次数: 0
BTC image coding with visual patterns BTC图像编码与视觉模式
Pub Date : 1994-12-05 DOI: 10.1109/APCCAS.1994.514628
Tuk Po Chun, B. Zeng, M. L. Liou
This paper presents a block truncation coding (BTC) scheme for image compression that employs visual patterns designed independently of the image to be coded. In this method, image blocks are first classified into three classes: uniform, gentle edge, and sharp edge, according to their variations. Design focus is on edge blocks, where two sets of patterns, namely, visual patterns and visual row patterns are used. Different quantization is performed on the mean values of each block according to its block type. Experimental results show that the proposed BTC scheme can achieve PSNR about 30 dB at bit rate 0.46/spl sim/0.53 bpp (for the image Lenna of size 512/spl times/512).
本文提出了一种用于图像压缩的块截断编码(BTC)方案,该方案采用独立于待编码图像设计的视觉模式。该方法首先根据图像块的变化情况,将图像块分为均匀边缘、平缓边缘和锐利边缘三类。设计重点是在边缘块上,其中使用了两组模式,即视觉模式和视觉行模式。根据块类型对每个块的均值进行不同的量化处理。实验结果表明,在比特率为0.46/spl sim/0.53 bpp(对于大小为512/spl times/512的图像Lenna)的情况下,所提出的BTC方案可实现约30 dB的PSNR。
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引用次数: 4
Modeling, simulation and layout synthesis for giga scale CMOS VLSI 千兆级CMOS VLSI的建模、仿真与布局综合
Pub Date : 1994-12-05 DOI: 10.1109/APCCAS.1994.514591
S. Kang
Summary form only given, as follows. With continuing proliferation of CMOS technology, we are approaching the era of giga-scale VLSI integration with lower power requirement. It would not be surprising to any member of the VLSI community that the validity of many CAD models become obsolete in the deep submicron technology. Also, the required chip complexity increases faster than what designers can afford in even shorter design cycle time. In order to manage the design complexity and contain the increase in the design effort of VLSI chips, it is critically important to fully automate the layout of VLSI circuits in a manner the finished layout meets all the design objectives such as timing, area, reliability constraints with high yield. Here the author considers new MOS models for deep submicron technologies, fast and accurate simulation techniques for VLSI circuits, MOS reliability modeling and diagnosis, and timing-driven layout CMOS synthesis techniques. FPGA, standard cells based design and full custom design cases are considered. For FPGA, timing-driven partitioning is considered along with new CAD tool development trends. For standard cells based design, gate sizing techniques for meeting timing and low-power constraints with minimum area are discussed. For full custom design, an integrated environment for compact layout platforms, triple metal routing techniques and transistor sizing algorithms is discussed.
仅给出摘要形式,如下。随着CMOS技术的不断发展,我们正在接近具有更低功耗要求的千兆级VLSI集成时代。对于VLSI社区的任何成员来说,许多CAD模型的有效性在深亚微米技术中变得过时并不奇怪。此外,所需芯片复杂性的增长速度比设计师在更短的设计周期内所能承受的要快得多。为了控制设计复杂性和控制VLSI芯片设计工作量的增加,使VLSI电路的布局完全自动化是至关重要的,并且最终的布局满足所有设计目标,如时间、面积、可靠性约束和高良率。在这里,作者考虑了深亚微米技术的新型MOS模型,VLSI电路的快速精确仿真技术,MOS可靠性建模和诊断以及时序驱动布局CMOS合成技术。考虑了FPGA、基于标准单元的设计和完全定制的设计案例。对于FPGA来说,时序驱动分区是随着新的CAD工具发展趋势而被考虑的。对于基于标准单元的设计,讨论了以最小面积满足时序和低功耗约束的栅极尺寸技术。对于完全定制设计,讨论了紧凑布局平台,三金属布线技术和晶体管尺寸算法的集成环境。
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引用次数: 0
Design of inverse DCT unit and motion compensator for MPEG2 HDTV decoding MPEG2高清电视解码反DCT单元及运动补偿器的设计
Pub Date : 1994-12-05 DOI: 10.1109/APCCAS.1994.514621
T. Onoye, Y. Morimoto, T. Masaki, I. Shirakawa
An MPEG2 video decoder core is implemented, which consists of an inverse discrete cosine transform (IDCT) unit and a motion compensator. By means of butterfly computation, multi-bit extension of distributed arithmetic, and improvement of critical paths, the IDCT unit achieves a high throughput, and the motion compensator calculates half-pel image dynamically so as to cover several types of picture prediction modes employed by MPEG2. The decoder core occupies 27 mm/sup 2/ in a 0.6-/spl mu/m triple-metal CMOS technology, processes a macroblock (16/spl times/16 pels) within 2.5 /spl mu/s, and therefore is capable of decoding HDTV (1920/spl times/1152 pels) resolution images in real time.
实现了一种由反离散余弦变换(IDCT)单元和运动补偿器组成的MPEG2视频解码器核心。通过蝴蝶计算、分布式算法的多位扩展和关键路径的改进,IDCT单元实现了高吞吐量,运动补偿器动态计算半像素图像,从而覆盖了MPEG2采用的几种图像预测模式。解码器核心采用0.6-/spl μ m三金属CMOS技术,占地27mm /sup / m2,在2.5 /spl μ s内处理宏块(16/spl次/16像素),因此能够实时解码HDTV (1920/spl次/1152像素)分辨率图像。
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引用次数: 1
A VLSI circuit extractor with a parallel algorithm 基于并行算法的VLSI电路提取器
Pub Date : 1994-12-05 DOI: 10.1109/APCCAS.1994.514567
K. Yoon, Doo-Bok Lee, P. K. Rhee, S. Han, S.J. Park
This paper describes a parallel algorithm of an automated CMOS circuit extraction that transforms an IC layout into a circuit netlist suitable for circuit simulations. Using reconfigurable parallel machine architecture, the newly developed algorithm achieved a circuit extraction performance which is a constant time complexity. The layout of a CMOS inverter used successfully to demonstrate an efficiency of the newly developed algorithm.
本文介绍了一种自动CMOS电路提取的并行算法,该算法将集成电路版图转换为适合电路仿真的电路网表。该算法采用可重构并行机架构,实现了恒定时间复杂度的电路提取性能。通过CMOS逆变器的设计,验证了该算法的有效性。
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引用次数: 0
A versatile current-mode biquad using operational amplifiers 使用运算放大器的通用电流模式双路电路
Pub Date : 1994-12-05 DOI: 10.1109/APCCAS.1994.514618
Y. Shiwen, S. Tsuiki, M. Ishida, Y. Fukui
A versatile current-mode biquad filter using three operational amplifiers and 9 passive elements is proposed. By the suitable choice of the output branch, lowpass, bandpass, highpass, bandstop and allpass transfer functions are realized simultaneously without changing the circuit configuration and elements. Two circuits, one is for low frequency application and the other for high frequency, are proposed. The center frequency, quality factor and gain constants of the circuit can be tuned independently. Simulated results will show that the circuits work successfully.
提出了一种由3个运算放大器和9个无源元件组成的通用电流模式双源滤波器。通过选择合适的输出支路,可以在不改变电路结构和元件的情况下同时实现低通、带通、高通、带阻和全通传递函数。提出了两种电路,一种用于低频,另一种用于高频。该电路的中心频率、品质因数和增益常数均可独立调谐。仿真结果表明,该电路工作正常。
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引用次数: 0
期刊
Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems
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