Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514622
Liang-Gee Chen, You-Ming Chiu, T. Chiueh, H. Jong
In this paper, a video coding method based on region segmentation is proposed. It is designed for very low bit-rate systems such as video-phone and video-conferencing. Instead of block-based coding, we adopt an object-oriented approach, which first calculates the motion vector of each pixel using a modified optical flow approach, then segments the motion field into circumscribed rectangular regions that can be efficiently coded. Simulation results of several typical image sequences reveal that the proposed algorithm is both effective and of high performance.
{"title":"Object-oriented video coding algorithm for very low bit-rate system","authors":"Liang-Gee Chen, You-Ming Chiu, T. Chiueh, H. Jong","doi":"10.1109/APCCAS.1994.514622","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514622","url":null,"abstract":"In this paper, a video coding method based on region segmentation is proposed. It is designed for very low bit-rate systems such as video-phone and video-conferencing. Instead of block-based coding, we adopt an object-oriented approach, which first calculates the motion vector of each pixel using a modified optical flow approach, then segments the motion field into circumscribed rectangular regions that can be efficiently coded. Simulation results of several typical image sequences reveal that the proposed algorithm is both effective and of high performance.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125734834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514550
Y. Horng, Shyue-Win Wei
Based on Euclid's algorithm, two architectures for performing rapid inversions and divisions in finite field GF(2/sup m/) with the standard basis representation are presented. Both architectures have regularity and modularity and are well suited for VLSI implementation. These circuits can be easily expanded to any finite field size because they are independent of the primitive polynomial used to generate the field. The proposed inverter and divider take exactly 2(m-1) clock cycles for each inversion and division operation, and the clock period is independent of the field size m.
{"title":"Fast inverters and dividers for finite field GF(2/sup m/)","authors":"Y. Horng, Shyue-Win Wei","doi":"10.1109/APCCAS.1994.514550","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514550","url":null,"abstract":"Based on Euclid's algorithm, two architectures for performing rapid inversions and divisions in finite field GF(2/sup m/) with the standard basis representation are presented. Both architectures have regularity and modularity and are well suited for VLSI implementation. These circuits can be easily expanded to any finite field size because they are independent of the primitive polynomial used to generate the field. The proposed inverter and divider take exactly 2(m-1) clock cycles for each inversion and division operation, and the clock period is independent of the field size m.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127739028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514616
A. Hyogo, K. Sekine
A new concept of a transconductance (Gm) tuning circuit using switched-capacitor (SC) circuits for voltage- or current-controlled transconductance circuits is proposed. This concept uses an integrator which is controlled by time (or frequency) as a current-to-voltage converter for tuning. The Gm can be determined by the integrated time of the current from the transconductance circuit, the integration capacitor and the reference voltage(s). Moreover, the Gm control voltage produced by the proposed circuit has no ripple. The proposed circuit can tune operational transconductance amplifiers, MOS resistive circuits and so on. Finally, an offset voltage cancellation technique for the integrator is shown. SPICE simulations are performed to verify the performance of the proposed circuits.
{"title":"A new concept of a Gm tuning circuit for voltage- or current-controlled transconductance circuits","authors":"A. Hyogo, K. Sekine","doi":"10.1109/APCCAS.1994.514616","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514616","url":null,"abstract":"A new concept of a transconductance (Gm) tuning circuit using switched-capacitor (SC) circuits for voltage- or current-controlled transconductance circuits is proposed. This concept uses an integrator which is controlled by time (or frequency) as a current-to-voltage converter for tuning. The Gm can be determined by the integrated time of the current from the transconductance circuit, the integration capacitor and the reference voltage(s). Moreover, the Gm control voltage produced by the proposed circuit has no ripple. The proposed circuit can tune operational transconductance amplifiers, MOS resistive circuits and so on. Finally, an offset voltage cancellation technique for the integrator is shown. SPICE simulations are performed to verify the performance of the proposed circuits.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126517117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514580
Wen-Rong Wu, Po-Cheng Chen
The AR modeling is widely used in signal processing. The coefficients of AR model can be easily obtained by a LMS prediction error filter. However, it is known that such filter will give bias coefficients when the input signal is corrupted by noise. In previous works, Treicher [1979] suggested the /spl gamma/-LMS algorithm to reduce the bias problem caused by Gaussian noise. This paper gives the theoretical analysis of the /spl gamma/-LMS algorithm. We derive the close form solution of the second order statistics of the tap-weight vector. Computer simulations are provided to show the accuracy of our theoretical result.
{"title":"Theoretic analysis of the /spl gamma/-LMS algorithm","authors":"Wen-Rong Wu, Po-Cheng Chen","doi":"10.1109/APCCAS.1994.514580","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514580","url":null,"abstract":"The AR modeling is widely used in signal processing. The coefficients of AR model can be easily obtained by a LMS prediction error filter. However, it is known that such filter will give bias coefficients when the input signal is corrupted by noise. In previous works, Treicher [1979] suggested the /spl gamma/-LMS algorithm to reduce the bias problem caused by Gaussian noise. This paper gives the theoretical analysis of the /spl gamma/-LMS algorithm. We derive the close form solution of the second order statistics of the tap-weight vector. Computer simulations are provided to show the accuracy of our theoretical result.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130831915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514575
H. Asada, H. Ikeda, H. Yoshida
This paper describes a digital signal transmission system using nine optical fibers for the picture code of 5 bits and supervisory signal of 3 bits, and using one optical fiber for the clock at 14.32 MHz, which is built based on the conventional digital TV signal transmission system consisting of a picture code of 8 bits with the clock at 14.32 MHz. Since the picture code and supervisory signals are transmitted at the same time, the system can be used for industrial applications in an inferior environment. Even if the environment is dangerous for human beings, the system can be operated satisfactorily. The experimental system succeeded in transmitting the TV signal, and the picture quality was almost the same as that operating at 8 quantizational bits. Since the TV and supervisory signals are digitized in the same sequence, these signals are suitable for computer processing.
{"title":"Optical fiber digital picture code and supervisory signal transmission system","authors":"H. Asada, H. Ikeda, H. Yoshida","doi":"10.1109/APCCAS.1994.514575","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514575","url":null,"abstract":"This paper describes a digital signal transmission system using nine optical fibers for the picture code of 5 bits and supervisory signal of 3 bits, and using one optical fiber for the clock at 14.32 MHz, which is built based on the conventional digital TV signal transmission system consisting of a picture code of 8 bits with the clock at 14.32 MHz. Since the picture code and supervisory signals are transmitted at the same time, the system can be used for industrial applications in an inferior environment. Even if the environment is dangerous for human beings, the system can be operated satisfactorily. The experimental system succeeded in transmitting the TV signal, and the picture quality was almost the same as that operating at 8 quantizational bits. Since the TV and supervisory signals are digitized in the same sequence, these signals are suitable for computer processing.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134190125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514625
C. Kuo, J. H. Leu
In this paper, we design a post-filter for the subband coding of images using vector quantization. The purpose of this filter is to remove the inevitable channel noise after the compressed image is transmitted across a channel. We first proposed two simple schemes to detect the edges and channel noises in the subbands based on the image and subband characteristics. Then the noise corrupted subbands at the uniform, edge, and texture region are then adaptively low-pass filtered. After noise filtering, the image is then reconstructed from all its subbands. Since the proposed filter does not assume any knowledge about the quantization, it can be used for any subband coding schemes. The experimental results show that the proposed filter always improves the coding performance when the channel bit error rate is greater than 0.01%. The largest gain (5.7 dB) occurs when the bit error rate is 1%.
{"title":"Channel noise filtering for subband image coding using vector quantization","authors":"C. Kuo, J. H. Leu","doi":"10.1109/APCCAS.1994.514625","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514625","url":null,"abstract":"In this paper, we design a post-filter for the subband coding of images using vector quantization. The purpose of this filter is to remove the inevitable channel noise after the compressed image is transmitted across a channel. We first proposed two simple schemes to detect the edges and channel noises in the subbands based on the image and subband characteristics. Then the noise corrupted subbands at the uniform, edge, and texture region are then adaptively low-pass filtered. After noise filtering, the image is then reconstructed from all its subbands. Since the proposed filter does not assume any knowledge about the quantization, it can be used for any subband coding schemes. The experimental results show that the proposed filter always improves the coding performance when the channel bit error rate is greater than 0.01%. The largest gain (5.7 dB) occurs when the bit error rate is 1%.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129829284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514591
S. Kang
Summary form only given, as follows. With continuing proliferation of CMOS technology, we are approaching the era of giga-scale VLSI integration with lower power requirement. It would not be surprising to any member of the VLSI community that the validity of many CAD models become obsolete in the deep submicron technology. Also, the required chip complexity increases faster than what designers can afford in even shorter design cycle time. In order to manage the design complexity and contain the increase in the design effort of VLSI chips, it is critically important to fully automate the layout of VLSI circuits in a manner the finished layout meets all the design objectives such as timing, area, reliability constraints with high yield. Here the author considers new MOS models for deep submicron technologies, fast and accurate simulation techniques for VLSI circuits, MOS reliability modeling and diagnosis, and timing-driven layout CMOS synthesis techniques. FPGA, standard cells based design and full custom design cases are considered. For FPGA, timing-driven partitioning is considered along with new CAD tool development trends. For standard cells based design, gate sizing techniques for meeting timing and low-power constraints with minimum area are discussed. For full custom design, an integrated environment for compact layout platforms, triple metal routing techniques and transistor sizing algorithms is discussed.
{"title":"Modeling, simulation and layout synthesis for giga scale CMOS VLSI","authors":"S. Kang","doi":"10.1109/APCCAS.1994.514591","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514591","url":null,"abstract":"Summary form only given, as follows. With continuing proliferation of CMOS technology, we are approaching the era of giga-scale VLSI integration with lower power requirement. It would not be surprising to any member of the VLSI community that the validity of many CAD models become obsolete in the deep submicron technology. Also, the required chip complexity increases faster than what designers can afford in even shorter design cycle time. In order to manage the design complexity and contain the increase in the design effort of VLSI chips, it is critically important to fully automate the layout of VLSI circuits in a manner the finished layout meets all the design objectives such as timing, area, reliability constraints with high yield. Here the author considers new MOS models for deep submicron technologies, fast and accurate simulation techniques for VLSI circuits, MOS reliability modeling and diagnosis, and timing-driven layout CMOS synthesis techniques. FPGA, standard cells based design and full custom design cases are considered. For FPGA, timing-driven partitioning is considered along with new CAD tool development trends. For standard cells based design, gate sizing techniques for meeting timing and low-power constraints with minimum area are discussed. For full custom design, an integrated environment for compact layout platforms, triple metal routing techniques and transistor sizing algorithms is discussed.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123697295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514621
T. Onoye, Y. Morimoto, T. Masaki, I. Shirakawa
An MPEG2 video decoder core is implemented, which consists of an inverse discrete cosine transform (IDCT) unit and a motion compensator. By means of butterfly computation, multi-bit extension of distributed arithmetic, and improvement of critical paths, the IDCT unit achieves a high throughput, and the motion compensator calculates half-pel image dynamically so as to cover several types of picture prediction modes employed by MPEG2. The decoder core occupies 27 mm/sup 2/ in a 0.6-/spl mu/m triple-metal CMOS technology, processes a macroblock (16/spl times/16 pels) within 2.5 /spl mu/s, and therefore is capable of decoding HDTV (1920/spl times/1152 pels) resolution images in real time.
{"title":"Design of inverse DCT unit and motion compensator for MPEG2 HDTV decoding","authors":"T. Onoye, Y. Morimoto, T. Masaki, I. Shirakawa","doi":"10.1109/APCCAS.1994.514621","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514621","url":null,"abstract":"An MPEG2 video decoder core is implemented, which consists of an inverse discrete cosine transform (IDCT) unit and a motion compensator. By means of butterfly computation, multi-bit extension of distributed arithmetic, and improvement of critical paths, the IDCT unit achieves a high throughput, and the motion compensator calculates half-pel image dynamically so as to cover several types of picture prediction modes employed by MPEG2. The decoder core occupies 27 mm/sup 2/ in a 0.6-/spl mu/m triple-metal CMOS technology, processes a macroblock (16/spl times/16 pels) within 2.5 /spl mu/s, and therefore is capable of decoding HDTV (1920/spl times/1152 pels) resolution images in real time.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127422567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514609
Jin-Tai Yan, P.-Y. Hsiao
A unified partitioning based algorithm for the orientation and rotation assignments of macro cells is proposed to minimize total wire length in a macro cell placement. For the orientation and rotation assignments of macro cells, we transform the orientation problem and the rotation problem into a constrained graph bisection problem and a constrained graph quadrisection problem, respectively. Furthermore, a unified fuzzy graph clustering is proposed to solve the two constrained partitioning problems at the same time. The partitioning results of the constrained graph bisection and the constrained graph quadrisection will lend to the orientation and rotation assignments for a macro cell placement. As a result, the proposed partitioning based approach has tested some macro cell placements for the orientation and rotation assignments. The experimental results show that the partitioning based approach obtains better wire reductions on these tested placements.
{"title":"A partitioning-based approach for the orientation and rotation assignments of macro cells","authors":"Jin-Tai Yan, P.-Y. Hsiao","doi":"10.1109/APCCAS.1994.514609","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514609","url":null,"abstract":"A unified partitioning based algorithm for the orientation and rotation assignments of macro cells is proposed to minimize total wire length in a macro cell placement. For the orientation and rotation assignments of macro cells, we transform the orientation problem and the rotation problem into a constrained graph bisection problem and a constrained graph quadrisection problem, respectively. Furthermore, a unified fuzzy graph clustering is proposed to solve the two constrained partitioning problems at the same time. The partitioning results of the constrained graph bisection and the constrained graph quadrisection will lend to the orientation and rotation assignments for a macro cell placement. As a result, the proposed partitioning based approach has tested some macro cell placements for the orientation and rotation assignments. The experimental results show that the partitioning based approach obtains better wire reductions on these tested placements.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122525952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-12-05DOI: 10.1109/APCCAS.1994.514592
T. Her, W. Tsai, F. Kurdahi, Y. Chen
We present a model based on the PLA implementation of logic circuits to estimate the transition densities in two-level combinational logic circuits. Given the primary input signal probabilities and transition densities, our model computes the transition densities at the internal and output nodes directly from the sum-of-products representation of the two-level logic circuits without further converting the circuits into other representations. The experimental results from our model compared to those from SPICE simulations are within an average of 1.7% error, confirming the effectiveness of our model.
{"title":"A PLA-based algorithm for estimating transition densities in two-level combinational logic circuits","authors":"T. Her, W. Tsai, F. Kurdahi, Y. Chen","doi":"10.1109/APCCAS.1994.514592","DOIUrl":"https://doi.org/10.1109/APCCAS.1994.514592","url":null,"abstract":"We present a model based on the PLA implementation of logic circuits to estimate the transition densities in two-level combinational logic circuits. Given the primary input signal probabilities and transition densities, our model computes the transition densities at the internal and output nodes directly from the sum-of-products representation of the two-level logic circuits without further converting the circuits into other representations. The experimental results from our model compared to those from SPICE simulations are within an average of 1.7% error, confirming the effectiveness of our model.","PeriodicalId":231368,"journal":{"name":"Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131998319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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