Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358340
A. Doridant, J. Raoult, S. Jarrix, J. Laurin, P. Hoffmann
The paper presents a detailed study of the dynamic response of an Automatic Gain Control loop (AGC loop) exposed to pulsed radiofrequency interference. It is shown that the most significant effect is an increase of the RF output level of the AGC that is strongly dependent on the pulse repetition frequency, the effect being less pronounced as the repetition frequency increases. It is demonstrated that this is related to the transient response of the logarithmic amplifier, which can be controlled by decoupling capacitors.
{"title":"Preliminary study of Automatic Control Gain loop subjected to pulse-modulated radiofrequency interference","authors":"A. Doridant, J. Raoult, S. Jarrix, J. Laurin, P. Hoffmann","doi":"10.1109/EMCCOMPO.2015.7358340","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358340","url":null,"abstract":"The paper presents a detailed study of the dynamic response of an Automatic Gain Control loop (AGC loop) exposed to pulsed radiofrequency interference. It is shown that the most significant effect is an increase of the RF output level of the AGC that is strongly dependent on the pulse repetition frequency, the effect being less pronounced as the repetition frequency increases. It is demonstrated that this is related to the transient response of the logarithmic amplifier, which can be controlled by decoupling capacitors.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130141113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358359
Jonghoon J. Kim, D. Jung, Heegon Kim, Sunkyu Kong, Sumin Choi, Jaemin Lim, Joungho Kim
Simultaneous switching noise (SSN) is caused by the simultaneous switching of a group of I/O drivers, and is proportional to the total inductance and the rate of change of the switching current. This often leads to signal distortion and degradation of signal and power integrity of systems. Furthermore, with the continuously decreasing operating voltage, susceptibility to SSN keeps on increasing and it becomes increasingly challenging to achieve high performance interfaces. Therefore, it is highly important to perform SSN analysis in order to accurately investigate the noise and timing margin of the devices under test; hence, it is important to know the exact amount of switching current drawn by the ICs. In this paper, we propose TSV-based current probing structure using magnetic coupling, named TSV-based Current Probe (TCP). By capturing the magnetic flux induced by the injected current and processing it through a series of reconstruction steps, we can obtain the original current waveform of interest. Through a series of simulations in frequency and time domains, we verify the performance of the proposed probing structure, TCP. Lastly, TCP is fabricated using TSV fabrication techniques and measured for experimental verification.
{"title":"TSV-based current probing structure using magnetic coupling in 2.5D and 3D IC","authors":"Jonghoon J. Kim, D. Jung, Heegon Kim, Sunkyu Kong, Sumin Choi, Jaemin Lim, Joungho Kim","doi":"10.1109/EMCCOMPO.2015.7358359","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358359","url":null,"abstract":"Simultaneous switching noise (SSN) is caused by the simultaneous switching of a group of I/O drivers, and is proportional to the total inductance and the rate of change of the switching current. This often leads to signal distortion and degradation of signal and power integrity of systems. Furthermore, with the continuously decreasing operating voltage, susceptibility to SSN keeps on increasing and it becomes increasingly challenging to achieve high performance interfaces. Therefore, it is highly important to perform SSN analysis in order to accurately investigate the noise and timing margin of the devices under test; hence, it is important to know the exact amount of switching current drawn by the ICs. In this paper, we propose TSV-based current probing structure using magnetic coupling, named TSV-based Current Probe (TCP). By capturing the magnetic flux induced by the injected current and processing it through a series of reconstruction steps, we can obtain the original current waveform of interest. Through a series of simulations in frequency and time domains, we verify the performance of the proposed probing structure, TCP. Lastly, TCP is fabricated using TSV fabrication techniques and measured for experimental verification.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130540398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358320
B. Deutschmann, G. Winkler, Timuçin Karaca
Due to their high efficiency compared to conventional Class AB amplifiers, Class D audio amplifiers have increasingly become the amplifier of choice especially for low power applications such as portable electronics. However, Class D amplifiers are still a major source of electromagnetic emission of the electronic applications in which they are used. In this paper the benefits of using spread spectrum techniques in order to reduce the emission of Class D audio amplifiers is highlighted. Based on IC-level measurement results of a 10W Mono Class D speaker amplifier, that allows to be synchronized to an external clock, it is shown how spread spectrum parameters like deviation, modulation frequency and modulation signal can be optimized in order to maximize the reduction of the emission.
{"title":"Emission reduction in Class D audio amplifiers by optimizing spread spectrum modulation","authors":"B. Deutschmann, G. Winkler, Timuçin Karaca","doi":"10.1109/EMCCOMPO.2015.7358320","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358320","url":null,"abstract":"Due to their high efficiency compared to conventional Class AB amplifiers, Class D audio amplifiers have increasingly become the amplifier of choice especially for low power applications such as portable electronics. However, Class D amplifiers are still a major source of electromagnetic emission of the electronic applications in which they are used. In this paper the benefits of using spread spectrum techniques in order to reduce the emission of Class D audio amplifiers is highlighted. Based on IC-level measurement results of a 10W Mono Class D speaker amplifier, that allows to be synchronized to an external clock, it is shown how spread spectrum parameters like deviation, modulation frequency and modulation signal can be optimized in order to maximize the reduction of the emission.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115488609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358328
M. Coenen, M. Ye, Huichun Yu
System Efficient ESD Design (SEED) [1] at present requires static response data from the devices and circuitry used along the protection chain, typically from the point of entry at the PCB boundary i.e. connector up to the circuit on-chip to be protected. On this path there may be external ESD protection i.e. voltage clamping, interconnect path delay with specific transmission line properties, package design, on-chip protection design all with parasitic layout effects and ultimately the on-chip circuit(s) to be protected, being unpowered or powered. The present way of using transmission line pulse (TLP) [2-4] to obtain the response parameters is inadequate as only the averaged I/V response parameters are used after 70% of the TLP pulse width used. With most commercially available TLP testers the bandwidth used (to obtain these I/V parameters at typ. 70 ns) is also insufficient to gather the full SEED information required. For the multiple SEED applications to be implemented, dynamic response parameters are needed in time and frequency domain, as the protection device response parameters are affected by the presence of RF energy e.g. with smart phone and other wireless appliances. Furthermore, the dynamic response parameters are a function of the DC bias voltage applied i.e. devices being powered or unpowered as well as temperature. In this 1st paper constraints and ideas are given to gather the multi-dimensional response parameters together with their rationales. At the end of the paper some examples will be presented. Future parts will contain data analysis, model building and model validation.
{"title":"Dynamic multi-parameter response model for SEED analysis","authors":"M. Coenen, M. Ye, Huichun Yu","doi":"10.1109/EMCCOMPO.2015.7358328","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358328","url":null,"abstract":"System Efficient ESD Design (SEED) [1] at present requires static response data from the devices and circuitry used along the protection chain, typically from the point of entry at the PCB boundary i.e. connector up to the circuit on-chip to be protected. On this path there may be external ESD protection i.e. voltage clamping, interconnect path delay with specific transmission line properties, package design, on-chip protection design all with parasitic layout effects and ultimately the on-chip circuit(s) to be protected, being unpowered or powered. The present way of using transmission line pulse (TLP) [2-4] to obtain the response parameters is inadequate as only the averaged I/V response parameters are used after 70% of the TLP pulse width used. With most commercially available TLP testers the bandwidth used (to obtain these I/V parameters at typ. 70 ns) is also insufficient to gather the full SEED information required. For the multiple SEED applications to be implemented, dynamic response parameters are needed in time and frequency domain, as the protection device response parameters are affected by the presence of RF energy e.g. with smart phone and other wireless appliances. Furthermore, the dynamic response parameters are a function of the DC bias voltage applied i.e. devices being powered or unpowered as well as temperature. In this 1st paper constraints and ideas are given to gather the multi-dimensional response parameters together with their rationales. At the end of the paper some examples will be presented. Future parts will contain data analysis, model building and model validation.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122498082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358344
B. Vrignon, A. Doridant, K. Abouda, Y. Gao, D. Pagnoux, T. Marek
Near-field injection at silicon level is a promising method for various areas such as the analysis of radiated immunity to electromagnetic disturbances. Up to now, the research has been mainly focused at PCB level due to the resolution of the near-field probe. This paper presents first investigations of near-field injection on a Safe System Basis Chip at die level. The investigations are focused on one of the regulators included in this IC. The goal is to use the coupling path from 'ultra-high-radiation' to check if the Fail Safe Machine detects correctly the regulator failures during near-field injection. Moreover, simulations help to understand the failure mechanism.
{"title":"Near-field injection on a Safe System Basis Chip at silicon level","authors":"B. Vrignon, A. Doridant, K. Abouda, Y. Gao, D. Pagnoux, T. Marek","doi":"10.1109/EMCCOMPO.2015.7358344","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358344","url":null,"abstract":"Near-field injection at silicon level is a promising method for various areas such as the analysis of radiated immunity to electromagnetic disturbances. Up to now, the research has been mainly focused at PCB level due to the resolution of the near-field probe. This paper presents first investigations of near-field injection on a Safe System Basis Chip at die level. The investigations are focused on one of the regulators included in this IC. The goal is to use the coupling path from 'ultra-high-radiation' to check if the Fail Safe Machine detects correctly the regulator failures during near-field injection. Moreover, simulations help to understand the failure mechanism.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114159816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358357
M. Kaufmann, T. Ostermann
A 3rd order lumped element circuit for the simulation of the JEDEC JS-001-2014 HBM ESD pulse is proposed. The resulting current pulse is analytically computed with a state space model of the circuit. For the purpose of verification a computer algebra system is used, solving and checking the model if it generates a current pulse which fulfils the requirements. The values of the voltage pulse, resistor, inductor and capacitor can be changed dynamically, resulting in an instant check against the standard which is also visualised by a plot. Finally the results are compared against numerical simulation in SPICE.
{"title":"Simulation model based on JEDEC JS-001-2014 for circuit simulation of HBM ESD pulses on IC level","authors":"M. Kaufmann, T. Ostermann","doi":"10.1109/EMCCOMPO.2015.7358357","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358357","url":null,"abstract":"A 3rd order lumped element circuit for the simulation of the JEDEC JS-001-2014 HBM ESD pulse is proposed. The resulting current pulse is analytically computed with a state space model of the circuit. For the purpose of verification a computer algebra system is used, solving and checking the model if it generates a current pulse which fulfils the requirements. The values of the voltage pulse, resistor, inductor and capacitor can be changed dynamically, resulting in an instant check against the standard which is also visualised by a plot. Finally the results are compared against numerical simulation in SPICE.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132507367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358329
A. Degraeve, D. Pissoort, K. Armstrong
This paper discusses the shielding performance or shielding effectiveness of a board-level shield in function of its bonding method. Improved shielding performance at board-level in order to harden integrated circuits against unintentional and intentional electromagnetic interference, and this under harsh environmental conditions, is getting more and more important to achieve the desired levels of functional performance and operational reliability despite an ever more aggressive electromagnetic environment. High levels of operational reliability are increasingly being required to help control functional safety or other risks. As a board-level shield on its own only provides 5 of the 6 required walls to form a complete Faraday Cage, its overall shielding performance depends heavily on the way it is bonded to the printed circuit board's ground plane. It is shown by full-wave simulations that the shielding effectiveness can improve by more than 40 dB when bonded with the waveguide-below-cutoff principle compared to a classic perimeter bond of a single row of vias. And this even if the waveguides-below-cutoff are formed by rows of vias. Finally, the paper stresses the influence that internal resonances of the board-level shield have on its shielding effectiveness.
{"title":"Improving the shielding effectiveness of a board-level shield by bonding it with the waveguide-below-cutoff principle","authors":"A. Degraeve, D. Pissoort, K. Armstrong","doi":"10.1109/EMCCOMPO.2015.7358329","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358329","url":null,"abstract":"This paper discusses the shielding performance or shielding effectiveness of a board-level shield in function of its bonding method. Improved shielding performance at board-level in order to harden integrated circuits against unintentional and intentional electromagnetic interference, and this under harsh environmental conditions, is getting more and more important to achieve the desired levels of functional performance and operational reliability despite an ever more aggressive electromagnetic environment. High levels of operational reliability are increasingly being required to help control functional safety or other risks. As a board-level shield on its own only provides 5 of the 6 required walls to form a complete Faraday Cage, its overall shielding performance depends heavily on the way it is bonded to the printed circuit board's ground plane. It is shown by full-wave simulations that the shielding effectiveness can improve by more than 40 dB when bonded with the waveguide-below-cutoff principle compared to a classic perimeter bond of a single row of vias. And this even if the waveguides-below-cutoff are formed by rows of vias. Finally, the paper stresses the influence that internal resonances of the board-level shield have on its shielding effectiveness.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127175263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358368
Marko Magerl, C. Stockreiter, O. Eisenberger, R. Minixhofer, A. Barić
An interchangeable black-box model of an integrated circuit block for time-domain simulations of the direct power injection (DPI) immunity test is presented. An artificial neural network implemented as a Verilog A module is used to build a model of a bandgap reference circuit sub-block. Being a part of a larger schematic of interconnected circuit blocks, the model is able to correctly load the transistor-level block in the previous stage. The simulation time for the transient analysis is significantly improved compared to the transistor-level models, and the time-to-steady-state of the model is negligible. The accuracy of the model is comparable to the state-of-the-art black-box modelling approaches. The model is very practical for obtaining the EMC behaviour of complex integrated circuits at design-time.
{"title":"Building interchangeable black-box models of integrated circuits for EMC simulations","authors":"Marko Magerl, C. Stockreiter, O. Eisenberger, R. Minixhofer, A. Barić","doi":"10.1109/EMCCOMPO.2015.7358368","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358368","url":null,"abstract":"An interchangeable black-box model of an integrated circuit block for time-domain simulations of the direct power injection (DPI) immunity test is presented. An artificial neural network implemented as a Verilog A module is used to build a model of a bandgap reference circuit sub-block. Being a part of a larger schematic of interconnected circuit blocks, the model is able to correctly load the transistor-level block in the previous stage. The simulation time for the transient analysis is significantly improved compared to the transistor-level models, and the time-to-steady-state of the model is negligible. The accuracy of the model is comparable to the state-of-the-art black-box modelling approaches. The model is very practical for obtaining the EMC behaviour of complex integrated circuits at design-time.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123982766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358322
M. Deloge, A. P. V. D. Wel, Shishir Goyal, Gerald Kwakernaat, A. Schoof
This paper presents a novel CAN transceiver based on a highly-digitized architecture designed and fabricated in 0.14μm high-voltage SOI CMOS. This advanced BCD process allows the implementation of this innovative architecture which combines digital and high-voltage analog circuits. Hence, the output stage can be split in multiple unit cells successively enabled or disabled by a shift register. It also allows an advantageous implementation of a dual-clock CAN receiver that combines an architecture optimized for high EM Immunity with a low-power mode where a low-frequency clock is used to reduce the power consumption. EMC performance was evaluated according to automotive industry standards. It shows excellent EME and EMI compliance to car manufacturer requirements without using a common-mode choke.
{"title":"A highly-digitized automotive CAN transceiver in 0.14µm high-voltage SOI CMOS","authors":"M. Deloge, A. P. V. D. Wel, Shishir Goyal, Gerald Kwakernaat, A. Schoof","doi":"10.1109/EMCCOMPO.2015.7358322","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358322","url":null,"abstract":"This paper presents a novel CAN transceiver based on a highly-digitized architecture designed and fabricated in 0.14μm high-voltage SOI CMOS. This advanced BCD process allows the implementation of this innovative architecture which combines digital and high-voltage analog circuits. Hence, the output stage can be split in multiple unit cells successively enabled or disabled by a shift register. It also allows an advantageous implementation of a dual-clock CAN receiver that combines an architecture optimized for high EM Immunity with a low-power mode where a low-frequency clock is used to reduce the power consumption. EMC performance was evaluated according to automotive industry standards. It shows excellent EME and EMI compliance to car manufacturer requirements without using a common-mode choke.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"2009 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129443805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358354
P. Fernandez-Lopez, M. Amara, T. Hoang, F. Lafon
This paper introduces a new Direct Power Injection (DPI) set-up used to characterize the conducted immunity of integrated circuits (IC) with differential inputs. It allows injecting common-mode, differential-mode signals or any combination of both. For a given kind of injection, it is necessary to calculate power and phase-shift at generators. To do so, an analytic model is developed based on S-parameters of all blocks involved in the set-up including the IC. This model is validated by simulation under PSpice and by measurement in [1 MHz - 800 MHz] band for pure common-mode and pure differential-mode injections. With this set-up, IC immunity can be characterized as functions of common-mode and differential-mode voltages versus frequency.
{"title":"DPI set-up for ICs with differential inputs","authors":"P. Fernandez-Lopez, M. Amara, T. Hoang, F. Lafon","doi":"10.1109/EMCCOMPO.2015.7358354","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358354","url":null,"abstract":"This paper introduces a new Direct Power Injection (DPI) set-up used to characterize the conducted immunity of integrated circuits (IC) with differential inputs. It allows injecting common-mode, differential-mode signals or any combination of both. For a given kind of injection, it is necessary to calculate power and phase-shift at generators. To do so, an analytic model is developed based on S-parameters of all blocks involved in the set-up including the IC. This model is validated by simulation under PSpice and by measurement in [1 MHz - 800 MHz] band for pure common-mode and pure differential-mode injections. With this set-up, IC immunity can be characterized as functions of common-mode and differential-mode voltages versus frequency.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115037603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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