Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358323
A. Schindler, Benno Koeppl, B. Wicht
There is a growing need for motor drives with improved EMC in various automotive and industrial applications. An often referenced approach to reduce EME is to change the shape of the switching signal to reduce the EMI caused by the voltage and current transitions. This requires very precise gate control of the power MOSFET to achieve better switching behaviour and lower EME without a major increase in switching losses. In order to find an optimal trade-off, this work utilizes a monolithic current mode gate driver with a variable output current that can be changed within 10ns. With this driver, measurements with different gate current profiles were taken. The di/dt transition was confirmed to be as important as the dv/dt transition in the power MOSFET. As a result of the improved switching behavior the emissions were reduced by up to 20dB between 7MHz and 60MHz with a switching loss that is 52% lower than with a constantly low gate current.
{"title":"EMC and switching loss improvement for fast switching power stages by di/dt, dv/dt optimization with 10ns variable current source gate driver","authors":"A. Schindler, Benno Koeppl, B. Wicht","doi":"10.1109/EMCCOMPO.2015.7358323","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358323","url":null,"abstract":"There is a growing need for motor drives with improved EMC in various automotive and industrial applications. An often referenced approach to reduce EME is to change the shape of the switching signal to reduce the EMI caused by the voltage and current transitions. This requires very precise gate control of the power MOSFET to achieve better switching behaviour and lower EME without a major increase in switching losses. In order to find an optimal trade-off, this work utilizes a monolithic current mode gate driver with a variable output current that can be changed within 10ns. With this driver, measurements with different gate current profiles were taken. The di/dt transition was confirmed to be as important as the dv/dt transition in the power MOSFET. As a result of the improved switching behavior the emissions were reduced by up to 20dB between 7MHz and 60MHz with a switching loss that is 52% lower than with a constantly low gate current.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131150553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358325
J. Raoult, Pierre Payet, R. Omarouayache, L. Chusseau
Electromagnetic (EM) injection experiments require an accurate and quantitative knowledge of the voltage effectively coupled to a target line or circuit in order to predict disruptive behavior or sensitivity of digital IC circuits to EM threats. To answer this question we derive here a complete quantitative model of the coupling of our magnetic probe to a microstrip line. The novelty of this model is to consider the coupling by analogy with a transformer and then to deduce the corresponding mutual inductance as a function of probe to target relative positions. Its inputs are S-parameter measurements of the actual probe coupled to a 50Ω microstrip line and its output is an electric equivalent circuit that can be implemented in any circuit simulator. Validity of the model extends up to GHz frequencies.
{"title":"Electromagnetic coupling circuit model of a magnetic near-field probe to a microstrip line","authors":"J. Raoult, Pierre Payet, R. Omarouayache, L. Chusseau","doi":"10.1109/EMCCOMPO.2015.7358325","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358325","url":null,"abstract":"Electromagnetic (EM) injection experiments require an accurate and quantitative knowledge of the voltage effectively coupled to a target line or circuit in order to predict disruptive behavior or sensitivity of digital IC circuits to EM threats. To answer this question we derive here a complete quantitative model of the coupling of our magnetic probe to a microstrip line. The novelty of this model is to consider the coupling by analogy with a transformer and then to deduce the corresponding mutual inductance as a function of probe to target relative positions. Its inputs are S-parameter measurements of the actual probe coupled to a 50Ω microstrip line and its output is an electric equivalent circuit that can be implemented in any circuit simulator. Validity of the model extends up to GHz frequencies.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130705335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358337
Sanghyeok Park, H. Huynh, Soyoung Kim
The electromagnetic interference (EMI) generated from the DC-DC buck converter effects the performance of integrated circuits which receive power supply from the buck converter. In this paper, the EMI reduction techniques of DC-DC buck converter are presented. The damping resistor is applied to reduce the output noise of the buck converter. In time domain, this damping resistor technique reduces the output noise of the buck converter significantly but is not effective in reducing high frequency noise components. To resolve this issue, PCB design is modified to contain separate planes for input, output, switching, and ground ports. The TEM-cell, measurement results show that with this modification in addition to the damping resistor, the EMI is significantly reduced over a wide range frequency up to 1GHz.
{"title":"Analysis of EMI reduction methods of DC-DC buck converter","authors":"Sanghyeok Park, H. Huynh, Soyoung Kim","doi":"10.1109/EMCCOMPO.2015.7358337","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358337","url":null,"abstract":"The electromagnetic interference (EMI) generated from the DC-DC buck converter effects the performance of integrated circuits which receive power supply from the buck converter. In this paper, the EMI reduction techniques of DC-DC buck converter are presented. The damping resistor is applied to reduce the output noise of the buck converter. In time domain, this damping resistor technique reduces the output noise of the buck converter significantly but is not effective in reducing high frequency noise components. To resolve this issue, PCB design is modified to contain separate planes for input, output, switching, and ground ports. The TEM-cell, measurement results show that with this modification in addition to the damping resistor, the EMI is significantly reduced over a wide range frequency up to 1GHz.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130236794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358336
Boyuan Zhu, Junwei Lu, Mingcheng Zhu, Mei Jiang
In very-large-scale-integration (VLSI), arbitrary structure of interconnections leads to unpredictable parasitic capacitance that generates EMC issues, i.e., parasitic noise, signal disorder, control failure, data asynchronous, etc. This paper investigates an EMC modelling and optimization method in calculating interconnect capacitance of VLSI interconnects based on the finite element method (FEM). Two- and three-dimensional interconnect models are simulated and the results of capacitance extraction are compared with experimental measurements, which proved the consistency and accuracy of FEM. Furthermore, optimizations of coupling capacitance are applied on multilayer interconnection structures by the non-dominated sorting genetic algorithm II (NSGA-II).
{"title":"Arbitrary shape multilayer interconnects EMC modelling and optimization","authors":"Boyuan Zhu, Junwei Lu, Mingcheng Zhu, Mei Jiang","doi":"10.1109/EMCCOMPO.2015.7358336","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358336","url":null,"abstract":"In very-large-scale-integration (VLSI), arbitrary structure of interconnections leads to unpredictable parasitic capacitance that generates EMC issues, i.e., parasitic noise, signal disorder, control failure, data asynchronous, etc. This paper investigates an EMC modelling and optimization method in calculating interconnect capacitance of VLSI interconnects based on the finite element method (FEM). Two- and three-dimensional interconnect models are simulated and the results of capacitance extraction are compared with experimental measurements, which proved the consistency and accuracy of FEM. Furthermore, optimizations of coupling capacitance are applied on multilayer interconnection structures by the non-dominated sorting genetic algorithm II (NSGA-II).","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133907702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358367
A. Ramanujan, E. Sicard, A. Boyer, J. Levant, C. Marot, F. Lafon
A new international standard proposal (IEC 62433-2 Edition 2.0) is in progress. The main purpose of the standard is to provide an Integrated Circuit Emission Model - Conducted Emission (ICEM-CE) along with a data exchange format. It is known that the existing ICEM-CE information is closely linked to the supplier of the model or simulation software used to generate the model information, rendering extremely difficult its exchange between suppliers, customers, EDA tool vendors, academics, etc. This paper describes a universal exchange format for ICEM-CE. The format is based on the well-known eXtensible Markup Language format, which is both machine and human readable. As an illustrative example, it is applied on an Atmega88 microcontroller: the model is extracted by the manufacturer, Atmel, and is exchanged with an academic partner, INSA, and an industrial partner, Valeo. The exchange proves fruitful and the model was easily deployable to predict conducted emission noise.
{"title":"Developing a universal exchange format for Integrated Circuit Emission Model - Conducted Emissions","authors":"A. Ramanujan, E. Sicard, A. Boyer, J. Levant, C. Marot, F. Lafon","doi":"10.1109/EMCCOMPO.2015.7358367","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358367","url":null,"abstract":"A new international standard proposal (IEC 62433-2 Edition 2.0) is in progress. The main purpose of the standard is to provide an Integrated Circuit Emission Model - Conducted Emission (ICEM-CE) along with a data exchange format. It is known that the existing ICEM-CE information is closely linked to the supplier of the model or simulation software used to generate the model information, rendering extremely difficult its exchange between suppliers, customers, EDA tool vendors, academics, etc. This paper describes a universal exchange format for ICEM-CE. The format is based on the well-known eXtensible Markup Language format, which is both machine and human readable. As an illustrative example, it is applied on an Atmega88 microcontroller: the model is extracted by the manufacturer, Atmel, and is exchanged with an academic partner, INSA, and an industrial partner, Valeo. The exchange proves fruitful and the model was easily deployable to predict conducted emission noise.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114507659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358351
Hyunho Park, D. Kam, Y. Park, Jiseong Kim, Jae-Deok Lim, Hark-Byeong Park, Eakhwan Song
This paper proposes a radio-frequency interference (RFI) evaluation method for flexible flat cables (FFCs), which are commonly employed for high-speed signal transmission in modern mobile devices and become a major path of noise coupling to antennas. The noise coupled from differential-mode and common-mode signals flowing through FFCs is obtained in terms of transfer functions based on S-parameter measurement. Considering the source power from a driver IC on the main board sent to the FFCs, the noise power at the antenna was calculated to evaluate the noise coupling through the FFCs based on a criterion of RFI noise power received at an antenna port. To measure the coupled noise in terms of transfer function, a dedicated evaluation board is designed and fabricated. Several low-voltage differential signaling (LVDS) FFCs used in a real tablet were evaluated based on the proposed method and validated by experimental measurement on RFI noise power at Wi-Fi antenna port using both the evaluation board and the real tablet. A good correlation was achieved between them.
{"title":"RF interference evaluation of flexible flat cables for high-speed data transmission in mobile devices","authors":"Hyunho Park, D. Kam, Y. Park, Jiseong Kim, Jae-Deok Lim, Hark-Byeong Park, Eakhwan Song","doi":"10.1109/EMCCOMPO.2015.7358351","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358351","url":null,"abstract":"This paper proposes a radio-frequency interference (RFI) evaluation method for flexible flat cables (FFCs), which are commonly employed for high-speed signal transmission in modern mobile devices and become a major path of noise coupling to antennas. The noise coupled from differential-mode and common-mode signals flowing through FFCs is obtained in terms of transfer functions based on S-parameter measurement. Considering the source power from a driver IC on the main board sent to the FFCs, the noise power at the antenna was calculated to evaluate the noise coupling through the FFCs based on a criterion of RFI noise power received at an antenna port. To measure the coupled noise in terms of transfer function, a dedicated evaluation board is designed and fabricated. Several low-voltage differential signaling (LVDS) FFCs used in a real tablet were evaluated based on the proposed method and validated by experimental measurement on RFI noise power at Wi-Fi antenna port using both the evaluation board and the real tablet. A good correlation was achieved between them.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"412 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131825984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-10DOI: 10.1109/EMCCOMPO.2015.7358364
E. Sicard, A. Boyer, P. Fernandez-Lopez, A. Zhou, N. Marier, F. Lafon
In this paper, the signal integrity (SI) and Electromagnetic Compatibility (EMC) performance of System-On-Chip (SoC) and stacked memory using Package-On-Package (PoP) technology is investigated. The reconfiguration of the IC-EMC software platform to PoP is described. From an existing 2D assembly using a discrete 65-nm SoC product, the benefits of PoP integration using a next-generation (NG) 28-nm product with stacked memory are analyzed, based on simulation and predictive analysis performed using IC-EMC software platform.
{"title":"EMC performance analysis of a processor/memory system using PCB and Package-On-Package","authors":"E. Sicard, A. Boyer, P. Fernandez-Lopez, A. Zhou, N. Marier, F. Lafon","doi":"10.1109/EMCCOMPO.2015.7358364","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358364","url":null,"abstract":"In this paper, the signal integrity (SI) and Electromagnetic Compatibility (EMC) performance of System-On-Chip (SoC) and stacked memory using Package-On-Package (PoP) technology is investigated. The reconfiguration of the IC-EMC software platform to PoP is described. From an existing 2D assembly using a discrete 65-nm SoC product, the benefits of PoP integration using a next-generation (NG) 28-nm product with stacked memory are analyzed, based on simulation and predictive analysis performed using IC-EMC software platform.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129517154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-10DOI: 10.1109/EMCCOMPO.2015.7358350
A. Boyer, M. Cavarroc
Near-field injection is a promising method for the analysis of the susceptibility of electronic boards and circuits. The resulting immunity map provides a precise localization of the sensitive area to electromagnetic disturbances. A major requirement is the spatial resolution of the immunity map, which depends on the size of the injection probe and the separation distance between the probe and the device under test. This paper aims at proposing a post-processing method to enhance the spatial resolution of immunity map and validating it on case studies at board and integrated circuit levels.
{"title":"Enhancement of the spatial resolution of near-field immunity maps","authors":"A. Boyer, M. Cavarroc","doi":"10.1109/EMCCOMPO.2015.7358350","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358350","url":null,"abstract":"Near-field injection is a promising method for the analysis of the susceptibility of electronic boards and circuits. The resulting immunity map provides a precise localization of the sensitive area to electromagnetic disturbances. A major requirement is the spatial resolution of the immunity map, which depends on the size of the injection probe and the separation distance between the probe and the device under test. This paper aims at proposing a post-processing method to enhance the spatial resolution of immunity map and validating it on case studies at board and integrated circuit levels.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134250765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358342
Philipp Schroeter, F. Klotz, M. Pamato
This paper studies and compares the RF immunity of DC current regulators against electromagnetic interferences (EMIs). The effect of EMI on the performance of a classic topology is analyzed. It turns out, especially the regulators output is very sensitive against EMI since disturbance levels in the millivolt range cause serious malfunctions. Subsequently the paper introduces a structured approach to the design of EMI resistant regulators. RF immunity measurements on IC level (DPI) and on system level (BCI) proof the superior EMC performance of the resisting topologies over the classic regulator, while the electrical characteristics and the area of the circuits are the same. The circuits have been designed using a HV- BiCMOS technology for automotive applications.
{"title":"RF immunity investigations of linear DC current regulators","authors":"Philipp Schroeter, F. Klotz, M. Pamato","doi":"10.1109/EMCCOMPO.2015.7358342","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358342","url":null,"abstract":"This paper studies and compares the RF immunity of DC current regulators against electromagnetic interferences (EMIs). The effect of EMI on the performance of a classic topology is analyzed. It turns out, especially the regulators output is very sensitive against EMI since disturbance levels in the millivolt range cause serious malfunctions. Subsequently the paper introduces a structured approach to the design of EMI resistant regulators. RF immunity measurements on IC level (DPI) and on system level (BCI) proof the superior EMC performance of the resisting topologies over the classic regulator, while the electrical characteristics and the area of the circuits are the same. The circuits have been designed using a HV- BiCMOS technology for automotive applications.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130895408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358365
H. Herrmann, W. Horchler, S. Schwarz, Philipp Schroeter, F. Klotz, Marco Brignone, F. Fiori
This paper deals with the susceptibility to radio frequency interference of smart power integrated circuits. A method to perform simulations aimed at evaluating the performance of subcircuits included in a more complex IC in the presence of EMI is presented. Referring to this, the behaviour of a current sensor included into a high-side power switch during DPI test is investigated. The results of simulation analyses and DPI tests are presented.
{"title":"Smart power IC macromodeling for DPI analysis","authors":"H. Herrmann, W. Horchler, S. Schwarz, Philipp Schroeter, F. Klotz, Marco Brignone, F. Fiori","doi":"10.1109/EMCCOMPO.2015.7358365","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358365","url":null,"abstract":"This paper deals with the susceptibility to radio frequency interference of smart power integrated circuits. A method to perform simulations aimed at evaluating the performance of subcircuits included in a more complex IC in the presence of EMI is presented. Referring to this, the behaviour of a current sensor included into a high-side power switch during DPI test is investigated. The results of simulation analyses and DPI tests are presented.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"57 1-2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114027544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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