Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358361
R. Blečić, R. Gillon, B. Nauwelaers, A. Barić
Radiation characteristics of a loop antenna, small compared to the wavelength and placed centrally above a perforated finite image plane, are presented. Holes in the image plane typically occur in a multilayer printed circuit boards (PCBs) when vias pass through the second layer which serves as a reflector. A 3D finite element method (FEM) electromagnetic (EM) simulation of a System-in-Package (SiP) synchronous buck converter shows a significant impact of the holes on the characteristics of the converter. A parametric analysis of the impact of the number and radius of holes on the radiated characteristics and on the inductance of a small loop antenna above perforated image plane is performed by 3D FEM EM simulations. Guidelines for a design of multilayer PCBs for magnetically driven sources, such as DC-DC converters, are deduced.
{"title":"Radiation characteristics of small loop antenna above perforated finite image plane","authors":"R. Blečić, R. Gillon, B. Nauwelaers, A. Barić","doi":"10.1109/EMCCOMPO.2015.7358361","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358361","url":null,"abstract":"Radiation characteristics of a loop antenna, small compared to the wavelength and placed centrally above a perforated finite image plane, are presented. Holes in the image plane typically occur in a multilayer printed circuit boards (PCBs) when vias pass through the second layer which serves as a reflector. A 3D finite element method (FEM) electromagnetic (EM) simulation of a System-in-Package (SiP) synchronous buck converter shows a significant impact of the holes on the characteristics of the converter. A parametric analysis of the impact of the number and radius of holes on the radiated characteristics and on the inductance of a small loop antenna above perforated image plane is performed by 3D FEM EM simulations. Guidelines for a design of multilayer PCBs for magnetically driven sources, such as DC-DC converters, are deduced.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127536996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358327
Megumi Saito, T. Mizuki, H. Sone, Yu-ichi Hayashi
Correlation Power Analysis (CPA) is one of the typical side-channel analyses targeting cryptographic IC. CPA calculates the Poisson correlation function between transient currents (which are generated from a cryptographic IC depending on the processed data) and hypothetical current values and then recovers the secret key from a high number of correlation computations. Countermeasures against side-channel attacks mainly focus on algorithms and architecture at the design levels. These methods suffer from some problems, e.g., increase in processing time and circuit scale. This paper discusses a countermeasure against CPA, which can be relatively inexpensively and easily implemented. CPA calculates the correlation value between the transient current waveforms and hypothetical current values under the assumption that the specific process that leaks the secret key information is always performed after a certain time from the time when the cryptographic IC starts performing encryption or decryption and recovers the secret key. Therefore, we consider the possibility of randomizing the time when a cryptographic IC runs the process where the secret key information is leaked to suppress the leakage of side-channel information available in recovering the secret key. In this paper, we propose a method of changing the clock frequencies for each encryption or decryption to randomize the time. In our experiment, we employed Side-channel Attack Standard Evaluation Board (SASEBO-G) and implemented Advanced Encryption Standard (AES) on a field-programmable gate array (FPGA) of SASEBO-G. We measured the transient currents in a cryptographic FPGA that was supplied a spread-spectrum clock while it performs AES encryption. We calculated the correlation value between each transient current waveform and a hypothetical current value and demonstrated that this process is effective as a countermeasure against CPA.
{"title":"Fundamental study on randomized processing in cryptographic IC using variable clock against Correlation Power Analysis","authors":"Megumi Saito, T. Mizuki, H. Sone, Yu-ichi Hayashi","doi":"10.1109/EMCCOMPO.2015.7358327","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358327","url":null,"abstract":"Correlation Power Analysis (CPA) is one of the typical side-channel analyses targeting cryptographic IC. CPA calculates the Poisson correlation function between transient currents (which are generated from a cryptographic IC depending on the processed data) and hypothetical current values and then recovers the secret key from a high number of correlation computations. Countermeasures against side-channel attacks mainly focus on algorithms and architecture at the design levels. These methods suffer from some problems, e.g., increase in processing time and circuit scale. This paper discusses a countermeasure against CPA, which can be relatively inexpensively and easily implemented. CPA calculates the correlation value between the transient current waveforms and hypothetical current values under the assumption that the specific process that leaks the secret key information is always performed after a certain time from the time when the cryptographic IC starts performing encryption or decryption and recovers the secret key. Therefore, we consider the possibility of randomizing the time when a cryptographic IC runs the process where the secret key information is leaked to suppress the leakage of side-channel information available in recovering the secret key. In this paper, we propose a method of changing the clock frequencies for each encryption or decryption to randomize the time. In our experiment, we employed Side-channel Attack Standard Evaluation Board (SASEBO-G) and implemented Advanced Encryption Standard (AES) on a field-programmable gate array (FPGA) of SASEBO-G. We measured the transient currents in a cryptographic FPGA that was supplied a spread-spectrum clock while it performs AES encryption. We calculated the correlation value between each transient current waveform and a hypothetical current value and demonstrated that this process is effective as a countermeasure against CPA.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117201076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358324
Mohammed Amellall, S. O. Land, R. Perdriau, M. Ramdani, A. Ahaitouf, M. Drissi
This paper deals with the conducted immunity of SPI EEPROM memories. The design and implementation of a wideband radio frequency-baseband multiplexer are described. This multiplexer makes it possible to superimpose radio frequency noise to a functional baseband signal with controlled and repeatable transfer characteristics. The baseband path has a measured DC - 380MHz bandwidth, while the radio frequency path (up to 1W) has a 150kHz - 5GHz bandwidth. This multiplexer is used to compare the conducted immunity of functional and non-functional pins of EEPROM memories with a single measurement set-up.
{"title":"Direct power injection on functional and non-functional signals of SPI EEPROM memories","authors":"Mohammed Amellall, S. O. Land, R. Perdriau, M. Ramdani, A. Ahaitouf, M. Drissi","doi":"10.1109/EMCCOMPO.2015.7358324","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358324","url":null,"abstract":"This paper deals with the conducted immunity of SPI EEPROM memories. The design and implementation of a wideband radio frequency-baseband multiplexer are described. This multiplexer makes it possible to superimpose radio frequency noise to a functional baseband signal with controlled and repeatable transfer characteristics. The baseband path has a measured DC - 380MHz bandwidth, while the radio frequency path (up to 1W) has a 150kHz - 5GHz bandwidth. This multiplexer is used to compare the conducted immunity of functional and non-functional pins of EEPROM memories with a single measurement set-up.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134316865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358321
T. Mandic, R. Blečić, R. Gillon, A. Barić
This paper presents the dead-time variation analysis and far-field radiation estimation of a DC/DC converter. The critical factors influencing the dead-time variation are identified and their statistical distributions are defined. The statistical distribution of the MOSFET parasitic capacitances is optimized to match the values obtained by measurements. The packaging process variation together with the variation of the printed circuit board properties are identified and transferred into circuit simulator by the response surface methodology (RSM). The RSM models together with the simplified synchronous buck DC/DC converter model is implemented in circuit simulator and Monte Carlo simulation is performed. The dead-time variation is extracted from Monte Carlo simulation results and most significant sources of variation are identified. The switching current extracted from the simulation results is used to estimate variation of the far-field radiation.
{"title":"DC/DC converter dead-time variation analysis and far-field radiation estimation","authors":"T. Mandic, R. Blečić, R. Gillon, A. Barić","doi":"10.1109/EMCCOMPO.2015.7358321","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358321","url":null,"abstract":"This paper presents the dead-time variation analysis and far-field radiation estimation of a DC/DC converter. The critical factors influencing the dead-time variation are identified and their statistical distributions are defined. The statistical distribution of the MOSFET parasitic capacitances is optimized to match the values obtained by measurements. The packaging process variation together with the variation of the printed circuit board properties are identified and transferred into circuit simulator by the response surface methodology (RSM). The RSM models together with the simplified synchronous buck DC/DC converter model is implemented in circuit simulator and Monte Carlo simulation is performed. The dead-time variation is extracted from Monte Carlo simulation results and most significant sources of variation are identified. The switching current extracted from the simulation results is used to estimate variation of the far-field radiation.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125623719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358331
C. Oliveira, L. Poehls, F. Vargas
The use of Real-Time Operating System (RTOS) became a mandatory condition to design safety-critical real-time embedded systems based on multicore processors. At the same time, these systems are becoming more and more sensitive to transient faults originated from a large spectrum of noisy sources such as conducted and radiated Electromagnetic Interference (EMI). Therefore, the system's reliability degrades. In this work, we present a hardware-based infrastructure intellectual property (I-IP) core able to monitor the RTOS' activity in a multicore processor system-on-chip (MPSoC). The final goal is to detect faults that corrupt the task scheduling process in embedded systems based on preemptive RTOS. The I-IP core, namely RTOS-Watchdog (RTOS-WD), was described in VHDL and is connected to the address busses between the cores and their local iCache memories. A case-study based on a MPSoC running different test programs under the control of a typical preemptive RTOS was implemented and exposed to conducted EMI. The obtained results demonstrate that the proposed approach provides higher fault coverage when compared to the native fault detection mechanisms embedded in the kernel of the RTOS.
{"title":"On-chip Watchdog to monitor RTOS activity in MPSoC exposed to noisy environment","authors":"C. Oliveira, L. Poehls, F. Vargas","doi":"10.1109/EMCCOMPO.2015.7358331","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358331","url":null,"abstract":"The use of Real-Time Operating System (RTOS) became a mandatory condition to design safety-critical real-time embedded systems based on multicore processors. At the same time, these systems are becoming more and more sensitive to transient faults originated from a large spectrum of noisy sources such as conducted and radiated Electromagnetic Interference (EMI). Therefore, the system's reliability degrades. In this work, we present a hardware-based infrastructure intellectual property (I-IP) core able to monitor the RTOS' activity in a multicore processor system-on-chip (MPSoC). The final goal is to detect faults that corrupt the task scheduling process in embedded systems based on preemptive RTOS. The I-IP core, namely RTOS-Watchdog (RTOS-WD), was described in VHDL and is connected to the address busses between the cores and their local iCache memories. A case-study based on a MPSoC running different test programs under the control of a typical preemptive RTOS was implemented and exposed to conducted EMI. The obtained results demonstrate that the proposed approach provides higher fault coverage when compared to the native fault detection mechanisms embedded in the kernel of the RTOS.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114205294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358356
Andrea Lavarda, Dominik Amschl, S. Bauer, B. Deutschmann
This paper deals with the characterization of the immunity of integrated circuits (ICs) by means of their susceptibility to conducted radio frequency (RF) electromagnetic interferences (EMI). It describes and analyses a framework to perform such characterization at wafer level, highlighting the benefits that are reaped from it and the problems that can be faced during the test bench setup and the measurement procedure, providing some possible solutions.
{"title":"Characterization of the immunity of integrated circuits (ICs) at wafer level","authors":"Andrea Lavarda, Dominik Amschl, S. Bauer, B. Deutschmann","doi":"10.1109/EMCCOMPO.2015.7358356","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358356","url":null,"abstract":"This paper deals with the characterization of the immunity of integrated circuits (ICs) by means of their susceptibility to conducted radio frequency (RF) electromagnetic interferences (EMI). It describes and analyses a framework to perform such characterization at wafer level, highlighting the benefits that are reaped from it and the problems that can be faced during the test bench setup and the measurement procedure, providing some possible solutions.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"415 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122110096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358363
C. Pouant, J. Raoult, P. Hoffmann
This paper deals with the “in band” and “out band” rectification of a Metal Oxide Semiconductor Field Effect Transistors (MOSFET's) device and proposes a semi-empirical model to predict the rectification effect in all transistor regions. The modeling method is based on two variables Taylor series expansion of ID(VGS, VDS) which shows a modification in drain current due to a gate Radio-Frequency (RF) voltage. This modification depends on the transconductance and conductance derivatives. When the transistor operates in the non-saturation and linear region the conductance becomes an important nonlinear source. However, it can be neglected in the saturation region of the MOSFET.
{"title":"Large domain validity of MOSFET microwave-rectification response","authors":"C. Pouant, J. Raoult, P. Hoffmann","doi":"10.1109/EMCCOMPO.2015.7358363","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358363","url":null,"abstract":"This paper deals with the “in band” and “out band” rectification of a Metal Oxide Semiconductor Field Effect Transistors (MOSFET's) device and proposes a semi-empirical model to predict the rectification effect in all transistor regions. The modeling method is based on two variables Taylor series expansion of ID(VGS, VDS) which shows a modification in drain current due to a gate Radio-Frequency (RF) voltage. This modification depends on the transconductance and conductance derivatives. When the transistor operates in the non-saturation and linear region the conductance becomes an important nonlinear source. However, it can be neglected in the saturation region of the MOSFET.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"316 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133658500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358326
V. Tomasevic, A. Boyer, S. Bendhia
In order to merge low power and high voltage devices on the same chip at competitive cost, Smart Power integrated circuits (ICs) are extensively used. The presence of low power and high voltage devices in Smart Power ICs cause parasitic substrate interaction between switched power stages and sensitive analog blocks. Nowadays this is the major cause of failure of Smart Power ICs inducing costly circuit redesign. Modern CAD tools cannot accurately simulate this type of interaction expressed as an injection of minority carriers in the substrate and their propagation in the substrate. In order to create a link between circuit design, modelling and implementation in innovative CAD tools there is a need to validate these models by measuring the high voltage perturbations that activate parasitic structures. This paper presents a study of bandgap failure issues due to the substrate coupling induced by high power parts of the circuit which can activate parasitic bipolar structures inside the substrate of Smart Power ICs.
{"title":"Bandgap failure study due to parasitic bipolar substrate coupling in Smart Power mixed ICs","authors":"V. Tomasevic, A. Boyer, S. Bendhia","doi":"10.1109/EMCCOMPO.2015.7358326","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358326","url":null,"abstract":"In order to merge low power and high voltage devices on the same chip at competitive cost, Smart Power integrated circuits (ICs) are extensively used. The presence of low power and high voltage devices in Smart Power ICs cause parasitic substrate interaction between switched power stages and sensitive analog blocks. Nowadays this is the major cause of failure of Smart Power ICs inducing costly circuit redesign. Modern CAD tools cannot accurately simulate this type of interaction expressed as an injection of minority carriers in the substrate and their propagation in the substrate. In order to create a link between circuit design, modelling and implementation in innovative CAD tools there is a need to validate these models by measuring the high voltage perturbations that activate parasitic structures. This paper presents a study of bandgap failure issues due to the substrate coupling induced by high power parts of the circuit which can activate parasitic bipolar structures inside the substrate of Smart Power ICs.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127751523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358334
K. Abouda, Guillaume Aulagnier, E. Rolland, M. Cousineau
Inside the car, all integrated circuits “IC” have to be optimized to survive against severe external aggressions. The noise generated by each activity inside each IC must be low enough, to not disturb the environment. As known nowadays, DC-DC converters can significantly impact the Electromagnetic Compatibility “EMC” performances, and mainly the emission ones. Unfortunately, simulation with linear models like ICEM or IBIS models [1, 2] remains very challenging for integrated analogue products due to the high number of parameters, plenty of possible applications and the extent of the frequency domain where the integrated circuit must be compliant. A paper describes an analytical approach to highlight the main contributors to the high frequency noise generated by switching activity in Buck converters [3]. This approach is then employed to reduce Conducted Emission “CE” performance using multiphase interleaved Buck converters and to highlight benefits of increasing the number of phases in improving the emission profile.
{"title":"Analytical approach to study Electromagnetic emission EME contributors on DC/DC applications","authors":"K. Abouda, Guillaume Aulagnier, E. Rolland, M. Cousineau","doi":"10.1109/EMCCOMPO.2015.7358334","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358334","url":null,"abstract":"Inside the car, all integrated circuits “IC” have to be optimized to survive against severe external aggressions. The noise generated by each activity inside each IC must be low enough, to not disturb the environment. As known nowadays, DC-DC converters can significantly impact the Electromagnetic Compatibility “EMC” performances, and mainly the emission ones. Unfortunately, simulation with linear models like ICEM or IBIS models [1, 2] remains very challenging for integrated analogue products due to the high number of parameters, plenty of possible applications and the extent of the frequency domain where the integrated circuit must be compliant. A paper describes an analytical approach to highlight the main contributors to the high frequency noise generated by switching activity in Buck converters [3]. This approach is then employed to reduce Conducted Emission “CE” performance using multiphase interleaved Buck converters and to highlight benefits of increasing the number of phases in improving the emission profile.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129935407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-17DOI: 10.1109/EMCCOMPO.2015.7358343
Thomas Ungru, W. Wilkening, Steffen Walker, R. Negra
This paper presents the analysis of effects and consequences of ESD on an operating integrated communication interface. We used a test structure for a differential bus module and observed its output signal behaviour under conducted ESD gun stress, to our knowledge for the first time. Measurements correlate to our simulations.
{"title":"Functional analysis of an integrated communication interface during ESD","authors":"Thomas Ungru, W. Wilkening, Steffen Walker, R. Negra","doi":"10.1109/EMCCOMPO.2015.7358343","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358343","url":null,"abstract":"This paper presents the analysis of effects and consequences of ESD on an operating integrated communication interface. We used a test structure for a differential bus module and observed its output signal behaviour under conducted ESD gun stress, to our knowledge for the first time. Measurements correlate to our simulations.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114725567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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