Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358358
M. Baran, W. Dehaene, H. Pues, K. Stijnen
Transient disturbance signals are getting more and more attention lately (e.g. in the automotive industry). Electromagnetic compatibility (EMC) at IC level so far focused on continuous wave (CW) disturbances and how to deal with them, but transient phenomena were not thoroughly studied yet. In this exploratory paper, we perform a case study (based on a basic current mirror) in order to reveal the effects of transient disturbances (as compared to CW ones) and to determine what IC design techniques could be used to deal with them.
{"title":"Case study on the differences between EMI resilience of analog ICs against continuous wave, modulated and transient disturbances","authors":"M. Baran, W. Dehaene, H. Pues, K. Stijnen","doi":"10.1109/EMCCOMPO.2015.7358358","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358358","url":null,"abstract":"Transient disturbance signals are getting more and more attention lately (e.g. in the automotive industry). Electromagnetic compatibility (EMC) at IC level so far focused on continuous wave (CW) disturbances and how to deal with them, but transient phenomena were not thoroughly studied yet. In this exploratory paper, we perform a case study (based on a basic current mirror) in order to reveal the effects of transient disturbances (as compared to CW ones) and to determine what IC design techniques could be used to deal with them.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114411608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358330
Y. Bacher, N. Froidevaux, P. Dupre, H. Braquet, G. Jacquemod
To be compliant with electromagnetic compatibility standards, integrated circuits such as microcontrollers have to be robust to fast transient burst tests. Because of high voltage and fast transient voltage variations used no measurement is possible during the stress. Lack of information makes the debug of a product a real challenge. The objective of this work is to provide a measurement method which permits to have more information on the stress propagation on the power supply network. The methodology applied here on fast transient burst test could be extended to other kind of stress on power supply.
{"title":"Resonance analysis for EMC improvement in integrated circuits","authors":"Y. Bacher, N. Froidevaux, P. Dupre, H. Braquet, G. Jacquemod","doi":"10.1109/EMCCOMPO.2015.7358330","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358330","url":null,"abstract":"To be compliant with electromagnetic compatibility standards, integrated circuits such as microcontrollers have to be robust to fast transient burst tests. Because of high voltage and fast transient voltage variations used no measurement is possible during the stress. Lack of information makes the debug of a product a real challenge. The objective of this work is to provide a measurement method which permits to have more information on the stress propagation on the power supply network. The methodology applied here on fast transient burst test could be extended to other kind of stress on power supply.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130664711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358352
Shih-Yi Yuan, Ting-Wei Yeh, Y. Tang, Chiu-Kuo Chen
With substantial progress in Internet of things (IoT), new challenges of EMI on IoT (IoT-EMI) measurement have emerged. The IoT-EMI behaviors are complex and dependent on the target's interactions between hardware and software. A systematic method for IoT-EMI measurement should be developed. However, the characteristics of IoT-EMI are digitally-controlled, time-varying, and software-dependent and make the IoT-EMI measurements difficult by conventional method. This paper proposes a time-domain measurement method for such issue. This method uses a `timestamp' by SW/HW-co-measurement strategy to analysis IoT-EMI behaviors. From the measurement result, the long-term measurements are comparable to the conventional SA measurements. And the software-related IoT-EMI results show tremendous differences - about 5-50 dBuV differences among different application programs are observed. To the best of the authors' knowledge, the software-dependent IoT-EMI behaviors are firstly observed and published.
{"title":"Time-domain EMI measurement methodology","authors":"Shih-Yi Yuan, Ting-Wei Yeh, Y. Tang, Chiu-Kuo Chen","doi":"10.1109/EMCCOMPO.2015.7358352","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358352","url":null,"abstract":"With substantial progress in Internet of things (IoT), new challenges of EMI on IoT (IoT-EMI) measurement have emerged. The IoT-EMI behaviors are complex and dependent on the target's interactions between hardware and software. A systematic method for IoT-EMI measurement should be developed. However, the characteristics of IoT-EMI are digitally-controlled, time-varying, and software-dependent and make the IoT-EMI measurements difficult by conventional method. This paper proposes a time-domain measurement method for such issue. This method uses a `timestamp' by SW/HW-co-measurement strategy to analysis IoT-EMI behaviors. From the measurement result, the long-term measurements are comparable to the conventional SA measurements. And the software-related IoT-EMI results show tremendous differences - about 5-50 dBuV differences among different application programs are observed. To the best of the authors' knowledge, the software-dependent IoT-EMI behaviors are firstly observed and published.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125461995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358339
Andreas Rauchenecker, T. Ostermann
In the presented paper we examine and compare different adder structures for their EMC behavior. On the one hand the analysis is carried out for different topologies as Ripple Carry Adder and Kogge Stone Adder. And on the other hand these topologies are realized in different logic styles as standard CMOS, complementary pass transistor logic, buffered NMOS pass transistor and complementary buffered NMOS pass transistor logic. All these variations are compared over di/dt, power consumption, speed / performance and transistor count. Additionally a new topology for the Kogge Stone Adder is introduced.
{"title":"Examination of different adder structures concerning di/dt in a 180nm technology","authors":"Andreas Rauchenecker, T. Ostermann","doi":"10.1109/EMCCOMPO.2015.7358339","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358339","url":null,"abstract":"In the presented paper we examine and compare different adder structures for their EMC behavior. On the one hand the analysis is carried out for different topologies as Ripple Carry Adder and Kogge Stone Adder. And on the other hand these topologies are realized in different logic styles as standard CMOS, complementary pass transistor logic, buffered NMOS pass transistor and complementary buffered NMOS pass transistor logic. All these variations are compared over di/dt, power consumption, speed / performance and transistor count. Additionally a new topology for the Kogge Stone Adder is introduced.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131806542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358346
Hidetoshi Miyahara, Nobuaki Ikehara, T. Matsushima, T. Hisakado, O. Wada
Because predicting undesired behaviors in IC (Integrated Circuit) due to conducted electromagnetic disturbances is necessary for front-loading the design process, immunity models are becoming more important to predict a malfunction at the design stage of electronic products. In this paper, the failure to function mechanism in a LDO (Low Dropout) voltage regulator is investigated from the aspect of the internal terminal in a circuit. Simulations confirm a relation between the internal reference voltage and the DC shift error at certain frequencies. Thus, monitoring the voltage or current at an internal terminal between functional blocks gives useful information about an IC model to predict immunity.
{"title":"Relation between internal terminal voltage and immunity behavior of LDO regulator circuits","authors":"Hidetoshi Miyahara, Nobuaki Ikehara, T. Matsushima, T. Hisakado, O. Wada","doi":"10.1109/EMCCOMPO.2015.7358346","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358346","url":null,"abstract":"Because predicting undesired behaviors in IC (Integrated Circuit) due to conducted electromagnetic disturbances is necessary for front-loading the design process, immunity models are becoming more important to predict a malfunction at the design stage of electronic products. In this paper, the failure to function mechanism in a LDO (Low Dropout) voltage regulator is investigated from the aspect of the internal terminal in a circuit. Simulations confirm a relation between the internal reference voltage and the DC shift error at certain frequencies. Thus, monitoring the voltage or current at an internal terminal between functional blocks gives useful information about an IC model to predict immunity.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127681996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358362
H. Hackl, G. Winkler, B. Deutschmann
As the electromagnetic compatibility (EMC) of IC products takes on greater significance for competitiveness, IC manufacturers are increasingly interested in evaluating the EMC performance of their products as soon as during the very first design phase without the need of prototypes. There are a number of approaches to predict radiated emissions of automotive components as defined in the CISPR25 standard. However, it can be concluded that none of them are suitable for continuous use by the circuit designer itself because they either need a manufactured prototype and a lab engineer, or lots of simulation time and resources. The designer is normally no EMC expert and does not want to deal with additional, complex simulation tools. This paper presents the generation and use of a simulation model which can easily be implemented in the design environment (e.g. Cadence Virtuoso) used by the designer and does not notably increase the simulation time. The transient data is post-processed with a Matlab script emulating an EMI test receiver.
{"title":"Simulation of radiated emission during the design phase based on scattering parameter measurement","authors":"H. Hackl, G. Winkler, B. Deutschmann","doi":"10.1109/EMCCOMPO.2015.7358362","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358362","url":null,"abstract":"As the electromagnetic compatibility (EMC) of IC products takes on greater significance for competitiveness, IC manufacturers are increasingly interested in evaluating the EMC performance of their products as soon as during the very first design phase without the need of prototypes. There are a number of approaches to predict radiated emissions of automotive components as defined in the CISPR25 standard. However, it can be concluded that none of them are suitable for continuous use by the circuit designer itself because they either need a manufactured prototype and a lab engineer, or lots of simulation time and resources. The designer is normally no EMC expert and does not want to deal with additional, complex simulation tools. This paper presents the generation and use of a simulation model which can easily be implemented in the design environment (e.g. Cadence Virtuoso) used by the designer and does not notably increase the simulation time. The transient data is post-processed with a Matlab script emulating an EMI test receiver.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125525461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358348
Lars Glaesser, S. Koenig
Apart from ESD tests at system level, e.g. according to IEC 61000-4-2, the investigation of the EMC immunity of individual ICs is becoming increasingly important: an ESD sensitive IC could cause problems in subsequent system level tests when in use. Knowing in advance what to expect from an IC can help save time and money in the design process. An appropriate component level test bench is therefore required. Using standard ESD generators (system level test methods) for component level tests can lead to unexpected results. This paper describes problems that can arise when using standard ESD generators in a customised test set-up whereby a microcontroller is used as a DUT (the tested IC) for demonstration purposes.
{"title":"ESD test at component level","authors":"Lars Glaesser, S. Koenig","doi":"10.1109/EMCCOMPO.2015.7358348","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358348","url":null,"abstract":"Apart from ESD tests at system level, e.g. according to IEC 61000-4-2, the investigation of the EMC immunity of individual ICs is becoming increasingly important: an ESD sensitive IC could cause problems in subsequent system level tests when in use. Knowing in advance what to expect from an IC can help save time and money in the design process. An appropriate component level test bench is therefore required. Using standard ESD generators (system level test methods) for component level tests can lead to unexpected results. This paper describes problems that can arise when using standard ESD generators in a customised test set-up whereby a microcontroller is used as a DUT (the tested IC) for demonstration purposes.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131465182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358349
Ahmed Aldabbagh, A. Duffy
In this paper, the Transmission Line Matrix (TLM) method is used to study the electro-thermal performance degradation in RF LDMOS (Radio Frequency - Laterally Diffused Metal Oxide Semiconductor) transistors, through Thermal Cycling Test (TCT), as the temperature is a crucial parameter in RF devices. A hybrid approach is presented, which combines the modelling of thermal diffusion and electric effects within a two dimensional TLM model to observe the device behaviour after simulated ageing, through including the ageing loop in a unified solver. Two sets of test results are compared with published data in order to verify the performance of the proposed hybrid solver. The work shows the suitability of using the TLM to model ageing phenomenon in MOS devices.
由于温度是射频器件的重要参数，本文采用传输线矩阵(TLM)方法，通过热循环测试(TCT)研究射频LDMOS (Radio Frequency - lateral diffusion Metal Oxide Semiconductor，射频横向扩散金属氧化物半导体)晶体管的电热性能退化问题。提出了一种混合方法，该方法结合了二维TLM模型中的热扩散和电效应建模，通过将老化回路包含在统一求解器中来观察模拟老化后的器件行为。为了验证所提出的混合求解器的性能，将两组测试结果与已发表的数据进行了比较。研究表明，使用TLM模型来模拟MOS器件中的老化现象是合适的。
{"title":"Ageing effects on power RF LDMOS reliability using the Transmission Line Matrix method","authors":"Ahmed Aldabbagh, A. Duffy","doi":"10.1109/EMCCOMPO.2015.7358349","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358349","url":null,"abstract":"In this paper, the Transmission Line Matrix (TLM) method is used to study the electro-thermal performance degradation in RF LDMOS (Radio Frequency - Laterally Diffused Metal Oxide Semiconductor) transistors, through Thermal Cycling Test (TCT), as the temperature is a crucial parameter in RF devices. A hybrid approach is presented, which combines the modelling of thermal diffusion and electric effects within a two dimensional TLM model to observe the device behaviour after simulated ageing, through including the ageing loop in a unified solver. Two sets of test results are compared with published data in order to verify the performance of the proposed hybrid solver. The work shows the suitability of using the TLM to model ageing phenomenon in MOS devices.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115379269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358355
J. Dienot, E. Batista, I. Ramos
With constraints for high-level integration of electronics, new EMC behaviors have to be considered to prevent real electromagnetic compliance. Especially, in embedded and on-board device's context, environmental temperature has an influence on the circuit behavior and EMC figures. This paper deals with susceptibility studies combined with temperature effects on electronic devices used to control power and transmissions. Specific dual thermal-electromagnetic test set-up developed for this are presented. Main results of an experimental campaign on digital PCB dedicated for generation of Pulse Width Modulation (PWM) patterns are presented. Temperature dependant susceptibility and sensitivity of the PWM parameters are compared and analyzed.
{"title":"Thermal-electromagnetic susceptibility behaviors of PWM patterns used in control electronic circuit","authors":"J. Dienot, E. Batista, I. Ramos","doi":"10.1109/EMCCOMPO.2015.7358355","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358355","url":null,"abstract":"With constraints for high-level integration of electronics, new EMC behaviors have to be considered to prevent real electromagnetic compliance. Especially, in embedded and on-board device's context, environmental temperature has an influence on the circuit behavior and EMC figures. This paper deals with susceptibility studies combined with temperature effects on electronic devices used to control power and transmissions. Specific dual thermal-electromagnetic test set-up developed for this are presented. Main results of an experimental campaign on digital PCB dedicated for generation of Pulse Width Modulation (PWM) patterns are presented. Temperature dependant susceptibility and sensitivity of the PWM parameters are compared and analyzed.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121137348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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