Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358335
Johannes Gert Janschitz
This paper describes a LIN (Local Interconnect Network) Transmitter designed in a BCD HV technology. The key design target is to comply with EMI (electromagnetic interference) specification limits. The two main aspects are low EME (electromagnetic emission) and sufficient immunity against RF disturbance. A gate driver is proposed which uses a certain current summation network for lowering the slew rate on the one hand and being reliable against radio frequency (RF) disturbances within the automotive environment on the other hand. Nowadays the low cost single wire LIN Bus is used for establishing communication between sensors, actuators and other components.
{"title":"An EMI robust LIN driver with low electromagnetic emission","authors":"Johannes Gert Janschitz","doi":"10.1109/EMCCOMPO.2015.7358335","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358335","url":null,"abstract":"This paper describes a LIN (Local Interconnect Network) Transmitter designed in a BCD HV technology. The key design target is to comply with EMI (electromagnetic interference) specification limits. The two main aspects are low EME (electromagnetic emission) and sufficient immunity against RF disturbance. A gate driver is proposed which uses a certain current summation network for lowering the slew rate on the one hand and being reliable against radio frequency (RF) disturbances within the automotive environment on the other hand. Nowadays the low cost single wire LIN Bus is used for establishing communication between sensors, actuators and other components.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132196773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358332
S. Kapora, Marcel Hanssen, J. Niehof, Quino Sandifort
A simulation methodology to predict and mitigate interferences between different subsystems in complex mixed-signal system-on-chip ICs at the early stages of a design project is presented. Different aspects of the analysis flow and abstraction levels of the models are discussed. The impact of the floorplan and design choices on circuit performance and the relative contribution of different coupling mechanisms are shown on a number of examples. Special attention is paid to on-chip and package coupling effects. The methodology has been validated with silicon measurements and has been successfully applied in the design process of NXP products.
{"title":"Methodology for interference analysis during early design stages of high-performance mixed-signal ICs","authors":"S. Kapora, Marcel Hanssen, J. Niehof, Quino Sandifort","doi":"10.1109/EMCCOMPO.2015.7358332","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358332","url":null,"abstract":"A simulation methodology to predict and mitigate interferences between different subsystems in complex mixed-signal system-on-chip ICs at the early stages of a design project is presented. Different aspects of the analysis flow and abstraction levels of the models are discussed. The impact of the floorplan and design choices on circuit performance and the relative contribution of different coupling mechanisms are shown on a number of examples. Special attention is paid to on-chip and package coupling effects. The methodology has been validated with silicon measurements and has been successfully applied in the design process of NXP products.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115806071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358345
S. Miropolsky, S. Jahn, F. Klotz, S. Frei
A small-signal model of an automotive system-level bulk current injection (BCI) setup developed with a generalized accurate method shown in the previous publication is verified on a case study with a demonstrator EUT module. The work utilizes an equivalent circuit modelling approach for the floating ungrounded EUT board and a macromodel for an active DUT IC. The simulation-based prediction of the BCI test results using an IC failure threshold and a small-signal simulation of RF levels at floating EUT module under BCI tests is shown. Due to high accuracy and detail of the BCI setup model, the prediction also shows very good correlation to real measurement data, both qualitatively and quantitatively, up to 1 GHz.
{"title":"Experimental validation of the generalized accurate modelling method for system-level bulk current injection setups up to 1 GHz","authors":"S. Miropolsky, S. Jahn, F. Klotz, S. Frei","doi":"10.1109/EMCCOMPO.2015.7358345","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358345","url":null,"abstract":"A small-signal model of an automotive system-level bulk current injection (BCI) setup developed with a generalized accurate method shown in the previous publication is verified on a case study with a demonstrator EUT module. The work utilizes an equivalent circuit modelling approach for the floating ungrounded EUT board and a macromodel for an active DUT IC. The simulation-based prediction of the BCI test results using an IC failure threshold and a small-signal simulation of RF levels at floating EUT module under BCI tests is shown. Due to high accuracy and detail of the BCI setup model, the prediction also shows very good correlation to real measurement data, both qualitatively and quantitatively, up to 1 GHz.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115459224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358360
Satoshi Tanaka, Peng Fan, Jingyan Ma, H. Aoki, M. Yamaguchi, M. Nagata, S. Muroga
In-band spurious tones of a LTE-class radio frequency integrated circuit (RFIC) receiver test element group (TEG) chip was studied in order to evaluate the degree of noise suppression by means of soft magnetic thin film. A 2-μm-thick crossed anisotropy multilayered Co-Zr-Nb film was applied onto the passivation layer of TEG chip. The in-band spurious was suppressed by 10 dB while it had no influence upon wanted signal. A magnetic near field map measured in the 2.1 GHz range indicated several noise coupling paths on chip, which were compared with the chip layout design to estimate victim wires. EM simulation model in connection with circuit simulation is carefully constructed. RF control wirings were most responsible wires than other wires and air couplings. EM simulation predicted the magnetic film should suppress noise by the maximum of 33 dB while it was 10 dB experimentally because of Si substrate coupling and board coupling.
{"title":"Analysis of on-chip digital noise coupling path for wireless communication IC test chip","authors":"Satoshi Tanaka, Peng Fan, Jingyan Ma, H. Aoki, M. Yamaguchi, M. Nagata, S. Muroga","doi":"10.1109/EMCCOMPO.2015.7358360","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358360","url":null,"abstract":"In-band spurious tones of a LTE-class radio frequency integrated circuit (RFIC) receiver test element group (TEG) chip was studied in order to evaluate the degree of noise suppression by means of soft magnetic thin film. A 2-μm-thick crossed anisotropy multilayered Co-Zr-Nb film was applied onto the passivation layer of TEG chip. The in-band spurious was suppressed by 10 dB while it had no influence upon wanted signal. A magnetic near field map measured in the 2.1 GHz range indicated several noise coupling paths on chip, which were compared with the chip layout design to estimate victim wires. EM simulation model in connection with circuit simulation is carefully constructed. RF control wirings were most responsible wires than other wires and air couplings. EM simulation predicted the magnetic film should suppress noise by the maximum of 33 dB while it was 10 dB experimentally because of Si substrate coupling and board coupling.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116322615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358353
Boyuan Zhu, Junwei Lu, Ling Sun, Haiyan Sun
System-in-package (SiP) encloses multiple dies in a single package which is much sensitive to electromagnetic interference due to its intensive internal density and complicated internal structure. This paper presents computational analysis of shielding performance by modelling, simulation and optimization of a radio frequency integrated circuit (RFIC) in SiP using a self-developed virtual electromagnetic compatibility (VEMC) system. The system is designed and proved for computational electromagnetics needs in high performance computation and visualization. Multi-objective optimisation in package thickness, material conductivity, number and order of shielding derives an optimal shielding effectiveness for the discussed package.
{"title":"Computational electromagnetics in shielding analysis of system in package","authors":"Boyuan Zhu, Junwei Lu, Ling Sun, Haiyan Sun","doi":"10.1109/EMCCOMPO.2015.7358353","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358353","url":null,"abstract":"System-in-package (SiP) encloses multiple dies in a single package which is much sensitive to electromagnetic interference due to its intensive internal density and complicated internal structure. This paper presents computational analysis of shielding performance by modelling, simulation and optimization of a radio frequency integrated circuit (RFIC) in SiP using a self-developed virtual electromagnetic compatibility (VEMC) system. The system is designed and proved for computational electromagnetics needs in high performance computation and visualization. Multi-objective optimisation in package thickness, material conductivity, number and order of shielding derives an optimal shielding effectiveness for the discussed package.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124678805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358341
Philipp Schroeter, Fabio Ballarin, F. Fiori
Current sensors are usually protected against electromagnetic interference (EMI) by means of filters placed at the PCB level. The literature has plenty of solutions aimed at keeping EMI filters' attenuation as high as possible in the widest possible frequency range. However such filters are less effective than expected because of the parasitic elements introduced by interconnects. As a consequence, EMI can be propagated into ICs causing temporary or definitive operation failures. This paper points out the causes of EMI-induced errors in high-side current sensors based on low-offset chopper OTAs. Analyses presented in the paper are supported by direct power injection measurements carried out on a test chip.
{"title":"Susceptibility to EMI of high side current sensors based on chopper OpAmps","authors":"Philipp Schroeter, Fabio Ballarin, F. Fiori","doi":"10.1109/EMCCOMPO.2015.7358341","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358341","url":null,"abstract":"Current sensors are usually protected against electromagnetic interference (EMI) by means of filters placed at the PCB level. The literature has plenty of solutions aimed at keeping EMI filters' attenuation as high as possible in the widest possible frequency range. However such filters are less effective than expected because of the parasitic elements introduced by interconnects. As a consequence, EMI can be propagated into ICs causing temporary or definitive operation failures. This paper points out the causes of EMI-induced errors in high-side current sensors based on low-offset chopper OTAs. Analyses presented in the paper are supported by direct power injection measurements carried out on a test chip.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132285188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358333
Andrea Lavarda, B. Deutschmann
This paper deals with low offset operational amplifiers. It shows an innovative approach to design an operational amplifier (OpAMP) which combines two different techniques that make it able to handle both the technological and the radio frequency interference (RFI) induced offset.
{"title":"EMI improved chopped operational amplifier","authors":"Andrea Lavarda, B. Deutschmann","doi":"10.1109/EMCCOMPO.2015.7358333","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358333","url":null,"abstract":"This paper deals with low offset operational amplifiers. It shows an innovative approach to design an operational amplifier (OpAMP) which combines two different techniques that make it able to handle both the technological and the radio frequency interference (RFI) induced offset.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116114268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358338
Mario Rotigni, M. Merlo, M. Cordoni, P. Colombo, V. Liberali
This paper presents the design of a silicon test chip specially conceived to study the noise propagation trough the silicon substrate in order to build up a model to be used in simulating EMC performances -both emission (EME) and immunity (EMI)- and to be able to predict early in advance, before silicon fabrication, EME-EMI characteristics. The chip is realized in 40 nm CMOS technology, the one used for the realization of automotive microcontroller. Four versions of the chip are presented and some measurements are shown. This first paper focuses on emissions aspects, even if the schematic architecture and layout has been developed to cover immunity phenomenon too. To understand the role played by the silicon substrate as propagation medium (noise internally generated to outside or to convey the external environment interferences into the silicon circuitries), the ESD pin protections have been removed on two versions of the test chip. The same electrical architecture is also proposed in different layout designs: with and without the Deep N-Well (DNW) implant allowing isolation of p-well substrates, to evaluate the benefit of this process technique. Previous work is discussed, and new hypotheses and emission measurements are shown. This work is focused on the basic version of the test chip, without DNW and ESD protection, to highlight noise propagation due to the substrate only, without intervention of different physical structures.
{"title":"Role of IC substrate and ESD protections in noise propagation: Design and modelling of dedicated test chip in 40 nm technology","authors":"Mario Rotigni, M. Merlo, M. Cordoni, P. Colombo, V. Liberali","doi":"10.1109/EMCCOMPO.2015.7358338","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358338","url":null,"abstract":"This paper presents the design of a silicon test chip specially conceived to study the noise propagation trough the silicon substrate in order to build up a model to be used in simulating EMC performances -both emission (EME) and immunity (EMI)- and to be able to predict early in advance, before silicon fabrication, EME-EMI characteristics. The chip is realized in 40 nm CMOS technology, the one used for the realization of automotive microcontroller. Four versions of the chip are presented and some measurements are shown. This first paper focuses on emissions aspects, even if the schematic architecture and layout has been developed to cover immunity phenomenon too. To understand the role played by the silicon substrate as propagation medium (noise internally generated to outside or to convey the external environment interferences into the silicon circuitries), the ESD pin protections have been removed on two versions of the test chip. The same electrical architecture is also proposed in different layout designs: with and without the Deep N-Well (DNW) implant allowing isolation of p-well substrates, to evaluate the benefit of this process technique. Previous work is discussed, and new hypotheses and emission measurements are shown. This work is focused on the basic version of the test chip, without DNW and ESD protection, to highlight noise propagation due to the substrate only, without intervention of different physical structures.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123065909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358366
Jaemin Lim, Manho Lee, D. Jung, Jonghoon J. Kim, Sumin Choi, Hyunsuk Lee, Joungho Kim
Through silicon via (TSV) has been extensively highlighted as the key solution for small form factor wide bandwidth, and low power consumption with compactly integrating multiple chips. Despite the many advantages of TSV based 3-dimensional integrated circuit (3D IC), there are several challenges to be overcome such as noise coupling, fabrication process limits, and failure issues. In this paper, we proposed shielding structures for TSV to active circuit noise coupling in 3D IC. The proposed structures can capture TSV substrate noise by blocking the noise paths to active circuit, LC-VCO in this study. The noise suppression mechanisms are analyzed by the noise coupling coefficient in frequency-domain obtained by 3D electromagnetic simulation. Various shielding structures are investigated and compared with regard to sensitivity of active circuit, such as phase noise of LC-VCO.
{"title":"Shielding structures for through silicon via (TSV) to active circuit noise coupling in 3D IC","authors":"Jaemin Lim, Manho Lee, D. Jung, Jonghoon J. Kim, Sumin Choi, Hyunsuk Lee, Joungho Kim","doi":"10.1109/EMCCOMPO.2015.7358366","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358366","url":null,"abstract":"Through silicon via (TSV) has been extensively highlighted as the key solution for small form factor wide bandwidth, and low power consumption with compactly integrating multiple chips. Despite the many advantages of TSV based 3-dimensional integrated circuit (3D IC), there are several challenges to be overcome such as noise coupling, fabrication process limits, and failure issues. In this paper, we proposed shielding structures for TSV to active circuit noise coupling in 3D IC. The proposed structures can capture TSV substrate noise by blocking the noise paths to active circuit, LC-VCO in this study. The noise suppression mechanisms are analyzed by the noise coupling coefficient in frequency-domain obtained by 3D electromagnetic simulation. Various shielding structures are investigated and compared with regard to sensitivity of active circuit, such as phase noise of LC-VCO.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129834458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/EMCCOMPO.2015.7358347
JongTae Hwang, Youngbong Han, Hyunho Park, W. Nah, Soyoung Kim
As system integration in wireless portable electronic devices has increased significantly, the analysis of electromagnetic compatibility (EMC) has become important to prevent the malfunction of integrated circuits (ICs). To evaluate the radiative immunity of an integrated circuit, we employ the IEC-standardized IC stripline method. In this paper, we provide an electromagnetic immunity analysis of the radiated electromagnetic noise coupling from an IC stripline to a ring voltage-controlled oscillator (VCO). We present the design of an IC stripline that meets the IEC 62132-8 standard, the test setup and the experimental results of the VCO test chip. The measurement shows that the radio frequency (RF) source from the IC stripline causes changes in the center frequency and output characteristics. VCO output variations show that the design is relatively immune to radiated noise of the same frequency as the oscillator output, and the output frequency spectrum spreads out more with higher noise amplitude due to injection. The experiment shows that the IC stripline method is an effective solution for the radiated electromagnetic analysis of an IC.
{"title":"Radiated electromagnetic immunity analysis of VCO using IC stripline method","authors":"JongTae Hwang, Youngbong Han, Hyunho Park, W. Nah, Soyoung Kim","doi":"10.1109/EMCCOMPO.2015.7358347","DOIUrl":"https://doi.org/10.1109/EMCCOMPO.2015.7358347","url":null,"abstract":"As system integration in wireless portable electronic devices has increased significantly, the analysis of electromagnetic compatibility (EMC) has become important to prevent the malfunction of integrated circuits (ICs). To evaluate the radiative immunity of an integrated circuit, we employ the IEC-standardized IC stripline method. In this paper, we provide an electromagnetic immunity analysis of the radiated electromagnetic noise coupling from an IC stripline to a ring voltage-controlled oscillator (VCO). We present the design of an IC stripline that meets the IEC 62132-8 standard, the test setup and the experimental results of the VCO test chip. The measurement shows that the radio frequency (RF) source from the IC stripline causes changes in the center frequency and output characteristics. VCO output variations show that the design is relatively immune to radiated noise of the same frequency as the oscillator output, and the output frequency spectrum spreads out more with higher noise amplitude due to injection. The experiment shows that the IC stripline method is an effective solution for the radiated electromagnetic analysis of an IC.","PeriodicalId":236992,"journal":{"name":"2015 10th International Workshop on the Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116317933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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