Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123250
E.M. Aleman
The author introduces automated schematic capture configuration for the UCS51 embedded microcontroller, which is based on the 80C51 microcontroller, and its five accompanying peripherals. In addition, current automation applications are outlined. The UCS51 design entry tool, a menu-driven automated schematic capture/configuration procedure, is discussed step by step, menu by menu. The discussion includes mapping the peripheral registers into the special function register bus where they may be directly accessed to support the full logical functions of the core's instruction set. 'How to' and sample schematics are shown for each configuration. Future and related applications are also explored.<>
{"title":"Automated schematic capture and the UCS51 (microcontroller)","authors":"E.M. Aleman","doi":"10.1109/ASIC.1989.123250","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123250","url":null,"abstract":"The author introduces automated schematic capture configuration for the UCS51 embedded microcontroller, which is based on the 80C51 microcontroller, and its five accompanying peripherals. In addition, current automation applications are outlined. The UCS51 design entry tool, a menu-driven automated schematic capture/configuration procedure, is discussed step by step, menu by menu. The discussion includes mapping the peripheral registers into the special function register bus where they may be directly accessed to support the full logical functions of the core's instruction set. 'How to' and sample schematics are shown for each configuration. Future and related applications are also explored.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128557125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123184
G. Pham, K. Schmitt
An ASIC (application-specific integrated circuit) first-in-first-out (FIFO) memory circuit that has the capability of interfacing two data processing units operating at different speeds is described. The memory is implemented using a circular queue structure, which permits writing and reading of data indefinitely as long as the boundary flag conditions are not met. This memory also has the capability to retransmit only bad data words, not whole memory blocks as most standard FIFOs do. Another feature is dual-port memory operation, which allows bidirectional data transfers through the FIFO. All of the circuit implementations are done using NCR standard cells. This allows the use of automatic routing and test program generation tools provided by NCR VISYS.<>
{"title":"A high throughput, asynchronous, dual port FIFO memory implemented in ASIC technology","authors":"G. Pham, K. Schmitt","doi":"10.1109/ASIC.1989.123184","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123184","url":null,"abstract":"An ASIC (application-specific integrated circuit) first-in-first-out (FIFO) memory circuit that has the capability of interfacing two data processing units operating at different speeds is described. The memory is implemented using a circular queue structure, which permits writing and reading of data indefinitely as long as the boundary flag conditions are not met. This memory also has the capability to retransmit only bad data words, not whole memory blocks as most standard FIFOs do. Another feature is dual-port memory operation, which allows bidirectional data transfers through the FIFO. All of the circuit implementations are done using NCR standard cells. This allows the use of automatic routing and test program generation tools provided by NCR VISYS.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"66 50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116990782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123178
T. Takei, M. Sekine, H. Nishi, T. Kitahara, A. Masuda
Design time reduction to a half of what was previously required was achieved by a register-transfer-level (RTL) design procedure. The problems encountered in rule-based synthesis were identified through a detailed comparison of the manual logic design procedure with the rule-based logic synthesis procedure. A logic synthesizer using a rule base for local transformations was developed that is able to generate practical logic circuits, even if the RTL descriptions for the circuits are large. The synthesized logic circuits are influenced by the form of the RTL descriptions. The logic synthesizer must generate the good logic circuits, using the meaning of the macro function. The logic synthesizer, using the local optimization, cannot remove the redundancy of the deep if-clause-nesting without the circuit semantics. If there are rules that clear the gates to allow the signal to move forward, more satisfactory optimization will be realized.<>
{"title":"A case study of functional design using functional simulation and logic synthesis","authors":"T. Takei, M. Sekine, H. Nishi, T. Kitahara, A. Masuda","doi":"10.1109/ASIC.1989.123178","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123178","url":null,"abstract":"Design time reduction to a half of what was previously required was achieved by a register-transfer-level (RTL) design procedure. The problems encountered in rule-based synthesis were identified through a detailed comparison of the manual logic design procedure with the rule-based logic synthesis procedure. A logic synthesizer using a rule base for local transformations was developed that is able to generate practical logic circuits, even if the RTL descriptions for the circuits are large. The synthesized logic circuits are influenced by the form of the RTL descriptions. The logic synthesizer must generate the good logic circuits, using the meaning of the macro function. The logic synthesizer, using the local optimization, cannot remove the redundancy of the deep if-clause-nesting without the circuit semantics. If there are rules that clear the gates to allow the signal to move forward, more satisfactory optimization will be realized.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124108214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123207
L. Kovács, M. Gaffney
A description is given of the realities of an implementation of a microprocessor-based design using a standard cell ASIC (application-specific integrated circuit). The entire design process is described from specifications and vendor selection through schematic capture, testability, and simulation. The ASIC design was implemented using the UCS51 family of microcontroller cells. An attempt is made to clarify the problems associated with the beta site nature of the project.<>
{"title":"The realities of core based ASIC design: a single-loop industrial process controller","authors":"L. Kovács, M. Gaffney","doi":"10.1109/ASIC.1989.123207","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123207","url":null,"abstract":"A description is given of the realities of an implementation of a microprocessor-based design using a standard cell ASIC (application-specific integrated circuit). The entire design process is described from specifications and vendor selection through schematic capture, testability, and simulation. The ASIC design was implemented using the UCS51 family of microcontroller cells. An attempt is made to clarify the problems associated with the beta site nature of the project.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126909386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123186
H. Ishihara, K. Tanaka, K. Sakiyama
A single-polysilicon flip-flop EEPROM has been developed. A single-polysilicon structure which is suitable for ASIC (application-specific integrated circuit) application and a flip-flop-type cell give an endurance of more than 1,000,000 cycles. With this technology, a one-chip computer with CPU, RAM, ROM, some I/O ports, and EEPROM has been fabricated.<>
{"title":"A single-polysilicon flip-flop EEPROM for ASIC application","authors":"H. Ishihara, K. Tanaka, K. Sakiyama","doi":"10.1109/ASIC.1989.123186","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123186","url":null,"abstract":"A single-polysilicon flip-flop EEPROM has been developed. A single-polysilicon structure which is suitable for ASIC (application-specific integrated circuit) application and a flip-flop-type cell give an endurance of more than 1,000,000 cycles. With this technology, a one-chip computer with CPU, RAM, ROM, some I/O ports, and EEPROM has been fabricated.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114719116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123215
J. Schmit, E. Maurau, P. Guebels, M. Van Camp
The Alcatel Bell methodology for ASIC (application-specific integrated circuit) design is presented, showing the feasibility of a high degree of circuit reusability. The methodology is supported by a proprietary integrated ASIC CAD system, providing access to libraries and technologies of various ASIC vendors. A considerable reduction in design effort is gained due to reusing and/or adapting components of a library constructed from building blocks created during previous designs. This is illustrated by the design of the network access interface circuit (NAIC), a key component in a telecommunication cross-connect system.<>
{"title":"A network access interface ASIC for a cross-connect system","authors":"J. Schmit, E. Maurau, P. Guebels, M. Van Camp","doi":"10.1109/ASIC.1989.123215","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123215","url":null,"abstract":"The Alcatel Bell methodology for ASIC (application-specific integrated circuit) design is presented, showing the feasibility of a high degree of circuit reusability. The methodology is supported by a proprietary integrated ASIC CAD system, providing access to libraries and technologies of various ASIC vendors. A considerable reduction in design effort is gained due to reusing and/or adapting components of a library constructed from building blocks created during previous designs. This is illustrated by the design of the network access interface circuit (NAIC), a key component in a telecommunication cross-connect system.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129407838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123181
J. M. Avery
A developmental approach for hardware implementations of neural networks is presented. Neural network architectural representations including both behavioral and structural influences are presented using the VHSIC High-Level Description Language (VHDL). VHDL design entities and configurations are applied to neural network algorithm development and simulation. Neural network design interchange formats are discussed.<>
{"title":"Neural network development using VHDL","authors":"J. M. Avery","doi":"10.1109/ASIC.1989.123181","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123181","url":null,"abstract":"A developmental approach for hardware implementations of neural networks is presented. Neural network architectural representations including both behavioral and structural influences are presented using the VHSIC High-Level Description Language (VHDL). VHDL design entities and configurations are applied to neural network algorithm development and simulation. Neural network design interchange formats are discussed.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133518575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123171
L. D'Luna
Electronic imaging places stringent demands on the signal processing circuitry for real-time operation. Dedicated processors that are algorithmic-specific are very attractive from speed, cost, and size considerations. The design of a digital image processing chip-set that falls in this domain is discussed. The design methodology, which includes circuit technologies for CMOS logic, memory, and datapath, together with the tools that ease layout, simulation, verification, and test, are described.<>
{"title":"Design of integrated circuits for electronic imaging applications","authors":"L. D'Luna","doi":"10.1109/ASIC.1989.123171","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123171","url":null,"abstract":"Electronic imaging places stringent demands on the signal processing circuitry for real-time operation. Dedicated processors that are algorithmic-specific are very attractive from speed, cost, and size considerations. The design of a digital image processing chip-set that falls in this domain is discussed. The design methodology, which includes circuit technologies for CMOS logic, memory, and datapath, together with the tools that ease layout, simulation, verification, and test, are described.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121806136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123216
A. Weidner, J. J. Farrell
The use of several chip sets for the IBM PC/AT-type system, which offered cost and performance advantages over other standard discrete implementation, is discussed. It is shown that using ASIC (application-specific integrated circuit) techniques allows not only huge device count reductions, but also permits further, proprietary ASIC advances for enhanced or unique functions. A system based on the devices described uses more than 70 fewer devices than are found originally on the IBM motherboard, yet provides almost three times the performance, as well as added functionality.<>
{"title":"PC/AT-compatible devices: fewer is better","authors":"A. Weidner, J. J. Farrell","doi":"10.1109/ASIC.1989.123216","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123216","url":null,"abstract":"The use of several chip sets for the IBM PC/AT-type system, which offered cost and performance advantages over other standard discrete implementation, is discussed. It is shown that using ASIC (application-specific integrated circuit) techniques allows not only huge device count reductions, but also permits further, proprietary ASIC advances for enhanced or unique functions. A system based on the devices described uses more than 70 fewer devices than are found originally on the IBM motherboard, yet provides almost three times the performance, as well as added functionality.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"897 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127146705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123243
S. Somanchi, M. Manwaring, M. F. Chowdhury
The stringent requirement of precision in the design of analog integrated circuit layout for correct functionality and reasonable performance warrant the use of parameterized module generators. A methodology for the design of a module generator is developed which outputs the mask-level topological description of the layout of the specified analog circuit and a (circuit-level) simulation model that includes the operational sensitivities of the circuit. The effectiveness of this methodology is demonstrated by the example of a generator for an operational transconductance amplifier.<>
{"title":"An analog module generator that includes operational sensitivities","authors":"S. Somanchi, M. Manwaring, M. F. Chowdhury","doi":"10.1109/ASIC.1989.123243","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123243","url":null,"abstract":"The stringent requirement of precision in the design of analog integrated circuit layout for correct functionality and reasonable performance warrant the use of parameterized module generators. A methodology for the design of a module generator is developed which outputs the mask-level topological description of the layout of the specified analog circuit and a (circuit-level) simulation model that includes the operational sensitivities of the circuit. The effectiveness of this methodology is demonstrated by the example of a generator for an operational transconductance amplifier.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126831114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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