Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123195
Jhing-Fa Wang, T. Kuo, Jau-Yien Lee
A test generation procedure to derive robust two-pattern tests for stuck-open faults is presented, based on the concept of using single-fault test sets for multiple-fault detection. If the tests of all single stuck-open faults at the checkpoints can be obtained, the resulting test set will detect all the multiple stuck-open faults in the circuit. It is shown how the fault selection ordering affects the fault coverage, and a fault selection rule is suggested to improve the test generation and fault coverage. A test generation system based on the test generation procedure and fault selection rule has been implemented in C language on a SUN workstation. Several examples are given to demonstrate the versatility of the test generation procedure.<>
{"title":"Test generation for multiple stuck-open faults in CMOS logic circuits","authors":"Jhing-Fa Wang, T. Kuo, Jau-Yien Lee","doi":"10.1109/ASIC.1989.123195","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123195","url":null,"abstract":"A test generation procedure to derive robust two-pattern tests for stuck-open faults is presented, based on the concept of using single-fault test sets for multiple-fault detection. If the tests of all single stuck-open faults at the checkpoints can be obtained, the resulting test set will detect all the multiple stuck-open faults in the circuit. It is shown how the fault selection ordering affects the fault coverage, and a fault selection rule is suggested to improve the test generation and fault coverage. A test generation system based on the test generation procedure and fault selection rule has been implemented in C language on a SUN workstation. Several examples are given to demonstrate the versatility of the test generation procedure.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125917644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123211
M. Williams, J. Nurmi, H. Tenhunen
An ASIC (application-specific integrated circuit) design for a linear-phase ECG (electrocardiogram) filter is presented. The filter utilizes a novel recursive multiplierless architecture. A bit-serial approach has been chosen to keep circuit area and power consumption as small as possible. The implementation has been done using partly full custom and partly standard cell techniques, yielding high transistor density and gate array design efficiency. In the implementation module generators have been used to allow flexible altering of the filter structure.<>
{"title":"ASIC design of digital ECG filter","authors":"M. Williams, J. Nurmi, H. Tenhunen","doi":"10.1109/ASIC.1989.123211","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123211","url":null,"abstract":"An ASIC (application-specific integrated circuit) design for a linear-phase ECG (electrocardiogram) filter is presented. The filter utilizes a novel recursive multiplierless architecture. A bit-serial approach has been chosen to keep circuit area and power consumption as small as possible. The implementation has been done using partly full custom and partly standard cell techniques, yielding high transistor density and gate array design efficiency. In the implementation module generators have been used to allow flexible altering of the filter structure.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131804056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123235
K. E. Dubowski
The ASIC (application-specific integrated circuit) designer often searches through various ASIC databooks trying to locate a cell that the design requires. If it is not possible to find the cell needed, the designer either changes the design so it can be implemented using cells that are available or requests the development of a custom cell from the ASIC supplier. A discussion is presented of custom cell development considerations for standard cell designs. The benefits and risks of custom cell development are examined, and recommendations for minimizing the risks are made.<>
{"title":"Custom cell development for standard cell designs","authors":"K. E. Dubowski","doi":"10.1109/ASIC.1989.123235","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123235","url":null,"abstract":"The ASIC (application-specific integrated circuit) designer often searches through various ASIC databooks trying to locate a cell that the design requires. If it is not possible to find the cell needed, the designer either changes the design so it can be implemented using cells that are available or requests the development of a custom cell from the ASIC supplier. A discussion is presented of custom cell development considerations for standard cell designs. The benefits and risks of custom cell development are examined, and recommendations for minimizing the risks are made.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124856364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123245
R. Melville, A. Yiannoulos
The authors describe a system which is able automatically to bring to the attention of the designer significant performance sensitivities which are introduced through interconnection parasitics. The input to the tool is a SPICE file and a performance specification provided by a designer. The output is again a SPICE file, but augmented with those interconnection parasitics which are most significant for the performance specification prescribed by the designer. The value attached to a parasitic is a quantitative estimate of how significant the parasitic is. This information is derived from a simulation of the circuit prior to layout. The list of most significant routing parasitics could be used to provide feedback to a human designer, direct an automatic layout tool, or guide a circuit extractor.<>
{"title":"Predictive analysis of sensitivity to chip-routing parasitics","authors":"R. Melville, A. Yiannoulos","doi":"10.1109/ASIC.1989.123245","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123245","url":null,"abstract":"The authors describe a system which is able automatically to bring to the attention of the designer significant performance sensitivities which are introduced through interconnection parasitics. The input to the tool is a SPICE file and a performance specification provided by a designer. The output is again a SPICE file, but augmented with those interconnection parasitics which are most significant for the performance specification prescribed by the designer. The value attached to a parasitic is a quantitative estimate of how significant the parasitic is. This information is derived from a simulation of the circuit prior to layout. The list of most significant routing parasitics could be used to provide feedback to a human designer, direct an automatic layout tool, or guide a circuit extractor.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121696890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123165
S. Kung
An application-specific array processor (ASAP) means a high-speed, application-driven, massively parallel, modular, and programmable computing system. The ever-increasing super-high-speed requirement (in giga/tera FLOPS) in modern engineering applications suggests that mainframe scientific computers will not be adequate for many real-time signal/image processing and scientific computing applications. Therefore, the new trend of real-time computing systems points to special-purpose parallel processors, whose architecture is dictated by the very rich underlying algorithmic structures and therefore optimized for high-speed processing of large arrays of data. It is also recognized that a fast-turnaround design environment will be in a great demand for such parallel processing systems. This has become more realistic and more compelling with the increasingly mature VLSI and CAD technology. Therefore, a major advance in the state of the art in the next decade or so is expected. How to effectively design an application-specific parallel processing system which leads to a fast-turnaround design methodology is discussed.<>
{"title":"Application-specific array processors","authors":"S. Kung","doi":"10.1109/ASIC.1989.123165","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123165","url":null,"abstract":"An application-specific array processor (ASAP) means a high-speed, application-driven, massively parallel, modular, and programmable computing system. The ever-increasing super-high-speed requirement (in giga/tera FLOPS) in modern engineering applications suggests that mainframe scientific computers will not be adequate for many real-time signal/image processing and scientific computing applications. Therefore, the new trend of real-time computing systems points to special-purpose parallel processors, whose architecture is dictated by the very rich underlying algorithmic structures and therefore optimized for high-speed processing of large arrays of data. It is also recognized that a fast-turnaround design environment will be in a great demand for such parallel processing systems. This has become more realistic and more compelling with the increasingly mature VLSI and CAD technology. Therefore, a major advance in the state of the art in the next decade or so is expected. How to effectively design an application-specific parallel processing system which leads to a fast-turnaround design methodology is discussed.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128548418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123242
R. Harjani, Rob A. Rutenbar, L. Carley
A description is given of a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks, each with associated design knowledge. The author also describes mechanisms for selecting from among alternate design styles and translating performance specifications from one level in the hierarchy to the next lower level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers and comparators from a set of performance specifications and process parameters. The role such a synthesis system can play in exploring the space of designable circuits is examined.<>
{"title":"OASYS: a framework for analog circuit synthesis","authors":"R. Harjani, Rob A. Rutenbar, L. Carley","doi":"10.1109/ASIC.1989.123242","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123242","url":null,"abstract":"A description is given of a hierarchical structure for a knowledge-based analog circuit synthesis tool. Analog circuit topologies are represented as a hierarchy of abstract functional blocks, each with associated design knowledge. The author also describes mechanisms for selecting from among alternate design styles and translating performance specifications from one level in the hierarchy to the next lower level. A prototype implementation, OASYS, synthesizes sized transistor schematics for CMOS operational amplifiers and comparators from a set of performance specifications and process parameters. The role such a synthesis system can play in exploring the space of designable circuits is examined.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128701740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123234
B. Bates
ASICs (application-specific integrated circuits) have been successfully designed at the component level using engineering workstations (EWS) since the early eighties. Although many workstations allow 'right-first-time' chips to be produced, they do not always offer system designers a secure link for the incorporation of these chips into the overall system. The author explores the needs, features and benefits of future workstation products for which the ASIC design process is an integral part of the system design activity.<>
{"title":"Painless ASIC design in the system environment","authors":"B. Bates","doi":"10.1109/ASIC.1989.123234","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123234","url":null,"abstract":"ASICs (application-specific integrated circuits) have been successfully designed at the component level using engineering workstations (EWS) since the early eighties. Although many workstations allow 'right-first-time' chips to be produced, they do not always offer system designers a secure link for the incorporation of these chips into the overall system. The author explores the needs, features and benefits of future workstation products for which the ASIC design process is an integral part of the system design activity.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124431820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123224
D. Steele
A study has been undertaken to investigate the ground bounce phenomena in CMOS ASICs (application-specific integrated circuits). A simple mathematical analysis was performed to help gain an intuitive understanding of the problem. SPICE simulations were then performed to build a more detailed model. The SPICE model allowed different problem solving approaches to be compared in a straightforward manner. Laboratory experiments were performed to confirm the validity of the simulation and mathematical analyses. The results indicate that there are effective measures which can be taken to reduce the magnitude of voltage transients induced by the device and to minimize the device's sensitivity to ground bounce.<>
{"title":"Ground bounce in CMOS ASICs","authors":"D. Steele","doi":"10.1109/ASIC.1989.123224","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123224","url":null,"abstract":"A study has been undertaken to investigate the ground bounce phenomena in CMOS ASICs (application-specific integrated circuits). A simple mathematical analysis was performed to help gain an intuitive understanding of the problem. SPICE simulations were then performed to build a more detailed model. The SPICE model allowed different problem solving approaches to be compared in a straightforward manner. Laboratory experiments were performed to confirm the validity of the simulation and mathematical analyses. The results indicate that there are effective measures which can be taken to reduce the magnitude of voltage transients induced by the device and to minimize the device's sensitivity to ground bounce.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116118311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123170
M. Jain
A description is given of different paths available for a designer in implementing an ASIC (application-specific integrated circuit). ASIC implementation can be long, complicated, and risky if the choices are not made correctly at the beginning of the project. ASICs can be implemented using a vendor design center, distributor design center, independent design center, or a captive/in-house design center. The pros and cons of each approach and the issues the designer should be aware of before selecting a design center are discussed.<>
{"title":"Choosing a design center","authors":"M. Jain","doi":"10.1109/ASIC.1989.123170","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123170","url":null,"abstract":"A description is given of different paths available for a designer in implementing an ASIC (application-specific integrated circuit). ASIC implementation can be long, complicated, and risky if the choices are not made correctly at the beginning of the project. ASICs can be implemented using a vendor design center, distributor design center, independent design center, or a captive/in-house design center. The pros and cons of each approach and the issues the designer should be aware of before selecting a design center are discussed.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116779512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123251
N. Ballinger
The author explores the challenges for ASIC (application-specific integrated circuit) technical training, now and in the future, in the area of standard product vs. ASIC training (i.e. microcontrollers). She examines the opportunity for setting the ASIC customer up for success through training. Specifically, the author introduces a method for training designed to reduce the risk involved in ASIC design. She explores some future opportunities for educating industry and universities in the area of ASIC design.<>
{"title":"ASIC technical training-the challenges and opportunities","authors":"N. Ballinger","doi":"10.1109/ASIC.1989.123251","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123251","url":null,"abstract":"The author explores the challenges for ASIC (application-specific integrated circuit) technical training, now and in the future, in the area of standard product vs. ASIC training (i.e. microcontrollers). She examines the opportunity for setting the ASIC customer up for success through training. Specifically, the author introduces a method for training designed to reduce the risk involved in ASIC design. She explores some future opportunities for educating industry and universities in the area of ASIC design.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117043898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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