Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123169
L. Yee, Y. Yung
The authors give designers who are not familiar with ECL (emitter-coupled logic) ASICs (application-specific integrated circuits) the basic knowledge necessary for starting an ECL array design. They cover basic ECL ASIC technology and explain how to take advantage of its unique features. The issue of power consumption and methods for reducing it are discussed in detail.<>
{"title":"ECL ASIC, a practical choice of high performance systems","authors":"L. Yee, Y. Yung","doi":"10.1109/ASIC.1989.123169","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123169","url":null,"abstract":"The authors give designers who are not familiar with ECL (emitter-coupled logic) ASICs (application-specific integrated circuits) the basic knowledge necessary for starting an ECL array design. They cover basic ECL ASIC technology and explain how to take advantage of its unique features. The issue of power consumption and methods for reducing it are discussed in detail.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114322348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123174
T. Wong
The objective of Hi-BiCMOS is to combine speed performance approaching that of ECL and integration density approaching that of CMOS. A high-performance 1.3- mu m BiCMOS technology and its applications to ASICs (application-specific integrated circuits) are described. This Hi-BiCMOS gate array contains 3072 gates and 90 input/output buffers. The inclusion of bipolar transistors enables this array to support both TTL (transistor-transistor logic) and ECL logic interfaces. A Hi-BiCMOS memory-plus-logic gate array has also been fabricated using a 1.3- mu m drawn two-layer metal silicon gate process technology. It contains approximately 10 K logic gates, 4.6 kb of triple port RAM, and 220 input/output buffers. A Hi-BiCMOS standard cell library has been developed to improve design productivity in microprocessor designs. Megacells such as ALUs, registers, ROMs, RAMs, multipliers and other macrofunctions are available as part of the macro library.<>
Hi-BiCMOS的目标是将接近ECL的速度性能和接近CMOS的集成密度结合起来。介绍了一种高性能1.3 μ m BiCMOS技术及其在专用集成电路(asic)中的应用。这个Hi-BiCMOS门阵列包含3072个门和90个输入/输出缓冲器。双极晶体管的包含使该阵列能够支持TTL(晶体管-晶体管逻辑)和ECL逻辑接口。采用1.3 μ m的两层金属硅栅极工艺技术制备了Hi-BiCMOS存储加逻辑栅极阵列。它包含大约10 K逻辑门，4.6 kb的三端口RAM和220个输入/输出缓冲区。开发了Hi-BiCMOS标准单元库，以提高微处理器设计的设计效率。巨单元，如alu，寄存器，rom, ram，乘法器和其他宏函数都可以作为宏库的一部分
{"title":"Perspective on BiCMOS","authors":"T. Wong","doi":"10.1109/ASIC.1989.123174","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123174","url":null,"abstract":"The objective of Hi-BiCMOS is to combine speed performance approaching that of ECL and integration density approaching that of CMOS. A high-performance 1.3- mu m BiCMOS technology and its applications to ASICs (application-specific integrated circuits) are described. This Hi-BiCMOS gate array contains 3072 gates and 90 input/output buffers. The inclusion of bipolar transistors enables this array to support both TTL (transistor-transistor logic) and ECL logic interfaces. A Hi-BiCMOS memory-plus-logic gate array has also been fabricated using a 1.3- mu m drawn two-layer metal silicon gate process technology. It contains approximately 10 K logic gates, 4.6 kb of triple port RAM, and 220 input/output buffers. A Hi-BiCMOS standard cell library has been developed to improve design productivity in microprocessor designs. Megacells such as ALUs, registers, ROMs, RAMs, multipliers and other macrofunctions are available as part of the macro library.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128153621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123203
M. Manley
There are numerous complex tasks involved in the construction and verifications of a customized ASIC (application-specific integrated circuit) system design. Intel's UCS51 design entry tool (UCS51 DET) greatly simplifies this process by automating schematic capture of the intricate connections between an ASIC version of the 80C51 microcontroller and its associated peripheral cells. Furthermore, the resulting configuration is guaranteed correct by construction. A description is given of the UCS51 DET and its integration into Intel's design verification system.<>
{"title":"Automation of core-based design construction","authors":"M. Manley","doi":"10.1109/ASIC.1989.123203","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123203","url":null,"abstract":"There are numerous complex tasks involved in the construction and verifications of a customized ASIC (application-specific integrated circuit) system design. Intel's UCS51 design entry tool (UCS51 DET) greatly simplifies this process by automating schematic capture of the intricate connections between an ASIC version of the 80C51 microcontroller and its associated peripheral cells. Furthermore, the resulting configuration is guaranteed correct by construction. A description is given of the UCS51 DET and its integration into Intel's design verification system.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126455018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123249
L. Fuller
The Rochester Institute of Technology has established a factory operation within its cleanroom facility. The factory coexists with class laboratory instruction and research. About one lot per week is released into the factory, and processing is completed automatically by paid student operators several weeks later. The customers for the factory are students and faculty involved in VLSI design courses in Electrical Engineering or Computer Engineering. Other customers included the Microelectronic Engineering faculty and staff and graduate students from a variety of programs. The factory supports a variety of processes, such as NMOS and bipolar. A description is given of the organization and operation of this student-operated factory.<>
{"title":"A university flexible technology foundry for VLSI application specific integrated circuits","authors":"L. Fuller","doi":"10.1109/ASIC.1989.123249","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123249","url":null,"abstract":"The Rochester Institute of Technology has established a factory operation within its cleanroom facility. The factory coexists with class laboratory instruction and research. About one lot per week is released into the factory, and processing is completed automatically by paid student operators several weeks later. The customers for the factory are students and faculty involved in VLSI design courses in Electrical Engineering or Computer Engineering. Other customers included the Microelectronic Engineering faculty and staff and graduate students from a variety of programs. The factory supports a variety of processes, such as NMOS and bipolar. A description is given of the organization and operation of this student-operated factory.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120990480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123192
J. Couleur, S. Cravatta
The device-level testing of an application-specific integrated circuit (ASIC) that is designed using VLSI cores and LSI peripheral cells is discussed. The Intel ASIC UCS51 microcontroller product family is described, and the UCS51 test methodology is compared to that of the Intel standard product 80C51. A solution that provides the ASIC customer with a flexible design environment without compromising device testing is accomplished by employing built-in test modes, which are designed into the microcontroller core and accessed through a minimal amount of device package pins.<>
{"title":"Applying testability to an ASIC architectural core","authors":"J. Couleur, S. Cravatta","doi":"10.1109/ASIC.1989.123192","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123192","url":null,"abstract":"The device-level testing of an application-specific integrated circuit (ASIC) that is designed using VLSI cores and LSI peripheral cells is discussed. The Intel ASIC UCS51 microcontroller product family is described, and the UCS51 test methodology is compared to that of the Intel standard product 80C51. A solution that provides the ASIC customer with a flexible design environment without compromising device testing is accomplished by employing built-in test modes, which are designed into the microcontroller core and accessed through a minimal amount of device package pins.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123366260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123222
L. Greggain, B. White
It is argued that although fault grading is generally used as a measure of the completeness of the test program, it has an even greater potential in measuring the integrity of the functional analysis as performed by the logic simulation. A brief description of stuck-at-1 and stuck-at-0 fault simulation is given. Fault simulation is contrasted with the typical controllability and observability measures, and the benefits of high fault coverage are examined. A number of standard techniques for improving fault coverage are discussed.<>
{"title":"Fault grading, a measure of logic simulation integrity","authors":"L. Greggain, B. White","doi":"10.1109/ASIC.1989.123222","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123222","url":null,"abstract":"It is argued that although fault grading is generally used as a measure of the completeness of the test program, it has an even greater potential in measuring the integrity of the functional analysis as performed by the logic simulation. A brief description of stuck-at-1 and stuck-at-0 fault simulation is given. Fault simulation is contrasted with the typical controllability and observability measures, and the benefits of high fault coverage are examined. A number of standard techniques for improving fault coverage are discussed.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134208864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123182
S. Purcell, M. Handa, R. L. Steinweg
An integrated set of design languages is presented for describing the various outputs of a cell compiler within VLSI Technology's ASIC (application-specific integrated circuit) design tool environment. The outputs include physical layout, netlists of several types, various external attributes of the compiled cell, and test vectors. The languages were designed with the goal of being simple enough to enable software-inexperienced circuit designers to create complex cell compilers independently. The languages, which follow a consistent format and use intuitive constructs, increase compiler development productivity significantly, primarily by removing the software engineer from the compiler development tool.<>
{"title":"A new language suite for designer-specifiable ASIC cell compilers","authors":"S. Purcell, M. Handa, R. L. Steinweg","doi":"10.1109/ASIC.1989.123182","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123182","url":null,"abstract":"An integrated set of design languages is presented for describing the various outputs of a cell compiler within VLSI Technology's ASIC (application-specific integrated circuit) design tool environment. The outputs include physical layout, netlists of several types, various external attributes of the compiled cell, and test vectors. The languages were designed with the goal of being simple enough to enable software-inexperienced circuit designers to create complex cell compilers independently. The languages, which follow a consistent format and use intuitive constructs, increase compiler development productivity significantly, primarily by removing the software engineer from the compiler development tool.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132588023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123179
R. Alessi, B. Roitblat
How logic synthesis can be integrated in a full-chip ASIC (application-specific integrated circuit) design system to maximize the design process is discussed. The discussion is based around the specifics of the ChipCrafter ASIC design system. It is shown that the logic synthesis can speed the implementation of glue or control logic and allow the user to explore the design space for optimal tradeoffs between area and delay. When coupled with a full-chip design system, the synthesis tools can weigh detailed information about actual area and delay, including interconnect area and loading, for more accurate design tradeoffs. Logic blocks account for only a portion of most designs. It is not enough to optimize the logic isolation. An integrated system, which can consider the logic in the context of the entire design, may be able to achieve a significant improvement over chip layout and logic synthesis accomplished separately.<>
{"title":"Integrating logic synthesis into a full chip ASIC design system","authors":"R. Alessi, B. Roitblat","doi":"10.1109/ASIC.1989.123179","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123179","url":null,"abstract":"How logic synthesis can be integrated in a full-chip ASIC (application-specific integrated circuit) design system to maximize the design process is discussed. The discussion is based around the specifics of the ChipCrafter ASIC design system. It is shown that the logic synthesis can speed the implementation of glue or control logic and allow the user to explore the design space for optimal tradeoffs between area and delay. When coupled with a full-chip design system, the synthesis tools can weigh detailed information about actual area and delay, including interconnect area and loading, for more accurate design tradeoffs. Logic blocks account for only a portion of most designs. It is not enough to optimize the logic isolation. An integrated system, which can consider the logic in the context of the entire design, may be able to achieve a significant improvement over chip layout and logic synthesis accomplished separately.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132715512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123233
S. J. Easley, E.E. Freeman, D. Steele
With the market-driven need to reduce product development times in the face of increasing complexity, the ability to forecast ASIC (application-specific integrated circuit) development time has become of paramount importance. The authors present techniques to forecast schedules more accurately, to minimize risks, and to improve productivity on a continuing basis. They found that it is critical to have a specification and a resource team; otherwise, schedule slips are almost certain. They point out that during the development process, tradeoffs must be made by the ASIC designer. To do so effectively, he or she must understand the end application. Risks need assessing and contingency planning. Scheduling itself must be addressed in three senses: future (forecasts), present (monitors) and past (data). The historical database helps to forecast as well as to identify opportunities for productivity improvement.<>
{"title":"ASIC design project scheduling","authors":"S. J. Easley, E.E. Freeman, D. Steele","doi":"10.1109/ASIC.1989.123233","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123233","url":null,"abstract":"With the market-driven need to reduce product development times in the face of increasing complexity, the ability to forecast ASIC (application-specific integrated circuit) development time has become of paramount importance. The authors present techniques to forecast schedules more accurately, to minimize risks, and to improve productivity on a continuing basis. They found that it is critical to have a specification and a resource team; otherwise, schedule slips are almost certain. They point out that during the development process, tradeoffs must be made by the ASIC designer. To do so effectively, he or she must understand the end application. Risks need assessing and contingency planning. Scheduling itself must be addressed in three senses: future (forecasts), present (monitors) and past (data). The historical database helps to forecast as well as to identify opportunities for productivity improvement.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129251027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123158
D. Braune, D. Ibarra, H. Courjon
Advanced testability techniques are described for ASIC (application-specific integrated circuit) design. BIST (built-in self-test), scan test, boundary scan, embedded cores, and mixed-signal circuitry are among the topics discussed. A CAE methodology and a specific case study are analyzed for each ASIC design choice. Emphasis is on modular design for test, automated testability analyses, and comprehensive pattern generation.<>
{"title":"ASIC design for testability","authors":"D. Braune, D. Ibarra, H. Courjon","doi":"10.1109/ASIC.1989.123158","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123158","url":null,"abstract":"Advanced testability techniques are described for ASIC (application-specific integrated circuit) design. BIST (built-in self-test), scan test, boundary scan, embedded cores, and mixed-signal circuitry are among the topics discussed. A CAE methodology and a specific case study are analyzed for each ASIC design choice. Emphasis is on modular design for test, automated testability analyses, and comprehensive pattern generation.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127797203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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