Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123200
V. LaBuda
One high-performance technology, ECL (emitter-coupled logic), is emerging with an innovative architecture, derived from identified customer needs, which blurs the distinction between current gate arrays and cell-based products. Short of being full custom, the customer definable array (CDA) approach used for the Motorola MCAIV MCA50000ECL gate array benefits large functional units like multipliers, barrel shifters, and ALUs. Some pragmatic aspects of the architecture-silicon relationship are examined for the UDA megacell design technique embracing ECL and BiCMOS on the same chip. The MCAIV ECL CDA impact on chip specifications is examined by describing various tiles-such as 4:1 MUX, latch D-flip-flop with gated inputs and a full adder-used as logic components, and by comparing their implementation on conventional arrays with the compacted CDA; similar tiles also have their place in memory implementations. Like comparisons of higher-level functions (e.g. multipliers, barrel shifters) built from these primitives are explored.<>
{"title":"Implications of a new architectural approach to designing ECL megacells","authors":"V. LaBuda","doi":"10.1109/ASIC.1989.123200","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123200","url":null,"abstract":"One high-performance technology, ECL (emitter-coupled logic), is emerging with an innovative architecture, derived from identified customer needs, which blurs the distinction between current gate arrays and cell-based products. Short of being full custom, the customer definable array (CDA) approach used for the Motorola MCAIV MCA50000ECL gate array benefits large functional units like multipliers, barrel shifters, and ALUs. Some pragmatic aspects of the architecture-silicon relationship are examined for the UDA megacell design technique embracing ECL and BiCMOS on the same chip. The MCAIV ECL CDA impact on chip specifications is examined by describing various tiles-such as 4:1 MUX, latch D-flip-flop with gated inputs and a full adder-used as logic components, and by comparing their implementation on conventional arrays with the compacted CDA; similar tiles also have their place in memory implementations. Like comparisons of higher-level functions (e.g. multipliers, barrel shifters) built from these primitives are explored.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121737921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123231
M. F. Chowdhury, M. Manwaring, S. Somanchi
Design issues in analog IC design are discussed. Heuristic algorithms are considered as a means of reducing the computational complexity of the problem. A module generator for an op amp, which incorporates heuristic algorithms to choose circuit technology and reduce crosstalk in the placement and routing of the layout, is presented.<>
{"title":"Heuristic issues in analog IC design","authors":"M. F. Chowdhury, M. Manwaring, S. Somanchi","doi":"10.1109/ASIC.1989.123231","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123231","url":null,"abstract":"Design issues in analog IC design are discussed. Heuristic algorithms are considered as a means of reducing the computational complexity of the problem. A module generator for an op amp, which incorporates heuristic algorithms to choose circuit technology and reduce crosstalk in the placement and routing of the layout, is presented.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"518 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123113683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123210
S.G. Smith, R. Morgan, J. Payne
A CAD system for design and synthesis of high-performance processors tailored to digital signal processing (DSP) applications is described. A unique design capture system supports independent specification of processor function, throughput, and accuracy, while a powerful circuit generation system isolates designers from details of the processor implementation. Circuits are assembled automatically according to an architectural blueprint, which is flexible enough in its use of innate parallelism to meet a wide range of throughput requirements with minimal waste of resources. The authors illustrate some multiplier instances in the parameter space and provide several snapshots from a design case study.<>
{"title":"Design automation system and architecture for high-performance integer applications","authors":"S.G. Smith, R. Morgan, J. Payne","doi":"10.1109/ASIC.1989.123210","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123210","url":null,"abstract":"A CAD system for design and synthesis of high-performance processors tailored to digital signal processing (DSP) applications is described. A unique design capture system supports independent specification of processor function, throughput, and accuracy, while a powerful circuit generation system isolates designers from details of the processor implementation. Circuits are assembled automatically according to an architectural blueprint, which is flexible enough in its use of innate parallelism to meet a wide range of throughput requirements with minimal waste of resources. The authors illustrate some multiplier instances in the parameter space and provide several snapshots from a design case study.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134282758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123187
T. Wong, M. El-Khatib
A 10 K-gate BiCMOS gate array with a configurable 4.6-kb SRAM (static RAM) has been developed using a 1.3- mu m technology. The propagation delay time of a two-input NAND is 0.45 ns at 0.6-pF load. The on-chip memory can be configured as *9, *18, *36 b. A description is given of the device structure, the basic cell design, the memory configuration, and the performance of this memory-plus-logic combination.<>
{"title":"A 1.3 mu m BiCMOS gate array with configurable on-chip 3-port RAM","authors":"T. Wong, M. El-Khatib","doi":"10.1109/ASIC.1989.123187","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123187","url":null,"abstract":"A 10 K-gate BiCMOS gate array with a configurable 4.6-kb SRAM (static RAM) has been developed using a 1.3- mu m technology. The propagation delay time of a two-input NAND is 0.45 ns at 0.6-pF load. The on-chip memory can be configured as *9, *18, *36 b. A description is given of the device structure, the basic cell design, the memory configuration, and the performance of this memory-plus-logic combination.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134155480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123240
J. Harrison
A description is given of the Zygen timing model generator tool, which provides engineers with a method for producing gate-level timing models more accurately and more quickly than by using hand calculations. The problem of assigning delays through multiple delay paths ranges from a trivial to a very complex task. The complexity arises when timing paths are reconvergent, overlapping, subdivided by nonoverlapping clocks, or when the model contains simulator-specific functions for which timings cannot be easily mapped. Zygen overcomes this complexity by employing the Zycad Magnum II hardware accelerator, Intel's reference simulator, in determining valid data paths throughout the model. In addition, it employs the power of the Simplex algorithm in solving the system of linear timing equations. A description of the algorithm and capabilities of Zygen is presented with two examples of how Zygen solved the timing problem.<>
介绍了Zygen时序模型生成工具，该工具为工程师提供了一种比手工计算更准确、更快速地生成门级时序模型的方法。通过多个延迟路径分配延迟的问题范围从琐碎到非常复杂的任务。当计时路径重新收敛、重叠、被不重叠的时钟细分时，或者当模型包含无法轻松映射计时的特定于模拟器的功能时，复杂性就会出现。Zygen通过采用Zycad Magnum II硬件加速器(英特尔的参考模拟器)来确定整个模型的有效数据路径，从而克服了这种复杂性。此外，它还利用单纯形算法的强大功能来求解线性时序方程组。介绍了Zygen的算法和功能，并举例说明了Zygen如何解决时序问题
{"title":"Zygen timing model generator","authors":"J. Harrison","doi":"10.1109/ASIC.1989.123240","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123240","url":null,"abstract":"A description is given of the Zygen timing model generator tool, which provides engineers with a method for producing gate-level timing models more accurately and more quickly than by using hand calculations. The problem of assigning delays through multiple delay paths ranges from a trivial to a very complex task. The complexity arises when timing paths are reconvergent, overlapping, subdivided by nonoverlapping clocks, or when the model contains simulator-specific functions for which timings cannot be easily mapped. Zygen overcomes this complexity by employing the Zycad Magnum II hardware accelerator, Intel's reference simulator, in determining valid data paths throughout the model. In addition, it employs the power of the Simplex algorithm in solving the system of linear timing equations. A description of the algorithm and capabilities of Zygen is presented with two examples of how Zygen solved the timing problem.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134360014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123188
J. Houghten
The increasing magnitude of bipolar ASIC (application-specific integrated circuit) arrays allows single-chip designs of up to 50 K gates. To take full advantage of these solitary chip systems, high-performance, ECL, bipolar arrays with large and small on-chip efficient memory architectures must be available. Motorola's MCA4 50 k ECL customer definable array (CDA), an approach that meets these needs through offering gate array or optional semicustom portions of ECL (emitter coupled logic) bipolar and BiCMOS custom memory on a single chip, is discussed. It is shown that ECL memories with less than 2-ns access times are practical for configurations of up to 4 kb. For larger memories, embedded BiCMOS RAMs of up to 180 kb can be implemented on half of an otherwise 50 k ECL array. Besides process flexibility, the array allows the designer to perform layout techniques using tiles (fully diffused macros adhering to the gate array row grid) as fundamental building blocks for the memory cells and RAM auxiliary logic. Implications of using embedded memories and large arrays are addressed.<>
双极ASIC(专用集成电路)阵列的增加幅度允许单芯片设计高达50 K门。为了充分利用这些单独的芯片系统，必须提供具有大小片上高效存储器架构的高性能ECL双极阵列。讨论了摩托罗拉的MCA4 50 k ECL客户可定义阵列(CDA)，通过在单芯片上提供门阵列或ECL(发射极耦合逻辑)双极和BiCMOS自定义存储器的可选半定制部分来满足这些需求。结果表明，访问时间小于2ns的ECL存储器对于高达4kb的配置是实用的。对于更大的存储器，可在50k ECL阵列的一半上实现高达180kb的嵌入式BiCMOS ram。除了过程的灵活性，阵列允许设计者使用瓦片(完全扩散的宏附着在门阵列行网格上)来执行布局技术，作为存储单元和RAM辅助逻辑的基本构建块。讨论了使用嵌入式存储器和大型阵列的含义。
{"title":"ECL and BiCMOS application specific memories (ASMs) on a single chip","authors":"J. Houghten","doi":"10.1109/ASIC.1989.123188","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123188","url":null,"abstract":"The increasing magnitude of bipolar ASIC (application-specific integrated circuit) arrays allows single-chip designs of up to 50 K gates. To take full advantage of these solitary chip systems, high-performance, ECL, bipolar arrays with large and small on-chip efficient memory architectures must be available. Motorola's MCA4 50 k ECL customer definable array (CDA), an approach that meets these needs through offering gate array or optional semicustom portions of ECL (emitter coupled logic) bipolar and BiCMOS custom memory on a single chip, is discussed. It is shown that ECL memories with less than 2-ns access times are practical for configurations of up to 4 kb. For larger memories, embedded BiCMOS RAMs of up to 180 kb can be implemented on half of an otherwise 50 k ECL array. Besides process flexibility, the array allows the designer to perform layout techniques using tiles (fully diffused macros adhering to the gate array row grid) as fundamental building blocks for the memory cells and RAM auxiliary logic. Implications of using embedded memories and large arrays are addressed.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123015748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123190
A. Cron
Products aimed at standardization and cost reduction of IC and system test and debug, compatible with the JTAG/IEEE-1149.1 scan protocols and standards, are discussed. Included are ASIC (application-specific integrated circuit) cells, standard interface ICs, a bus master IC, a controller interface board for IBM compatibles, a high-speed scan interface, and software to control the scan bus. Tradeoffs to be looked at when using the JTAG/IEEE-1149.1 standard for ASIC are evaluated.<>
{"title":"IEEE-1149.1 use in design for verification and testability at Texas Instruments","authors":"A. Cron","doi":"10.1109/ASIC.1989.123190","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123190","url":null,"abstract":"Products aimed at standardization and cost reduction of IC and system test and debug, compatible with the JTAG/IEEE-1149.1 scan protocols and standards, are discussed. Included are ASIC (application-specific integrated circuit) cells, standard interface ICs, a bus master IC, a controller interface board for IBM compatibles, a high-speed scan interface, and software to control the scan bus. Tradeoffs to be looked at when using the JTAG/IEEE-1149.1 standard for ASIC are evaluated.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122912346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123161
J. Seaton
A description is given of the principles of fault simulation, fault modeling techniques and the economic benefits of fault simulation. The principles of fault simulation are discussed, including serial, parallel, and concurrent fault simulation algorithms. Digital faults, fault coverage, and fault mechanisms typically found in digital circuits are described. The tradeoffs of fault placement, fault collapsing algorithms, and the ability to discover different physical defects through fault simulation are discussed. Economic benefits are shown through empirical examples and through correlating fault coverage to average defect levels resulting after manufacturing test.<>
{"title":"Fault simulation basics","authors":"J. Seaton","doi":"10.1109/ASIC.1989.123161","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123161","url":null,"abstract":"A description is given of the principles of fault simulation, fault modeling techniques and the economic benefits of fault simulation. The principles of fault simulation are discussed, including serial, parallel, and concurrent fault simulation algorithms. Digital faults, fault coverage, and fault mechanisms typically found in digital circuits are described. The tradeoffs of fault placement, fault collapsing algorithms, and the ability to discover different physical defects through fault simulation are discussed. Economic benefits are shown through empirical examples and through correlating fault coverage to average defect levels resulting after manufacturing test.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116734913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123217
G. Lakshmikanth, M. Abd-El-Barr, H. Raafat, R. Bolton
A systolic-array-based architecture for texture distance computation is presented. Texture information is extracted and then represented as a set of histograms for various texture features. On the basis of this representation and the concept of event set distance, a transportation-like simplex algorithm is used to compute the texture distances between pairs of textures. Using this algorithm, the texture matching process is reduced to finding a solution to the streamlined transportation simplex problem. The solution to this problem requires two algorithms. The first algorithm is used to obtain the initial basic feasible solution (IBFS) based on Russel's approximation. The second algorithm tests the optimality of the computed IBFS. The authors also present the design and implementation of a prototype VLSI chip which maps the systolic implementation of the two algorithms onto silicon.<>
{"title":"An integrated circuit for texture distance computation","authors":"G. Lakshmikanth, M. Abd-El-Barr, H. Raafat, R. Bolton","doi":"10.1109/ASIC.1989.123217","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123217","url":null,"abstract":"A systolic-array-based architecture for texture distance computation is presented. Texture information is extracted and then represented as a set of histograms for various texture features. On the basis of this representation and the concept of event set distance, a transportation-like simplex algorithm is used to compute the texture distances between pairs of textures. Using this algorithm, the texture matching process is reduced to finding a solution to the streamlined transportation simplex problem. The solution to this problem requires two algorithms. The first algorithm is used to obtain the initial basic feasible solution (IBFS) based on Russel's approximation. The second algorithm tests the optimality of the computed IBFS. The authors also present the design and implementation of a prototype VLSI chip which maps the systolic implementation of the two algorithms onto silicon.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130175818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-09-25DOI: 10.1109/ASIC.1989.123221
R.T. Aparicio, P. Hallinan
A study is presented on fault grading of the OST (operation self-test) for a Delco VHSIC 1750A computer in its early design phases, using a commercially available hardware accelerator. The OST fault-grading effort illustrated the need for design methodologies that take into consideration the capabilities of today's CAE tools. A fault simulation methodology and design guidelines for optimizing the fault grading performance on these large systems are discussed.<>
{"title":"Fault grading operational self-test","authors":"R.T. Aparicio, P. Hallinan","doi":"10.1109/ASIC.1989.123221","DOIUrl":"https://doi.org/10.1109/ASIC.1989.123221","url":null,"abstract":"A study is presented on fault grading of the OST (operation self-test) for a Delco VHSIC 1750A computer in its early design phases, using a commercially available hardware accelerator. The OST fault-grading effort illustrated the need for design methodologies that take into consideration the capabilities of today's CAE tools. A fault simulation methodology and design guidelines for optimizing the fault grading performance on these large systems are discussed.<<ETX>>","PeriodicalId":245997,"journal":{"name":"Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-09-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125612689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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