Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158084
Shi-Hao Chen, Jiing-Yuan Lin
Reducing the power supply voltage is an effective technique to reduce dynamic power. Power shut-off (PSO) is also a well-known approach to reduce leakage power. In practice, one may employ multi-supply voltage or dynamic voltage and frequency scaling (DVFS) techniques accompanied with power gating and multi-depth sleep modes to reduce both of dynamic and leakage power consumption. As the voltage domains (power domains) and sleep modes (power modes) are increased dramatically, it is difficult to plan interface logics such as level shifters and isolation cells completely by manual for each power domain. In this paper, we present an interface planning methodology, and take a DVFS and power gating design with over 50 power domains and 80 power modes to demonstrate the verification challenges and our solutions. Besides, we propose a “seamless” interface control circuit for PSO and DVFS designs. By using the circuit, the designs in the power on domain don't feel any data change when the opposite power domain is powered off.
{"title":"Implementation and verification practices of DVFS and power gating","authors":"Shi-Hao Chen, Jiing-Yuan Lin","doi":"10.1109/VDAT.2009.5158084","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158084","url":null,"abstract":"Reducing the power supply voltage is an effective technique to reduce dynamic power. Power shut-off (PSO) is also a well-known approach to reduce leakage power. In practice, one may employ multi-supply voltage or dynamic voltage and frequency scaling (DVFS) techniques accompanied with power gating and multi-depth sleep modes to reduce both of dynamic and leakage power consumption. As the voltage domains (power domains) and sleep modes (power modes) are increased dramatically, it is difficult to plan interface logics such as level shifters and isolation cells completely by manual for each power domain. In this paper, we present an interface planning methodology, and take a DVFS and power gating design with over 50 power domains and 80 power modes to demonstrate the verification challenges and our solutions. Besides, we propose a “seamless” interface control circuit for PSO and DVFS designs. By using the circuit, the designs in the power on domain don't feel any data change when the opposite power domain is powered off.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129375852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158102
Yo‐Sheng Lin, Tien-Hung Chang, Chang‐Zhi Chen, Chi-Chen Chen, H. Yang, S. Wong
A low-power low-phase-noise 48-GHz CMOS LC voltage-control oscillator (VCO) and a low-power 60-GHz CMOS low-noise amplifier (LNA) for 60-GHz dual-conversion receiver are reported. The VCO dissipated 5.556 mW power, and achieved state-of-the-art phase noise of −105 dBc/Hz at 1-MHz offset from 47.84 GHz. The corresponding figure-of-merit (FOM) was −191.1 dBc/Hz, which is better than those of the reported CMOS LC VCOs around 48 GHz in the literature. Besides, the LNA consumed 21.4 mW power, and achieved input return loss (S11) of −10.6∼ −37.4 dB, voltage gain (AV) of 10.7∼ 18.8 dB, reverse isolation (S12) of −43.5∼ −48.1 dB, input referred 1-dB compression point (P1dB-in) of −16.2∼ −20.8 dBm, and input third-order inter-modulation point (IIP3) of −4∼ −7.5 dBm over the 57-64-GHz-band of interest.
{"title":"Low-power 48-GHz CMOS VCO and 60-GHz CMOS LNA for 60-GHz dual-conversion receiver","authors":"Yo‐Sheng Lin, Tien-Hung Chang, Chang‐Zhi Chen, Chi-Chen Chen, H. Yang, S. Wong","doi":"10.1109/VDAT.2009.5158102","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158102","url":null,"abstract":"A low-power low-phase-noise 48-GHz CMOS LC voltage-control oscillator (VCO) and a low-power 60-GHz CMOS low-noise amplifier (LNA) for 60-GHz dual-conversion receiver are reported. The VCO dissipated 5.556 mW power, and achieved state-of-the-art phase noise of −105 dBc/Hz at 1-MHz offset from 47.84 GHz. The corresponding figure-of-merit (FOM) was −191.1 dBc/Hz, which is better than those of the reported CMOS LC VCOs around 48 GHz in the literature. Besides, the LNA consumed 21.4 mW power, and achieved input return loss (S<inf>11</inf>) of −10.6∼ −37.4 dB, voltage gain (A<inf>V</inf>) of 10.7∼ 18.8 dB, reverse isolation (S<inf>12</inf>) of −43.5∼ −48.1 dB, input referred 1-dB compression point (P<inf>1dB-in</inf>) of −16.2∼ −20.8 dBm, and input third-order inter-modulation point (IIP3) of −4∼ −7.5 dBm over the 57-64-GHz-band of interest.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115893973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158081
J. Rabaey
The continuous reduction of size, and cost of wireless transceivers pretty soon will allow for every appliance, component or object to be networked (“The Internet of Things”). However, a substantial reduction in power dissipation by one or two orders of magnitude is still necessary. In this presentation, we identify the opportunities and challenges offered by technology evolution. While CMOS scaling offers some advantages, it also comes with additional burdens such as leakage and variability. Even more, energy per operation may not reduce very much once we reach the 32 nm node. Fortunately, other emerging devices such as RF-NEMS resonators or other elements emerging from the vast cauldron of nanotechnology may create new opportunities. We will show some example of ULP wireless transceivers created through a combination of aggressive technology utilization, use of novel technologies and innovative architectures. We believe that this combination is what it takes to continue the promise of electronics scaling.
{"title":"Microscopic wireless - Exploring the boundaries of ultra low-power design","authors":"J. Rabaey","doi":"10.1109/VDAT.2009.5158081","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158081","url":null,"abstract":"The continuous reduction of size, and cost of wireless transceivers pretty soon will allow for every appliance, component or object to be networked (“The Internet of Things”). However, a substantial reduction in power dissipation by one or two orders of magnitude is still necessary. In this presentation, we identify the opportunities and challenges offered by technology evolution. While CMOS scaling offers some advantages, it also comes with additional burdens such as leakage and variability. Even more, energy per operation may not reduce very much once we reach the 32 nm node. Fortunately, other emerging devices such as RF-NEMS resonators or other elements emerging from the vast cauldron of nanotechnology may create new opportunities. We will show some example of ULP wireless transceivers created through a combination of aggressive technology utilization, use of novel technologies and innovative architectures. We believe that this combination is what it takes to continue the promise of electronics scaling.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114479919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158158
K. Liang, Luis Chen, C. Yue
This paper presents a low-power and high-speed super-regenerative receiver operating at the 60-GHz using 65-nm CMOS technology. The receiver uses the simplicity and power efficiency architecture for short-range communication. The proposed receiver achieves a data rate of 200 Mb/s with current consumption of 10 mA at a supply voltage of 1 V. The corresponding energy consumption of 50 pJ per receiver bit was an excellent tradeoff between cost, performance and power consumption.
{"title":"A 200-Mb/s 10-mW super-regenerative receiver at 60 GHz","authors":"K. Liang, Luis Chen, C. Yue","doi":"10.1109/VDAT.2009.5158158","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158158","url":null,"abstract":"This paper presents a low-power and high-speed super-regenerative receiver operating at the 60-GHz using 65-nm CMOS technology. The receiver uses the simplicity and power efficiency architecture for short-range communication. The proposed receiver achieves a data rate of 200 Mb/s with current consumption of 10 mA at a supply voltage of 1 V. The corresponding energy consumption of 50 pJ per receiver bit was an excellent tradeoff between cost, performance and power consumption.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126606620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158168
S. Shibata, S. Honda, H. Tomiyama, H. Takada
This paper presents a case study on designing an MPEG4 decoder system using our system-level design toolkit named SystemBuilder. We start with a sequential specification of the MPEG4 decoder behavior and generate an FPGA implementation. In order to improve the performance, we refine the behavioral description based on the analysis result obtained by a profiler. Finally, we achieve over 15fps performance with pipelined hardware implementation.
{"title":"A case study on MPEG4 decoder design with SystemBuilder","authors":"S. Shibata, S. Honda, H. Tomiyama, H. Takada","doi":"10.1109/VDAT.2009.5158168","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158168","url":null,"abstract":"This paper presents a case study on designing an MPEG4 decoder system using our system-level design toolkit named SystemBuilder. We start with a sequential specification of the MPEG4 decoder behavior and generate an FPGA implementation. In order to improve the performance, we refine the behavioral description based on the analysis result obtained by a profiler. Finally, we achieve over 15fps performance with pipelined hardware implementation.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123787684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158162
Charlie Hsiao, Chi-Yun Chen, T. Chiueh
A dual mode 2×2 MIMO OFDM & OFDMA receiver is implemented with shared hardware resources. This dual mode receiver functions well in both static and mobile channels. It follows the specification requirement of EWC HT PHY V1.27 and IEEE 802.16e-2005, and proposes a PHY baseband simulation model to meet the specifications. Additionally, equalization supports both static and dynamic channel estimation. 2×2 MIMO STBC and V-BLAST are supported as well. A low cost ICI (inter-carrier interference) cancellation hardware is also proposed.
采用共享硬件资源实现了一种双模2×2 MIMO OFDM & OFDMA接收机。这种双模接收机在静态和移动信道中都能很好地工作。遵循EWC HT PHY V1.27和IEEE 802.16e-2005的规范要求，提出了满足规范要求的PHY基带仿真模型。此外，均衡支持静态和动态信道估计。2×2也支持MIMO STBC和V-BLAST。提出了一种低成本的载波间干扰消除硬件。
{"title":"Design of a dual-mode baseband receiver for 802.11n and 802.16e MIMO OFDM/OFDMA","authors":"Charlie Hsiao, Chi-Yun Chen, T. Chiueh","doi":"10.1109/VDAT.2009.5158162","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158162","url":null,"abstract":"A dual mode 2×2 MIMO OFDM & OFDMA receiver is implemented with shared hardware resources. This dual mode receiver functions well in both static and mobile channels. It follows the specification requirement of EWC HT PHY V1.27 and IEEE 802.16e-2005, and proposes a PHY baseband simulation model to meet the specifications. Additionally, equalization supports both static and dynamic channel estimation. 2×2 MIMO STBC and V-BLAST are supported as well. A low cost ICI (inter-carrier interference) cancellation hardware is also proposed.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122769905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158159
Zhen Chen, D. Xiang, Boxue Yin
Many X-Filling strategies are proposed to reduce test power during scan based testing. Because their main motivation is to reduce the switching activities of test patterns in the test process, some of them are prone to reduce the test ability of test patterns, which may lead to low defect coverage. In this paper, we propose a segment based X-filling(SBF) technique to reduce test power using multiple scan chains, with minimal impact on defect coverage. Different from the previous filling methods, our X-filling technique is segment based and defect coverage aware. The method can be easily incorporated into traditional ATPG flow to keep capture power below a certain limit and keep the defect coverage at a high level.
{"title":"Segment based X-Filling for low power and high defect coverage","authors":"Zhen Chen, D. Xiang, Boxue Yin","doi":"10.1109/VDAT.2009.5158159","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158159","url":null,"abstract":"Many X-Filling strategies are proposed to reduce test power during scan based testing. Because their main motivation is to reduce the switching activities of test patterns in the test process, some of them are prone to reduce the test ability of test patterns, which may lead to low defect coverage. In this paper, we propose a segment based X-filling(SBF) technique to reduce test power using multiple scan chains, with minimal impact on defect coverage. Different from the previous filling methods, our X-filling technique is segment based and defect coverage aware. The method can be easily incorporated into traditional ATPG flow to keep capture power below a certain limit and keep the defect coverage at a high level.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129862008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158136
I-Wei Tseng, Jen-Ming Wu
This paper presents a 10-GHz phase-locked loop (PLL) design with low power for high speed networking. A mixed design of Current Mode Logic (CML) and True Single Phase Clock (TSPC) logic is presented to reduce the power consumption of the frequency divider. With gain-boosting design in the charge pump leads to low jitter and low reference spur. An additional diversity of VCO by user body bias is proposed to improve KVCO. The PLL circuit is fabricated in TSMC 0.13µm RF CMOS process. The chip occupies 1.03 × 0.91 mm2, draws less than 18.7mW from a 1.2V supply, and is −117.43dBc/Hz at an offset frequency of 1MHz from the carrier.
{"title":"An 18.7mW 10-GHz Phase-Locked Loop Circuit in 0.13-µm CMOS","authors":"I-Wei Tseng, Jen-Ming Wu","doi":"10.1109/VDAT.2009.5158136","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158136","url":null,"abstract":"This paper presents a 10-GHz phase-locked loop (PLL) design with low power for high speed networking. A mixed design of Current Mode Logic (CML) and True Single Phase Clock (TSPC) logic is presented to reduce the power consumption of the frequency divider. With gain-boosting design in the charge pump leads to low jitter and low reference spur. An additional diversity of VCO by user body bias is proposed to improve KVCO. The PLL circuit is fabricated in TSMC 0.13µm RF CMOS process. The chip occupies 1.03 × 0.91 mm2, draws less than 18.7mW from a 1.2V supply, and is −117.43dBc/Hz at an offset frequency of 1MHz from the carrier.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128898504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158129
Y. Lu, Ming-Der Shieh, W. Kuo
A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n ≤ 255 with ν errors and ρ erasures correcting capability, 0≤ 2ν+ρ ≤ 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13µm 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.
{"title":"Design of high-speed errors-and-erasures Reed-Solomon decoders for multi-mode applications","authors":"Y. Lu, Ming-Der Shieh, W. Kuo","doi":"10.1109/VDAT.2009.5158129","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158129","url":null,"abstract":"A multi-mode Reed-Solomon (RS) decoder design based on the reformulated inversionless Berlekamp-Massey (riBM) algorithm is proposed to correct both errors and erasures for any RS code including shortened codes. Without degrading the resulting performance, we effectively improve the hardware utilization of decoder and simplify the routing network in conventional multi-mode decoder design. With the developed multi-mode arrangement, the proposed decoder possesses not only high-performance property but also simple and regular interconnect topology, making the decoder suitable for VLSI realization. Experimental results reveal that for code words of length n ≤ 255 with ν errors and ρ erasures correcting capability, 0≤ 2ν+ρ ≤ 16, the achievable throughput rate of the proposed decoder, implemented in TSMC 0.13µm 1P8M process, is 4Gbps at a maximum operating clock of 450MHz and the total gate count is 50K.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130888299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-µm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.
本文报道了一种用于低功耗低成本CMOS集成系统的6位220 ms /s时间交错逐次逼近寄存器模数转换器(SAR ADC)。设计的主要概念是基于在DAC电容阵列中提出的设置和关闭电容开关方法。与传统的开关方式相比，平均开关能量降低约81%。在220-MS/s采样速率下，测得的SNDR和SFDR分别为32.62 dB和48.96 dB。所得ENOB为5.13位。总功耗为6.8 mW。采用台积电0.18-µm 1P5M数字CMOS技术制造，ADC的有效面积仅为0.032 mm2。
{"title":"A 6-bit 220-MS/s time-interleaving SAR ADC in 0.18-µm digital CMOS process","authors":"Chun-Cheng Liu, Yi-Ting Huang, Guan-Ying Huang, Soon-Jyh Chang, Chung-Ming Huang, Chih-Haur Huang","doi":"10.1109/VDAT.2009.5158133","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158133","url":null,"abstract":"This paper reports a 6-bit 220-MS/s time-interleaving successive approximation register analog-to-digital converter (SAR ADC) for low-power low-cost CMOS integrated systems. The major concept of the design is based on the proposed set-and-down capacitor switching method in the DAC capacitor array. Compared to the conventional switching method, the average switching energy is reduced about 81%. At 220-MS/s sampling rate, the measured SNDR and SFDR are 32.62 dB and 48.96 dB respectively. The resultant ENOB is 5.13 bits. The total power consumption is 6.8 mW. Fabricated in TSMC 0.18-µm 1P5M Digital CMOS technology, the ADC only occupies 0.032 mm2 active area.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132922101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：