Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158101
L. Aspemyr, H. Sjoland, Denis Berthiot, J. Proot
To demonstrate the capability of the System-on-Package concept for microwave design a 19 GHz low-power, low-noise amplifier in 0.13 µm CMOS is manufactured. A CMOS chip is flip-chip mounted on a glass carrier with integrated passive components. The LNA has a power gain of 7 dB, a 3.8 dB noise figure, and a IP1dB of −5.8 dBm at 19.2 GHz. The LNA consumes 5 mA from a 1.2 V supply.
{"title":"Glass carrier SOP technology demonstrated by design of a 19 GHz 3.8 dB CMOS LNA","authors":"L. Aspemyr, H. Sjoland, Denis Berthiot, J. Proot","doi":"10.1109/VDAT.2009.5158101","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158101","url":null,"abstract":"To demonstrate the capability of the System-on-Package concept for microwave design a 19 GHz low-power, low-noise amplifier in 0.13 µm CMOS is manufactured. A CMOS chip is flip-chip mounted on a glass carrier with integrated passive components. The LNA has a power gain of 7 dB, a 3.8 dB noise figure, and a IP1dB of −5.8 dBm at 19.2 GHz. The LNA consumes 5 mA from a 1.2 V supply.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116278455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158169
Chen-Chieh Wang, Ro-Pun Wong, Jing-Wun Lin, C. Chen
In this paper, we propose a framework to develop high-performance system accelerator at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication support that enables full system simulation. We have also developed a network virtual interface for our system to co-work with the real world network environment. Finally, the MD5 algorithm offload and the network offload engine are used as examples to demonstrate the proposed framework system for full system simulation.
{"title":"System-level development and verification framework for high-performance system accelerator","authors":"Chen-Chieh Wang, Ro-Pun Wong, Jing-Wun Lin, C. Chen","doi":"10.1109/VDAT.2009.5158169","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158169","url":null,"abstract":"In this paper, we propose a framework to develop high-performance system accelerator at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication support that enables full system simulation. We have also developed a network virtual interface for our system to co-work with the real world network environment. Finally, the MD5 algorithm offload and the network offload engine are used as examples to demonstrate the proposed framework system for full system simulation.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129538362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158110
Yu-Lun Co, Hung-Ming Chen, Yi-Kan Cheng
With feature sizes on chips shrinking at advanced process nodes, the difficulty in manufacturability and reliability of chips is extremely increasing. It has necessitated better planarization of chip surface topography to improve both functional and parametric yields. The common solution to minimize topography variation is to perform metal fills in empty spaces in the layout. However, these dummy metals will increase the capacitances between wires and then invoke delay and coupling/ crosstalk noise problems. Furthermore, the impact of ECP (electroplating) should be included in the copper CMP model in order to have accurate metal fill results. In this paper, we adopt and implement an approach to considering especially the key layout parameters that affect the post-ECP topography. We further apply a greedy-based method to place the floating dummy metals in the positions with minimal additional coupling capacitances. The experimental results are encouraging. Our method not only considers the thickness range of post-ECP, it can also add much less additional coupling capacitances over a density-driven metal fill method.
{"title":"Coupling- and ECP-aware metal fill for improving layout uniformity in copper CMP","authors":"Yu-Lun Co, Hung-Ming Chen, Yi-Kan Cheng","doi":"10.1109/VDAT.2009.5158110","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158110","url":null,"abstract":"With feature sizes on chips shrinking at advanced process nodes, the difficulty in manufacturability and reliability of chips is extremely increasing. It has necessitated better planarization of chip surface topography to improve both functional and parametric yields. The common solution to minimize topography variation is to perform metal fills in empty spaces in the layout. However, these dummy metals will increase the capacitances between wires and then invoke delay and coupling/ crosstalk noise problems. Furthermore, the impact of ECP (electroplating) should be included in the copper CMP model in order to have accurate metal fill results. In this paper, we adopt and implement an approach to considering especially the key layout parameters that affect the post-ECP topography. We further apply a greedy-based method to place the floating dummy metals in the positions with minimal additional coupling capacitances. The experimental results are encouraging. Our method not only considers the thickness range of post-ECP, it can also add much less additional coupling capacitances over a density-driven metal fill method.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130583148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a transistor-level automation to perform component sizing, power optimization and layout generation for fully-differential operational amplifiers (op-amps). The design variables of the component sizing are bias voltages and bias currents. The free space of the variables is easy to be restricted by circuit constraints. A lookup-table-based scheme is presented to translate the variables into transistor dimensions without much preparing effort. The layout generation employs analog layout skills, such as device matching, dummy cell and guard ring, to have good quality.
{"title":"A bias-driven approach for automated design of operational amplifiers","authors":"Cheng-Wu Lin, Pin-Dai Sue, Ya-Ting Shyu, Soon-Jyh Chang","doi":"10.1109/VDAT.2009.5158109","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158109","url":null,"abstract":"This paper presents a transistor-level automation to perform component sizing, power optimization and layout generation for fully-differential operational amplifiers (op-amps). The design variables of the component sizing are bias voltages and bias currents. The free space of the variables is easy to be restricted by circuit constraints. A lookup-table-based scheme is presented to translate the variables into transistor dimensions without much preparing effort. The layout generation employs analog layout skills, such as device matching, dummy cell and guard ring, to have good quality.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158161
Shih-Hung Chen, M. Ker
A power-rail ESD clamp circuit with a new proposed ESD-transient detection circuit which adopts a ultra small capacitor to achieve the required functions has been presented and substantiated to own a long turn-on duration and high turn-on efficiency. In addition, the power-rail ESD clamp circuits with the new proposed ESD-transient detection circuit also presented an excellent immunity against the mis-trigger and the latch-on event under the fast power-on condition.
{"title":"Design of on-chip power-rail ESD clamp circuit with ultra-small capacitance to detect ESD transition","authors":"Shih-Hung Chen, M. Ker","doi":"10.1109/VDAT.2009.5158161","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158161","url":null,"abstract":"A power-rail ESD clamp circuit with a new proposed ESD-transient detection circuit which adopts a ultra small capacitor to achieve the required functions has been presented and substantiated to own a long turn-on duration and high turn-on efficiency. In addition, the power-rail ESD clamp circuits with the new proposed ESD-transient detection circuit also presented an excellent immunity against the mis-trigger and the latch-on event under the fast power-on condition.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116872511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158082
T. Iizuka
In the past over two decades, the horizontal cooperation in addition to the vertically integrated model played an important role in driving semiconductor industry growth. Especially in the last decade, the co-work among the EDA tool providers, equipment manufacturers, foundries, test houses and fabless chip providers proved to be powerful alternative to integrated model in supporting diversifying demands of system product solutions. However, as the industry approaches to maturing stage, the cost distribution among the horizontal value chain is changing so that it may hurt the possibility of emerging new players and may weaken the industry dynamism. To enhance the healthier growth in the next decade of the semiconductor industry, as an indispensable value creator for the whole industry and human welfare, the collaboration among the value chain must be developed. In this talk, trends of the value generation and cost sharing structure will be reviewed, and deeper mutual collaboration scheme for the industry prosperity will be discussed.
{"title":"Semiconductor industry prosperity trough deeper horizontal collaborations","authors":"T. Iizuka","doi":"10.1109/VDAT.2009.5158082","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158082","url":null,"abstract":"In the past over two decades, the horizontal cooperation in addition to the vertically integrated model played an important role in driving semiconductor industry growth. Especially in the last decade, the co-work among the EDA tool providers, equipment manufacturers, foundries, test houses and fabless chip providers proved to be powerful alternative to integrated model in supporting diversifying demands of system product solutions. However, as the industry approaches to maturing stage, the cost distribution among the horizontal value chain is changing so that it may hurt the possibility of emerging new players and may weaken the industry dynamism. To enhance the healthier growth in the next decade of the semiconductor industry, as an indispensable value creator for the whole industry and human welfare, the collaboration among the value chain must be developed. In this talk, trends of the value generation and cost sharing structure will be reviewed, and deeper mutual collaboration scheme for the industry prosperity will be discussed.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116082352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158139
Yi-Chan Li, Hisu-Hsien Li, Han-Lin Li, Chia-Lin Yang
As personal multimedia devices become mainstream consumer products, an energy-aware on-demand video streaming system for portable devices is critical. A critical component of an energy-aware video streaming system is an accurate energy prediction scheme for video decoding. In this paper, we propose the first content-aware energy predictor for video playback. We correlate video attributes with decoding energy through linear regression. The average prediction error achieved by proposed content-aware energy prediction scheme is only 1.88%.
{"title":"Content-aware energy prediction for video streaming in mobile devices","authors":"Yi-Chan Li, Hisu-Hsien Li, Han-Lin Li, Chia-Lin Yang","doi":"10.1109/VDAT.2009.5158139","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158139","url":null,"abstract":"As personal multimedia devices become mainstream consumer products, an energy-aware on-demand video streaming system for portable devices is critical. A critical component of an energy-aware video streaming system is an accurate energy prediction scheme for video decoding. In this paper, we propose the first content-aware energy predictor for video playback. We correlate video attributes with decoding energy through linear regression. The average prediction error achieved by proposed content-aware energy prediction scheme is only 1.88%.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121674880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158156
Changhui Hu, S. Redfield, Huaping Liu, R. Khanna, J. Nejedlo, P. Chiang
This paper presents a novel CMOS 2-tap equalizer for combating multipath interference in impulse radio, ultra-wideband (IR-UWB) transceiver systems. The equalizer is composed of pulse width control, pulse tap delay control, pulse sign inversion, and current mode logic (CML) summation for data transmission. SpectreRF post-layout simulation in a 90-nm CMOS technology shows that the transceiver operates up to a 2Gbps data rate by removing the 1st and 2nd multipath reflections, illustrating significant signal-to-noise (SNR) improvement when compared with a conventional transmitter.
{"title":"Transmitter equalization for multipath interference cancellation in impulse radio ultra-wideband(IR-UWB) transceivers","authors":"Changhui Hu, S. Redfield, Huaping Liu, R. Khanna, J. Nejedlo, P. Chiang","doi":"10.1109/VDAT.2009.5158156","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158156","url":null,"abstract":"This paper presents a novel CMOS 2-tap equalizer for combating multipath interference in impulse radio, ultra-wideband (IR-UWB) transceiver systems. The equalizer is composed of pulse width control, pulse tap delay control, pulse sign inversion, and current mode logic (CML) summation for data transmission. SpectreRF post-layout simulation in a 90-nm CMOS technology shows that the transceiver operates up to a 2Gbps data rate by removing the 1st and 2nd multipath reflections, illustrating significant signal-to-noise (SNR) improvement when compared with a conventional transmitter.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133965559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158141
Wenjie. Yang, Wen-Hung Hsieh, C. Hung
This paper presents the design of a third-order continuous-time (CT) single-bit active-RC sigma-delta (ΣΔ) modulator for Bluetooth application. Through the use of the architecture, cascade of resonators with distributed feedback (CRFB), the signal bandwidth can be improved without increasing the order of the modulator. All integrators are implemented by active-RC type to have better linearity. Furthermore, in order to reduce the effect of the clock jitter, the feedback digital-to-analog converter (DAC) shape is realized by non-return-to-zero (NRZ). The modulator is designed in a standard digital 0.18µm CMOS process with a chip area of 1.32×1.23 mm2. The measurement results show that the modulator achieves 56.8dB SNDR and 60dB dynamic range over 1MHz signal bandwidth, consuming 22.2mW at 1.8V supply.
本文介绍了一种用于蓝牙应用的三阶连续时间(CT)单比特有源rc sigma-delta (ΣΔ)调制器的设计。通过采用分布反馈(CRFB)谐振器级联的结构，可以在不增加调制器阶数的情况下提高信号带宽。所有积分器均采用主动rc型实现，具有较好的线性度。此外，为了减小时钟抖动的影响，采用不归零(NRZ)实现了反馈数模转换器(DAC)的形状。该调制器采用标准数字0.18 μ m CMOS工艺设计，芯片面积为1.32×1.23 mm2。测量结果表明，在1MHz信号带宽下，该调制器实现了56.8dB的SNDR和60dB的动态范围，在1.8V电源下功耗为22.2mW。
{"title":"A third-order continuous-time sigma-delta modulator for Bluetooth","authors":"Wenjie. Yang, Wen-Hung Hsieh, C. Hung","doi":"10.1109/VDAT.2009.5158141","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158141","url":null,"abstract":"This paper presents the design of a third-order continuous-time (CT) single-bit active-RC sigma-delta (ΣΔ) modulator for Bluetooth application. Through the use of the architecture, cascade of resonators with distributed feedback (CRFB), the signal bandwidth can be improved without increasing the order of the modulator. All integrators are implemented by active-RC type to have better linearity. Furthermore, in order to reduce the effect of the clock jitter, the feedback digital-to-analog converter (DAC) shape is realized by non-return-to-zero (NRZ). The modulator is designed in a standard digital 0.18µm CMOS process with a chip area of 1.32×1.23 mm2. The measurement results show that the modulator achieves 56.8dB SNDR and 60dB dynamic range over 1MHz signal bandwidth, consuming 22.2mW at 1.8V supply.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"291 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129255257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158092
S. Heng, Weichun Tung, C. Pham
In this paper, a low power current protection circuit implemented in LDOs is presented. The proposed circuit, designed in 0.35µm CMOS process, provides a precise limiting current as well as holding current with low dependency on both supply voltage and regulator output voltage. The experimental results showed the proposed circuit is operable in the regulator output voltage range V OUT = 1.2V to V OUT = 3.6V and supply voltage range V DD = V OUT + 0.5V to V DD = 5.6V . Since the proposed circuit is composed of few simple basic circuits such as comparator, Schmitt Trigger, it has a low current consumption which is less than ISS = 0.82µA at load current ILOAD = 200mA. This makes the circuit suitable for low power and low voltage LDO design.
本文提出了一种低功耗电流保护电路。该电路采用0.35µm CMOS工艺设计，可提供精确的限制电流以及对电源电压和稳压器输出电压依赖性较低的保持电流。实验结果表明，该电路可在稳压器输出电压V OUT = 1.2V ~ V OUT = 3.6V和电源电压V DD = V OUT + 0.5V ~ V DD = 5.6V范围内工作。由于所提出的电路由比较器、施密特触发器等几个简单的基本电路组成，因此在负载电流ILOAD = 200mA时，其电流消耗低于ISS = 0.82µa。这使得该电路适用于低功耗、低电压的LDO设计。
{"title":"New design method of low power over current protection circuit for low dropout regulator","authors":"S. Heng, Weichun Tung, C. Pham","doi":"10.1109/VDAT.2009.5158092","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158092","url":null,"abstract":"In this paper, a low power current protection circuit implemented in LDOs is presented. The proposed circuit, designed in 0.35µm CMOS process, provides a precise limiting current as well as holding current with low dependency on both supply voltage and regulator output voltage. The experimental results showed the proposed circuit is operable in the regulator output voltage range V OUT = 1.2V to V OUT = 3.6V and supply voltage range V DD = V OUT + 0.5V to V DD = 5.6V . Since the proposed circuit is composed of few simple basic circuits such as comparator, Schmitt Trigger, it has a low current consumption which is less than ISS = 0.82µA at load current ILOAD = 200mA. This makes the circuit suitable for low power and low voltage LDO design.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131913685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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