Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158132
Yu-Chang Lien, Ying-Zu Lin, Soon-Jyh Chang
This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13µm CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.
{"title":"A 6-bit 1GS/s low-power flash ADC","authors":"Yu-Chang Lien, Ying-Zu Lin, Soon-Jyh Chang","doi":"10.1109/VDAT.2009.5158132","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158132","url":null,"abstract":"This paper proposes a low-power design guideline for high speed ADCs, and a low-power ADC with this design guideline is fabricated in a 0.13µm CMOS process. The experimental results show that the effective number of bit (ENOB) is 5.16 at the sampling frequency of 1 GHz, and the resolution bandwidth (ERBW) is higher than 500 MHz at 700MS/s. Due to the high input bandwidth and low power consumption, this ADC is very suitable for UWB systems.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122614229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158096
S. Kajihara, Shinji Oku, K. Miyase, X. Wen, Yasuo Sato
This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns with Xs. Because the detectable delay size of each fault by a test cube is fixed after assigning logic values to the Xs in the test cube, the proposed method computes a range of the delay values of the test patterns covered by the test cube. By using the proposed method, we can derive the lowest test quality and the highest test quality of test patterns covered by the test cube.
{"title":"On calculation of delay range in fault simulation for test cubes","authors":"S. Kajihara, Shinji Oku, K. Miyase, X. Wen, Yasuo Sato","doi":"10.1109/VDAT.2009.5158096","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158096","url":null,"abstract":"This paper proposes a method to compute delay values in 3-valued fault simulation for test cubes which are test patterns with Xs. Because the detectable delay size of each fault by a test cube is fixed after assigning logic values to the Xs in the test cube, the proposed method computes a range of the delay values of the test patterns covered by the test cube. By using the proposed method, we can derive the lowest test quality and the highest test quality of test patterns covered by the test cube.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128616681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158085
Gi-Joon Nam, D. Papa, Michael D. Moffitt, C. Alpert
In high-frequency microprocessor design, placement plays a significantly different role from that in large ASICs. Not only does it have to find a good global placement solution, placement needs tighter interaction with physical optimizations to improve every picosecond possible. This paper will introduce practical placement techniques that integrate buffering and gate sizing to maximize timing improvement in a standard-cell library based high-performance design flow. Combined with accurate timing models and analysis, these incremental placement techniques simultaneously consider multiple optimization options and make timing-optimal changes under the given timing model. These techniques are equipped with a “Do-no-harm” policy that makes them applicable in incremental optimization frameworks to reform critical subcircuits.
{"title":"Toward the integration of incremental physical synthesis optimizations","authors":"Gi-Joon Nam, D. Papa, Michael D. Moffitt, C. Alpert","doi":"10.1109/VDAT.2009.5158085","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158085","url":null,"abstract":"In high-frequency microprocessor design, placement plays a significantly different role from that in large ASICs. Not only does it have to find a good global placement solution, placement needs tighter interaction with physical optimizations to improve every picosecond possible. This paper will introduce practical placement techniques that integrate buffering and gate sizing to maximize timing improvement in a standard-cell library based high-performance design flow. Combined with accurate timing models and analysis, these incremental placement techniques simultaneously consider multiple optimization options and make timing-optimal changes under the given timing model. These techniques are equipped with a “Do-no-harm” policy that makes them applicable in incremental optimization frameworks to reform critical subcircuits.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126423716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158122
Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma
As fabrication technology progresses, several new challenges follow. Among them, the most noticeable two are process variations and leakage current of the circuit. To tackle these two problems, an effective way is to use body biasing technique. In substance, using RBB technique can minimize leakage current but increase the delay of a gate. FBB technique decreases the delay but increases leakage current. In previous works, a single body biasing is applied to whole circuit. In a slow circuit, since the FBB is applied to whole circuit, the leakage current increases dramatically. In a fast circuit, RBB is applied to decrease the leakage current. However, without violating the timing specification, the value of body biasing is restricted by the critical paths, and the saving of leakage current is limited. In this paper, we propose a design flow to partition the circuit into subcircuits so that each subcircuit can be applied its individual RBB or FBB to reduce the leakage current and cope with process variations. In the experimental result, our method is able to save leakage current from 41% to 46% as compared with design without body biasing technique. Under process variations, our method can save 40% to 49% leakage on fast circuits and 15% to 32% on slow circuits.
{"title":"Leakage reduction, variation compensation using partition-based tunable body-biasing techniques","authors":"Po-Yuan Chen, Chiao-Chen Fang, TingTing Hwang, Hsi-Pin Ma","doi":"10.1109/VDAT.2009.5158122","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158122","url":null,"abstract":"As fabrication technology progresses, several new challenges follow. Among them, the most noticeable two are process variations and leakage current of the circuit. To tackle these two problems, an effective way is to use body biasing technique. In substance, using RBB technique can minimize leakage current but increase the delay of a gate. FBB technique decreases the delay but increases leakage current. In previous works, a single body biasing is applied to whole circuit. In a slow circuit, since the FBB is applied to whole circuit, the leakage current increases dramatically. In a fast circuit, RBB is applied to decrease the leakage current. However, without violating the timing specification, the value of body biasing is restricted by the critical paths, and the saving of leakage current is limited. In this paper, we propose a design flow to partition the circuit into subcircuits so that each subcircuit can be applied its individual RBB or FBB to reduce the leakage current and cope with process variations. In the experimental result, our method is able to save leakage current from 41% to 46% as compared with design without body biasing technique. Under process variations, our method can save 40% to 49% leakage on fast circuits and 15% to 32% on slow circuits.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121600904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158125
B. Vermeulen, K. Goossens
Problems in a new System on Chip (SOC) consisting of hardware and embedded software often only show up when a silicon prototype of the chip is placed in its intended target environment and the application is executed. Traditionally, the debugging of embedded systems is difficult and time consuming because of the intrinsic lack of internal system observability and controlability in the target environment. Design for Debug (DfD) is the act of adding debug support to the design of a chip, in the realization that not every SOC is correct first time. DfD provides debug engineers with increased observability and controlability of the internal operation of an embedded system. In this paper, we present a monitoring infrastructure for multi-processor SOCs with a Network on Chip (NOC), and explain its application to performance analysis and debug. We describe how our monitors aid in the performance analysis and debug of the interactions of the embedded processors. We present a generic template for bus and router monitors, and show how they are instantiated at design time in our NOC design flow. We conclude this paper with details of their hardware cost.
{"title":"A Network-on-Chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs","authors":"B. Vermeulen, K. Goossens","doi":"10.1109/VDAT.2009.5158125","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158125","url":null,"abstract":"Problems in a new System on Chip (SOC) consisting of hardware and embedded software often only show up when a silicon prototype of the chip is placed in its intended target environment and the application is executed. Traditionally, the debugging of embedded systems is difficult and time consuming because of the intrinsic lack of internal system observability and controlability in the target environment. Design for Debug (DfD) is the act of adding debug support to the design of a chip, in the realization that not every SOC is correct first time. DfD provides debug engineers with increased observability and controlability of the internal operation of an embedded system. In this paper, we present a monitoring infrastructure for multi-processor SOCs with a Network on Chip (NOC), and explain its application to performance analysis and debug. We describe how our monitors aid in the performance analysis and debug of the interactions of the embedded processors. We present a generic template for bus and router monitors, and show how they are instantiated at design time in our NOC design flow. We conclude this paper with details of their hardware cost.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114188080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a circuit-level synthesis tool for pipelined ADCs by consulting the circuit-design experience. A top-down systematic design procedure for a conventional pipelined ADC is summarized. In order to decrease the design period for analog circuit sizing, a design automation methodology based on gm/ID concept is manipulated in the synthesis process. With the proposed design automation flow for pipelined ADCs, the developed synthesis tool can produce satisfactory circuit performance within reasonable simulation time.
{"title":"A gm/ID-based synthesis tool for pipelined analog to digital converters","authors":"Ya-Ting Shyu, Cheng-Wu Lin, Jin-Fu Lin, Soon-Jyh Chang","doi":"10.1109/VDAT.2009.5158154","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158154","url":null,"abstract":"This paper presents a circuit-level synthesis tool for pipelined ADCs by consulting the circuit-design experience. A top-down systematic design procedure for a conventional pipelined ADC is summarized. In order to decrease the design period for analog circuit sizing, a design automation methodology based on gm/ID concept is manipulated in the synthesis process. With the proposed design automation flow for pipelined ADCs, the developed synthesis tool can produce satisfactory circuit performance within reasonable simulation time.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114433936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158088
J. Cunningham, A. Krishnamoorthy, Xuezhe Zheng, Guoliang Li, R. Ho, J. Lexau, I. Shubin, K. Raj
There have been a number of recent high-profile advances in silicon-integrated optical devices, including low-loss silicon waveguides, integrated laser modulators and photodetectors, optical gratings for surface-normal attach of fibers to chips, and many more. These technologies open the possibility of using silicon-based nano-photonics inside a traditional computer system based on very large scale integration (VLSI) chips using todays most advanced complementary metal-oxide-silicon (CMOS) technologies. Such a system might offer the cost and computing performance advantages of modern microprocessors in conjunction with the low latency and enormous bandwidth of wavelength-division multiplexing (WDM) optics.
{"title":"Communication in macrochips using silicon photonics for high-performance and low-energy computing","authors":"J. Cunningham, A. Krishnamoorthy, Xuezhe Zheng, Guoliang Li, R. Ho, J. Lexau, I. Shubin, K. Raj","doi":"10.1109/VDAT.2009.5158088","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158088","url":null,"abstract":"There have been a number of recent high-profile advances in silicon-integrated optical devices, including low-loss silicon waveguides, integrated laser modulators and photodetectors, optical gratings for surface-normal attach of fibers to chips, and many more. These technologies open the possibility of using silicon-based nano-photonics inside a traditional computer system based on very large scale integration (VLSI) chips using todays most advanced complementary metal-oxide-silicon (CMOS) technologies. Such a system might offer the cost and computing performance advantages of modern microprocessors in conjunction with the low latency and enormous bandwidth of wavelength-division multiplexing (WDM) optics.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"05 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130656807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158117
Hsiang-Sheng Hu, Hsiao-Yun Chen, S. Jou
A novel FFT processor that can provide parallel-in-parallel-out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16e. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm2 by using 90 nm, 1V CMOS process.
{"title":"Novel FFT processor with parallel-in-parallel-out in normal order","authors":"Hsiang-Sheng Hu, Hsiao-Yun Chen, S. Jou","doi":"10.1109/VDAT.2009.5158117","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158117","url":null,"abstract":"A novel FFT processor that can provide parallel-in-parallel-out in normal order is proposed for high throughput required OFDM communication system, such as discrete Fourier transform (DFT)-based channel estimation in IEEE 802.16e. The hardware implementation results show the proposed 1024-point FFT architecture can achieve the throughput rate up to 1.28 G samples/sec and the execution time down to 7.3 us when working at 160 MHz. When working at the system required 83.3 MHz, it consumes 21.7 mW with 134474 gates (including memory) that occupy 0.471 mm2 by using 90 nm, 1V CMOS process.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123070301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158086
Prashant Saxena
With the worsening of interconnects due to scaling, the reliance of the original physical synthesis paradigm on merely some placement of the cells in order to predict net delays no longer suffices. Practitioners have augmented this paradigm over the years with increasingly sophisticated net models in an effort to improve the accuracy of the interconnect delay predictions. In this paper, we will review these advances and motivate their natural evolution towards “guaranteed” net delays by describing a new scheme known as persistence. Although a naïve implementation of persistence can result in unroutable circuits, we will describe how persistence can be applied intelligently in an industrial flow to improve the circuit optimization without impacting its congestion.
{"title":"The evolution of interconnect management in physical synthesis","authors":"Prashant Saxena","doi":"10.1109/VDAT.2009.5158086","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158086","url":null,"abstract":"With the worsening of interconnects due to scaling, the reliance of the original physical synthesis paradigm on merely some placement of the cells in order to predict net delays no longer suffices. Practitioners have augmented this paradigm over the years with increasingly sophisticated net models in an effort to improve the accuracy of the interconnect delay predictions. In this paper, we will review these advances and motivate their natural evolution towards “guaranteed” net delays by describing a new scheme known as persistence. Although a naïve implementation of persistence can result in unroutable circuits, we will describe how persistence can be applied intelligently in an industrial flow to improve the circuit optimization without impacting its congestion.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129532315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158113
Huan-Lin Chang, Hung-Chih Chang, Shang-Chi Yang, Hsi-Chun Tsai, Hsuan-Chih Li, C. Liu
This paper presents an improved SPICE macromodel of phase change random access memory (PCRAM). Based on the circuit-based model architecture in [1], the novelty of this work lies in (1) accurate modeling the current-voltage (I-V) plot including the snapback phenomenon, and (2) solution to the falling edge problem to avoid misrepresentation of the PCRAM state, and (3) calibration of the crystallization time for potential multilevel (ML) operation of the PCRAM.
{"title":"Improved SPICE macromodel of phase change random access memory","authors":"Huan-Lin Chang, Hung-Chih Chang, Shang-Chi Yang, Hsi-Chun Tsai, Hsuan-Chih Li, C. Liu","doi":"10.1109/VDAT.2009.5158113","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158113","url":null,"abstract":"This paper presents an improved SPICE macromodel of phase change random access memory (PCRAM). Based on the circuit-based model architecture in [1], the novelty of this work lies in (1) accurate modeling the current-voltage (I-V) plot including the snapback phenomenon, and (2) solution to the falling edge problem to avoid misrepresentation of the PCRAM state, and (3) calibration of the crystallization time for potential multilevel (ML) operation of the PCRAM.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122377582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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