Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158100
Wei-Jen Huang, Chein-Lung Chen, Shen-Iuan Liu
A wireless power telemetry with self-calibrated resonant frequency is presented. The proposed calibration scheme adjusts the resonant frequency of inductively secondary coil to match the incident frequency of inductively primary coil. To adjust the resonant frequency of the secondary coil, the received power efficiency is improved. By experimented results, the overall power efficiency with frequency calibration is improved by a factor of 33%, compared with that one without frequency calibration. This wireless power telemetry has been fabricated in a standard 0.35µm CMOS process, and the chip area is 1.536mm2 including I/O pads.
提出了一种自校准谐振频率的无线电力遥测技术。该校正方案通过调整感应次级线圈的谐振频率，使之与感应初级线圈的入射频率相匹配。通过调整二次线圈的谐振频率，提高了接收功率效率。实验结果表明，与不进行频率校准相比，进行频率校准后的整体功率效率提高了33%。这种无线电力遥测技术采用标准的0.35 μ m CMOS工艺制造，芯片面积为1.536mm2，包括I/O垫。
{"title":"A wireless power telemetry with self-calibrated resonant frequency","authors":"Wei-Jen Huang, Chein-Lung Chen, Shen-Iuan Liu","doi":"10.1109/VDAT.2009.5158100","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158100","url":null,"abstract":"A wireless power telemetry with self-calibrated resonant frequency is presented. The proposed calibration scheme adjusts the resonant frequency of inductively secondary coil to match the incident frequency of inductively primary coil. To adjust the resonant frequency of the secondary coil, the received power efficiency is improved. By experimented results, the overall power efficiency with frequency calibration is improved by a factor of 33%, compared with that one without frequency calibration. This wireless power telemetry has been fabricated in a standard 0.35µm CMOS process, and the chip area is 1.536mm2 including I/O pads.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129002787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158140
Yung-Chou Lin, Wen-Hung Hsieh, C. Hung
A third-order continuous-time delta-sigma comprised of Active-RC integrator and Gm-C integrator is presented. For the consideration of power, linearity and performance, the first integrator uses active-RC OpAmp and the others use Gm-C. To reduce the clock jitter sensitivity, we choose nonreturn-to-zero (NRZ) pulse shaping as our DAC type. For the realization of NTF zero optimization, we use resistors to reduce power consumption. The delta-sigma modulator is implemented in standard digital 0.18-µm CMOS process which achieves a 60-dB SNDR or 10-bits ENOB over a 1-MHz signal bandwidth at an OSR of 50. The power consumption of the continuous-time delta-sigma modulator itself is 13.7 mW from the 1.8-V supply.
{"title":"A continuous-time delta-sigma modulator using feedback resistors","authors":"Yung-Chou Lin, Wen-Hung Hsieh, C. Hung","doi":"10.1109/VDAT.2009.5158140","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158140","url":null,"abstract":"A third-order continuous-time delta-sigma comprised of Active-RC integrator and Gm-C integrator is presented. For the consideration of power, linearity and performance, the first integrator uses active-RC OpAmp and the others use Gm-C. To reduce the clock jitter sensitivity, we choose nonreturn-to-zero (NRZ) pulse shaping as our DAC type. For the realization of NTF zero optimization, we use resistors to reduce power consumption. The delta-sigma modulator is implemented in standard digital 0.18-µm CMOS process which achieves a 60-dB SNDR or 10-bits ENOB over a 1-MHz signal bandwidth at an OSR of 50. The power consumption of the continuous-time delta-sigma modulator itself is 13.7 mW from the 1.8-V supply.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"798 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123909544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158124
D. Appello
This paper proposes advances on fault localization methods suiting the learning of yield and reliability in VLSI cmos technologies. Industrial methodologies and tools will be discussed and the experimental results obtained through their implementation will be presented.
{"title":"Exploiting advanced fault localization methods for yield & reliability learning on SoCs","authors":"D. Appello","doi":"10.1109/VDAT.2009.5158124","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158124","url":null,"abstract":"This paper proposes advances on fault localization methods suiting the learning of yield and reliability in VLSI cmos technologies. Industrial methodologies and tools will be discussed and the experimental results obtained through their implementation will be presented.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117249204","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158090
A. Chow, D. Hopkins, R. Drost, R. Ho
Proximity Communication enables high-performance multi-chip packages by providing high-bandwidth, low-power, and low-latency chip-to-chip I/O. Chips are placed face-to-face, with only a few microns of separation, such that overlapping transceiver circuits can send and receive signals through capacitive or inductive coupling. Packaging chips in this way, however, presents a number of physical challenges. The multi-chip package must hold and maintain the chips in precise alignment. This paper presents a number of electrical and mechanical technologies that address these challenges to enable multi-chip integration using Proximity Communication.
{"title":"Enabling technologies for multi-chip integration using Proximity Communication","authors":"A. Chow, D. Hopkins, R. Drost, R. Ho","doi":"10.1109/VDAT.2009.5158090","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158090","url":null,"abstract":"Proximity Communication enables high-performance multi-chip packages by providing high-bandwidth, low-power, and low-latency chip-to-chip I/O. Chips are placed face-to-face, with only a few microns of separation, such that overlapping transceiver circuits can send and receive signals through capacitive or inductive coupling. Packaging chips in this way, however, presents a number of physical challenges. The multi-chip package must hold and maintain the chips in precise alignment. This paper presents a number of electrical and mechanical technologies that address these challenges to enable multi-chip integration using Proximity Communication.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126383889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158106
B. C. Schafer, T. Takenaka, K. Wakabayashi
This paper presents a microarchitectural design space exploration tool called cwbexplorer based on an Adpative Simulated Annealer Exploration Algorithm (ASA-ExpA) for behavioral descriptions written in untimed C or SystemC. Cwbexplorer automatically generates a series of designs given a set of constraints (area and latency) from an untimed high level language description. A commercial high level synthesis tool (CyberWorkBench) is used to synthesize each new architecture. The ASA-ExpA searches the design space based on the results of the previous synthesis, the global cost function and the given constraints. The global cost function weights are adaptively modified during the exploration to adjust the objective to minimize area or latency. Experimental results show that cwbexplorer successfully searches the design space fast and efficiently finding the smallest and fastest designs for most benchmarks, incurring in small penalties (5% in area and 8% in latency) for larger benchmarks while reducing the total runtime by an average of 66% compared to a brute force approach.
{"title":"Adaptive Simulated Annealer for high level synthesis design space exploration","authors":"B. C. Schafer, T. Takenaka, K. Wakabayashi","doi":"10.1109/VDAT.2009.5158106","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158106","url":null,"abstract":"This paper presents a microarchitectural design space exploration tool called cwbexplorer based on an Adpative Simulated Annealer Exploration Algorithm (ASA-ExpA) for behavioral descriptions written in untimed C or SystemC. Cwbexplorer automatically generates a series of designs given a set of constraints (area and latency) from an untimed high level language description. A commercial high level synthesis tool (CyberWorkBench) is used to synthesize each new architecture. The ASA-ExpA searches the design space based on the results of the previous synthesis, the global cost function and the given constraints. The global cost function weights are adaptively modified during the exploration to adjust the objective to minimize area or latency. Experimental results show that cwbexplorer successfully searches the design space fast and efficiently finding the smallest and fastest designs for most benchmarks, incurring in small penalties (5% in area and 8% in latency) for larger benchmarks while reducing the total runtime by an average of 66% compared to a brute force approach.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129932968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158143
Tong-Yu Hsieh, Kuen-Jong Lee, M. Breuer
In many multimedia applications, some faults induce errors that are user-imperceptible and thus are acceptable. By not testing for these faults, the effective yield can be significantly increased based on the principle of error-tolerance. However, studies have shown that test patterns generated by a conventional ATPG procedure targeting only unacceptable faults also detect many acceptable faults, resulting in a significant degradation in achievable yield improvement. In this paper we present a multi-phase test technique that can perfectly prevent this over-detection problem. Solid theoretical derivations are provided to validate the effectiveness of this technique. Compared with previous work, only a much smaller number of test patterns are required and thus the required test cost can be much lower. Experimental results on benchmark circuits illustrate the high efficiency of this novel technique.
{"title":"An efficient multi-phase test technique to perfectly prevent over-detection of acceptable faults for optimal yield improvement via error-tolerance","authors":"Tong-Yu Hsieh, Kuen-Jong Lee, M. Breuer","doi":"10.1109/VDAT.2009.5158143","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158143","url":null,"abstract":"In many multimedia applications, some faults induce errors that are user-imperceptible and thus are acceptable. By not testing for these faults, the effective yield can be significantly increased based on the principle of error-tolerance. However, studies have shown that test patterns generated by a conventional ATPG procedure targeting only unacceptable faults also detect many acceptable faults, resulting in a significant degradation in achievable yield improvement. In this paper we present a multi-phase test technique that can perfectly prevent this over-detection problem. Solid theoretical derivations are provided to validate the effectiveness of this technique. Compared with previous work, only a much smaller number of test patterns are required and thus the required test cost can be much lower. Experimental results on benchmark circuits illustrate the high efficiency of this novel technique.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122237618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158119
H. Hsu, Shi-Yu Huang
In this paper we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). The digitally controlled oscillator (DCO) is able to operate from 53 to 560 MHz with 5.1ps resolution. Combined with a programmable divider with multiplicative factor from 1 to 2046, various frequencies could be synthesized to meet different applications. In order to reduce output clock jitter after phase locking, we propose a three-step locking procedure. The phase can be locked quickly through a preliminary phase locking scheme and the jitter is then reduced by the proposed suppressive digital loop filter. Simulation results show the jitter performance is very close to that of free running DCO. The jitterPk-Pk and jitterRMS is 51ps and 6.74ps respectively when the output clock of ADPLL operates at 200Mhz.
{"title":"A low-jitter all-digital phase-locked loop using a suppressive digital loop filter","authors":"H. Hsu, Shi-Yu Huang","doi":"10.1109/VDAT.2009.5158119","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158119","url":null,"abstract":"In this paper we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). The digitally controlled oscillator (DCO) is able to operate from 53 to 560 MHz with 5.1ps resolution. Combined with a programmable divider with multiplicative factor from 1 to 2046, various frequencies could be synthesized to meet different applications. In order to reduce output clock jitter after phase locking, we propose a three-step locking procedure. The phase can be locked quickly through a preliminary phase locking scheme and the jitter is then reduced by the proposed suppressive digital loop filter. Simulation results show the jitter performance is very close to that of free running DCO. The jitterPk-Pk and jitterRMS is 51ps and 6.74ps respectively when the output clock of ADPLL operates at 200Mhz.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126855907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158164
P. Brisk, P. Ienne
The present formulation of the port assignment problem for binary commutative operators tries to minimize the number of wires connected to both the left and right inputs of the operator; intuitively, this minimizes the total number of inputs connected to both inputs, which reduces the size of the multiplexers that are instantiated. This paper revises the formulation to attempt to balance the difference between the number of wires connected to both inputs; minimizing the size of the larger multiplexer place on the input minimizes the delay through the operator.
{"title":"On the complexity of the Port Assignment Problem for Binary Commutative Operators in high-level synthesis","authors":"P. Brisk, P. Ienne","doi":"10.1109/VDAT.2009.5158164","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158164","url":null,"abstract":"The present formulation of the port assignment problem for binary commutative operators tries to minimize the number of wires connected to both the left and right inputs of the operator; intuitively, this minimizes the total number of inputs connected to both inputs, which reduces the size of the multiplexers that are instantiated. This paper revises the formulation to attempt to balance the difference between the number of wires connected to both inputs; minimizing the size of the larger multiplexer place on the input minimizes the delay through the operator.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126456140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158151
R. Chang, Wenjun Zhang
A novel procedure to extract all parameters from a compact double-π model for on-chip inductors has been presented. The major method used in the process is linear regression, which avoids iteration and complexity. The methodology presented here is used to extract parameters from the measured scattering matrices of symmetric inductors fabricated with a 0.18µm process. The comparisons between the predictions of the model based on the extracted parameters and the measurements demonstrate the effectiveness and accuracy of the proposed procedure over a broad frequency range even beyond the self-resonant frequencies(SRF)
{"title":"A comprehensive linear-regression-based Procedure for inductor parameter extraction","authors":"R. Chang, Wenjun Zhang","doi":"10.1109/VDAT.2009.5158151","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158151","url":null,"abstract":"A novel procedure to extract all parameters from a compact double-π model for on-chip inductors has been presented. The major method used in the process is linear regression, which avoids iteration and complexity. The methodology presented here is used to extract parameters from the measured scattering matrices of symmetric inductors fabricated with a 0.18µm process. The comparisons between the predictions of the model based on the extracted parameters and the measurements demonstrate the effectiveness and accuracy of the proposed procedure over a broad frequency range even beyond the self-resonant frequencies(SRF)","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131397397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158142
Wei-Ming Lin, Chao-Chyun Chen, Shen-Iuan Liu
An all-digital clock generator for dynamic frequency scaling is presented by using a cyclic clock multiplier. It realizes the fractional or multiplied output clock within four reference clock cycles. The frequency of the output clock can be programmed as Mfref/N (fref is the reference clock frequency, 1≦M≦7, and 1≦N≦8). It has been fabricated in a 0.18um CMOS process. The measured rms jitter of the output clock is 3ps when the input clock is 133MHz, M is 7, and N is 1 and consumes 53mW from a supply of 1.8V. The core area of this clock generator is 0.26mm2.
{"title":"An all-digital clock generator for dynamic frequency scaling","authors":"Wei-Ming Lin, Chao-Chyun Chen, Shen-Iuan Liu","doi":"10.1109/VDAT.2009.5158142","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158142","url":null,"abstract":"An all-digital clock generator for dynamic frequency scaling is presented by using a cyclic clock multiplier. It realizes the fractional or multiplied output clock within four reference clock cycles. The frequency of the output clock can be programmed as Mfref/N (fref is the reference clock frequency, 1≦M≦7, and 1≦N≦8). It has been fabricated in a 0.18um CMOS process. The measured rms jitter of the output clock is 3ps when the input clock is 133MHz, M is 7, and N is 1 and consumes 53mW from a supply of 1.8V. The core area of this clock generator is 0.26mm2.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131755607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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