Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158089
G. Chien, K. L. Loh
Wireless communication has become ubiquitous in everyday life. However, in the last two decades, much has changed in the RF transceiver design that provides the essential linkage between the antenna and baseband signal processing unit. As more and more wireless applications spring up in the commercial world and the data rate continues to climb at a fast trajectory, the RF transceiver design faces increasing challenges in many different areas. In this presentation, a brief review of the RF transceiver evolution will be introduced; followed by some discussions of transceiver design challenges in today's wireless communication system.
{"title":"Past, present and future of RF design in wireless communication","authors":"G. Chien, K. L. Loh","doi":"10.1109/VDAT.2009.5158089","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158089","url":null,"abstract":"Wireless communication has become ubiquitous in everyday life. However, in the last two decades, much has changed in the RF transceiver design that provides the essential linkage between the antenna and baseband signal processing unit. As more and more wireless applications spring up in the commercial world and the data rate continues to climb at a fast trajectory, the RF transceiver design faces increasing challenges in many different areas. In this presentation, a brief review of the RF transceiver evolution will be introduced; followed by some discussions of transceiver design challenges in today's wireless communication system.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130640116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158123
Mingqi Jiang, W. Tang, Evangeline F. Y. Young, Y. L. Wu
Due to the intrinsic difference between fan-in and fan-out counts of a retimed component, the number of flip-flops tends to be undesirably increased in a conventional retiming procedure, which can cause a significant area/power penalty on the retimed circuit. Nonetheless, because of the higher dominance on interconnect delays, without a mechanism to reflect real physical design accurately, the clock period produced by a retiming scheme will be unrealistic. To overcome these two major drawbacks of the conventional retiming technique, we propose a novel retiming flow combined with rewiring, being able to largely cut down flip-flops (FFs) while with the original retimed clock period uncompromised. For a more accurate delay estimation, all interconnect delays are formulated and calculated based on real placements. Experimental results show that this novel rewired retiming scheme can bring a reduction of 18.7% (on average) on the number of flip-flops compared to the original retiming without rewiring. This large FF reduction can be considered a free gain as the retimed clock period can still be kept without compromise in such flow. Further experiments have indicated that about 8.26% of the total dynamic power can be saved.
{"title":"Rewired retiming for free flip-flop reductions without delay penalty","authors":"Mingqi Jiang, W. Tang, Evangeline F. Y. Young, Y. L. Wu","doi":"10.1109/VDAT.2009.5158123","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158123","url":null,"abstract":"Due to the intrinsic difference between fan-in and fan-out counts of a retimed component, the number of flip-flops tends to be undesirably increased in a conventional retiming procedure, which can cause a significant area/power penalty on the retimed circuit. Nonetheless, because of the higher dominance on interconnect delays, without a mechanism to reflect real physical design accurately, the clock period produced by a retiming scheme will be unrealistic. To overcome these two major drawbacks of the conventional retiming technique, we propose a novel retiming flow combined with rewiring, being able to largely cut down flip-flops (FFs) while with the original retimed clock period uncompromised. For a more accurate delay estimation, all interconnect delays are formulated and calculated based on real placements. Experimental results show that this novel rewired retiming scheme can bring a reduction of 18.7% (on average) on the number of flip-flops compared to the original retiming without rewiring. This large FF reduction can be considered a free gain as the retimed clock period can still be kept without compromise in such flow. Further experiments have indicated that about 8.26% of the total dynamic power can be saved.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132093152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158087
F. O’Mahony, G. Balamurugan, J. Jaussi, J. Kennedy, M. Mansuri, S. Shekhar, B. Casper
High-speed CMOS microprocessor I/O has scaled aggressively over the past decade in terms of power and performance largely due to advances in equalization and clocking techniques. With future multi-core processors expected to require ≫1TB/s bandwidth and dramatically improved power efficiency, there has been some question as to whether electrical I/O will continue to satisfy chip-to-chip communication requirements over the next decade. In this paper, we show that electrical signaling has the power, performance, and density scaling potential to enable the next several generations of systems and applications. Circuit innovation is aggressively pushing link power efficiency toward 1–2mW/Gb/s while departures from legacy channels to include new topologies and materials can significantly improve the power/performance/density tradeoff. Statistical link-level design tools that allow designers to rapidly quantify high-level architecture tradeoffs will enable balanced link designs that co-optimize power, performance, and channel topology.
{"title":"The future of electrical I/O for microprocessors","authors":"F. O’Mahony, G. Balamurugan, J. Jaussi, J. Kennedy, M. Mansuri, S. Shekhar, B. Casper","doi":"10.1109/VDAT.2009.5158087","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158087","url":null,"abstract":"High-speed CMOS microprocessor I/O has scaled aggressively over the past decade in terms of power and performance largely due to advances in equalization and clocking techniques. With future multi-core processors expected to require ≫1TB/s bandwidth and dramatically improved power efficiency, there has been some question as to whether electrical I/O will continue to satisfy chip-to-chip communication requirements over the next decade. In this paper, we show that electrical signaling has the power, performance, and density scaling potential to enable the next several generations of systems and applications. Circuit innovation is aggressively pushing link power efficiency toward 1–2mW/Gb/s while departures from legacy channels to include new topologies and materials can significantly improve the power/performance/density tradeoff. Statistical link-level design tools that allow designers to rapidly quantify high-level architecture tradeoffs will enable balanced link designs that co-optimize power, performance, and channel topology.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132652852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we introduce a new test paradigm called indirect-access scan test, demonstrated over the HOY test platform [12]. Unlike the traditional ATE-based testing, the test data in this paradigm are sent to the chip under test via packets over a single indirect channel. Although there is extra test time overhead for establishing the store-and-forward communication, it offers almost unlimited test memory - a highly desirable property since the large volume of test data today could easily blow up a traditional ATEs test memory. In addition to demonstrating the feasibility of this new paradigm, we also show that its efficiency can be substantially improved by two schemes; i.e., primary input (PI) data encoding and dynamic packet formatting. For a design with 155K gates, the speed-up achieved can be more than 50X.
{"title":"iScan: Indirect-access scan test over HOY test platform","authors":"Chao-Wen Tzeng, Chun-Yen Lin, Shi-Yu Huang, Chih-Tsun Huang, J. Liou, Hsi-Pin Ma, Po-Chiun Huang, Cheng-Wen Wu","doi":"10.1109/VDAT.2009.5158095","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158095","url":null,"abstract":"In this paper, we introduce a new test paradigm called indirect-access scan test, demonstrated over the HOY test platform [12]. Unlike the traditional ATE-based testing, the test data in this paradigm are sent to the chip under test via packets over a single indirect channel. Although there is extra test time overhead for establishing the store-and-forward communication, it offers almost unlimited test memory - a highly desirable property since the large volume of test data today could easily blow up a traditional ATEs test memory. In addition to demonstrating the feasibility of this new paradigm, we also show that its efficiency can be substantially improved by two schemes; i.e., primary input (PI) data encoding and dynamic packet formatting. For a design with 155K gates, the speed-up achieved can be more than 50X.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125105515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158153
Hsin-Chia Lu, Jhih-Kuan Wu, Chuan Pan, C. Chiang, H. Fu
Two low pass filters for 2.4GHz are developed using IPD (integrated passive device) process. The IPD process uses BCB as dielectric for inductor and SiO2 for capacitor on glass. Low-pass filters using lump elements are synthesized based on standard filter synthesis process. Shunt capacitors are added to inductors to create transmission zeros for harmonic suppression. Low insertion loss and good harmonic suppression at 2nd and 3rd order are observed in both types of low pass filters in simulation and measurement.
{"title":"2.4 GHz low-pass filters with harmonic suppression using integrated passive device process","authors":"Hsin-Chia Lu, Jhih-Kuan Wu, Chuan Pan, C. Chiang, H. Fu","doi":"10.1109/VDAT.2009.5158153","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158153","url":null,"abstract":"Two low pass filters for 2.4GHz are developed using IPD (integrated passive device) process. The IPD process uses BCB as dielectric for inductor and SiO2 for capacitor on glass. Low-pass filters using lump elements are synthesized based on standard filter synthesis process. Shunt capacitors are added to inductors to create transmission zeros for harmonic suppression. Low insertion loss and good harmonic suppression at 2nd and 3rd order are observed in both types of low pass filters in simulation and measurement.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130452363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158091
Jia-Hui Wang, H. Zheng, Chien-Hung Tsai, Chin-Tien Chang, Ching-Chung Lee, Chen-Yu Wang
A new compact rail-to-rail buffer amplifier for active matrix liquid crystal display source driver applications is proposed. Two complementary buffer amplifiers driving a pair of column lines are used to realize a rail-to-rail driver. The compact buffer amplifier has a large driving capability with the function of charge and discharge provided by the current positive-feedback (CPF). The CPF can increase the charge capability in conventional class-A pMOS input buffer amplifiers and increases the discharge capability in conventional class-A nMOS input buffer amplifiers. The compact rail-to-rail buffer amplifier is implemented using 0.35µm CMOS 2-poly 4-metal process technology. The quiescent current consumed is 2.8µA and 3µA for a pMOS input buffer amplifier and an nMOS input buffer amplifier, respectively.
{"title":"A compact rail-to-rail buffer with current positive-feedback for LCD source driver","authors":"Jia-Hui Wang, H. Zheng, Chien-Hung Tsai, Chin-Tien Chang, Ching-Chung Lee, Chen-Yu Wang","doi":"10.1109/VDAT.2009.5158091","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158091","url":null,"abstract":"A new compact rail-to-rail buffer amplifier for active matrix liquid crystal display source driver applications is proposed. Two complementary buffer amplifiers driving a pair of column lines are used to realize a rail-to-rail driver. The compact buffer amplifier has a large driving capability with the function of charge and discharge provided by the current positive-feedback (CPF). The CPF can increase the charge capability in conventional class-A pMOS input buffer amplifiers and increases the discharge capability in conventional class-A nMOS input buffer amplifiers. The compact rail-to-rail buffer amplifier is implemented using 0.35µm CMOS 2-poly 4-metal process technology. The quiescent current consumed is 2.8µA and 3µA for a pMOS input buffer amplifier and an nMOS input buffer amplifier, respectively.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124539469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-28DOI: 10.1109/VDAT.2009.5158128
Cheng-Zhou Zhan, Kai-Yuan Jheng, Yen-Lian Chen, Ting-Jhun Jheng, A. Wu
Multiple-input multiple-output (MIMO) wireless communication systems with orthogonal frequency-division multiplexing (OFDM) achieve high spectral efficiency high channel capacity, and many MIMO-OFDM systems use the spatial multiplexing technique to improve the system performance. The MIMO-OFDM systems require the singular values and the corresponding singular vectors of the channel matrix by exploiting singular value decomposition (SVD). The information of the right singular-vector matrix can be fed back to the transmitter for linear precoding to improve the error performance when facing the channel matrix with rank deficiency problem. This work proposes a SVD algorithm with fast convergence speed, which is suitable for the MIMO channels with short coherent time. The proposed SVD algorithm has the following features: (1) low total computational complexity, (2) fast convergence speed, (3) the ability of reconfigurable to different numbers of transmitter and receiver antennas, and (4) insensitive to the dynamic range problem, which is suitable for hardware implementation.
{"title":"High-convergence-speed low-computation-complexity SVD algorithm for MIMO-OFDM systems","authors":"Cheng-Zhou Zhan, Kai-Yuan Jheng, Yen-Lian Chen, Ting-Jhun Jheng, A. Wu","doi":"10.1109/VDAT.2009.5158128","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158128","url":null,"abstract":"Multiple-input multiple-output (MIMO) wireless communication systems with orthogonal frequency-division multiplexing (OFDM) achieve high spectral efficiency high channel capacity, and many MIMO-OFDM systems use the spatial multiplexing technique to improve the system performance. The MIMO-OFDM systems require the singular values and the corresponding singular vectors of the channel matrix by exploiting singular value decomposition (SVD). The information of the right singular-vector matrix can be fed back to the transmitter for linear precoding to improve the error performance when facing the channel matrix with rank deficiency problem. This work proposes a SVD algorithm with fast convergence speed, which is suitable for the MIMO channels with short coherent time. The proposed SVD algorithm has the following features: (1) low total computational complexity, (2) fast convergence speed, (3) the ability of reconfigurable to different numbers of transmitter and receiver antennas, and (4) insensitive to the dynamic range problem, which is suitable for hardware implementation.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129287481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-04-01DOI: 10.1109/VDAT.2009.5158144
Hsiang-Ning Liu, Yu-Jen Huang, Jin-Fu Li
Network-on-chip is one popular interconnection infrastructure for giga-scale integrated chips. Moreover, the number of memory cores in such chips usually is very large. This paper proposes an efficient built-in self-repair (BISR) method for repairing memories in NoCs. By reusing the communication links in NoCs, the BISR scheme can repair multiple memories using one BISR circuit without incurring the problem of routing. To increase the repair efficiency, a global spare memory is designed for repairing multiple memories. Experimental results show that the proposed BISR scheme can achieve very high repair efficiency. Also, the area overhead of the BISR circuit is very low—only about 1.38% for fifteen 8K×64-bit memories.
{"title":"A built-in self-repair method for RAMs in mesh-based NoCs","authors":"Hsiang-Ning Liu, Yu-Jen Huang, Jin-Fu Li","doi":"10.1109/VDAT.2009.5158144","DOIUrl":"https://doi.org/10.1109/VDAT.2009.5158144","url":null,"abstract":"Network-on-chip is one popular interconnection infrastructure for giga-scale integrated chips. Moreover, the number of memory cores in such chips usually is very large. This paper proposes an efficient built-in self-repair (BISR) method for repairing memories in NoCs. By reusing the communication links in NoCs, the BISR scheme can repair multiple memories using one BISR circuit without incurring the problem of routing. To increase the repair efficiency, a global spare memory is designed for repairing multiple memories. Experimental results show that the proposed BISR scheme can achieve very high repair efficiency. Also, the area overhead of the BISR circuit is very low—only about 1.38% for fifteen 8K×64-bit memories.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121544118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-01-21DOI: 10.1109/ASPDAC.2008.4484013
F. Tseng
The semiconductor industry has been in a path of steady growth tolerating waves of economical ups and downturns. We are currently facing a severe one that very few of us have encountered in our lifetime. Nevertheless, it is not a question whether the growth curve will resume. It is always a matter of when it does.
{"title":"The future of semiconductor industry - A foundry's perspective","authors":"F. Tseng","doi":"10.1109/ASPDAC.2008.4484013","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484013","url":null,"abstract":"The semiconductor industry has been in a path of steady growth tolerating waves of economical ups and downturns. We are currently facing a severe one that very few of us have encountered in our lifetime. Nevertheless, it is not a question whether the growth curve will resume. It is always a matter of when it does.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126507850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/vtsa.2009.5159266
R.P. de Vries
For decades semiconductor developments have been driven by Moore's Law productivity gains. This led to extremely fast digital processors, increase in bandwidth and huge memories that boost productivity of PCs, mobile phones, and other applications demanding heavy data traffic and storage. The economics of the IC industry as well as developments in society, however, will cause the trend to turn, leading to a paradigm shift in the semiconductors world.
{"title":"From living faster to living better","authors":"R.P. de Vries","doi":"10.1109/vtsa.2009.5159266","DOIUrl":"https://doi.org/10.1109/vtsa.2009.5159266","url":null,"abstract":"For decades semiconductor developments have been driven by Moore's Law productivity gains. This led to extremely fast digital processors, increase in bandwidth and huge memories that boost productivity of PCs, mobile phones, and other applications demanding heavy data traffic and storage. The economics of the IC industry as well as developments in society, however, will cause the trend to turn, leading to a paradigm shift in the semiconductors world.","PeriodicalId":246670,"journal":{"name":"2009 International Symposium on VLSI Design, Automation and Test","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116366548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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