Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683373
D. Grant, G. Lemieux
To accelerate many computational software algorithms, designers are implementing them as computational circuits. These algorithms are diverse and include molecular dynamics, weather simulation, video encoding, and financial modelling. Circuit designers repeatedly synthesize and simulate circuits for debugging and incremental design, but due to the size of computational circuits these steps are slow and waste designer productivity. In this paper we present an architecture and tool flow for rapidly compiling and simulating/executing computational circuits. We use a motion estimation circuit to demonstrate the performance vs. capacity scalability of our architecture, and show that the performance is comparable to an FPGA-based design.
{"title":"A spatial computing architecture for implementing computational circuits","authors":"D. Grant, G. Lemieux","doi":"10.1109/MNRC.2008.4683373","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683373","url":null,"abstract":"To accelerate many computational software algorithms, designers are implementing them as computational circuits. These algorithms are diverse and include molecular dynamics, weather simulation, video encoding, and financial modelling. Circuit designers repeatedly synthesize and simulate circuits for debugging and incremental design, but due to the size of computational circuits these steps are slow and waste designer productivity. In this paper we present an architecture and tool flow for rapidly compiling and simulating/executing computational circuits. We use a motion estimation circuit to demonstrate the performance vs. capacity scalability of our architecture, and show that the performance is comparable to an FPGA-based design.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116914490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683392
A. Dinh, D. Teng, L. Chen, Y. Shi, C. McCrosky, J. Basran, V. Del Bello-Hass, S. Ko, A. Ralhan, D. Williams, N. Windels, A. Choudhury
The FANFARE project has developed a system to fulfill the need for a wearable device to collect data for fall analysis. The system consists of a computer and a wireless sensor network to measure, display and store fall related parameters such as postural activities and heart rate variability. Ease of use and low power were considered in the design. The system was built and successfully tested. Medical community now has the tool to collect and analyze fall related data for the purpose of detection and prevention of unintentional falls.
{"title":"A fall detection and near-fall data collection system","authors":"A. Dinh, D. Teng, L. Chen, Y. Shi, C. McCrosky, J. Basran, V. Del Bello-Hass, S. Ko, A. Ralhan, D. Williams, N. Windels, A. Choudhury","doi":"10.1109/MNRC.2008.4683392","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683392","url":null,"abstract":"The FANFARE project has developed a system to fulfill the need for a wearable device to collect data for fall analysis. The system consists of a computer and a wireless sensor network to measure, display and store fall related parameters such as postural activities and heart rate variability. Ease of use and low power were considered in the design. The system was built and successfully tested. Medical community now has the tool to collect and analyze fall related data for the purpose of detection and prevention of unintentional falls.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117149291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683404
V. Narasimhan, N. Yastrebova, C. Valdivia, T. Hall, K. Hinzer, D. Masson, S. Fafard, A. Jaouad, R. Arès, V. Aimez
To optimize the design of multi-junction photovoltaic devices, robust models of the tunnel junctions connecting sub-cells are essential. In this paper, we describe the effects of varying key parameters in a model of an AlGaAs tunnel junction. We noted two peaks in the current-voltage behavior of the AlGaAs tunnel junction under consideration. We found that the effective Richardson constant scaling factors in the model primarily affected the magnitude of the main peak. The p++ doping concentration impacted the height of both peaks, while the n++ doping concentration changed the magnitude of the main peak and shifted the secondary peak.
{"title":"Effect of parameter variations on the current-voltage behavior of AlGaAs tunnel junction models","authors":"V. Narasimhan, N. Yastrebova, C. Valdivia, T. Hall, K. Hinzer, D. Masson, S. Fafard, A. Jaouad, R. Arès, V. Aimez","doi":"10.1109/MNRC.2008.4683404","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683404","url":null,"abstract":"To optimize the design of multi-junction photovoltaic devices, robust models of the tunnel junctions connecting sub-cells are essential. In this paper, we describe the effects of varying key parameters in a model of an AlGaAs tunnel junction. We noted two peaks in the current-voltage behavior of the AlGaAs tunnel junction under consideration. We found that the effective Richardson constant scaling factors in the model primarily affected the magnitude of the main peak. The p++ doping concentration impacted the height of both peaks, while the n++ doping concentration changed the magnitude of the main peak and shifted the secondary peak.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114368315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683388
Dianyong Chen, Bo Wang, B. Liang, Dezhong Cheng, T. Kwasniewski
Wireline transceivers for high-speed data transmission through backplane and ethernet cables are important applications for microelectronic and nanoelectronic CMOS technologies. Although many circuit simulators provide correct system-level and transistor-level simulations, they usually fail to give correct results for many highly lossy or/and highly dispersive channels. This paper discusses the advanced simulator that we developed. It can give correct simulation results for those channels. It can also process those channel model files to allow commercial circuit simulators to give correct results. This simulator when used together with commercial simulators gives correct system-level and transistor-level simulation results.
{"title":"An improved simulation method for high-speed data transmission through electrical backplane","authors":"Dianyong Chen, Bo Wang, B. Liang, Dezhong Cheng, T. Kwasniewski","doi":"10.1109/MNRC.2008.4683388","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683388","url":null,"abstract":"Wireline transceivers for high-speed data transmission through backplane and ethernet cables are important applications for microelectronic and nanoelectronic CMOS technologies. Although many circuit simulators provide correct system-level and transistor-level simulations, they usually fail to give correct results for many highly lossy or/and highly dispersive channels. This paper discusses the advanced simulator that we developed. It can give correct simulation results for those channels. It can also process those channel model files to allow commercial circuit simulators to give correct results. This simulator when used together with commercial simulators gives correct system-level and transistor-level simulation results.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114563179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683394
M. Hagman, T. Kwasniewski
In this work, two unique decision feedback equalizers (DFE) for use in 10 Gb/s optical communications are presented. These equalizers are effective at cancelling post-cursor ISI as well as pre-cursor ISI without the use of a feed-forward equalizer (FFE). The removal of the FFE equalizer is desirable as it is very expensive from a chip real-estate perspective. The synthetic transmission lines used to achieve the analog delay in FFE filters also suffer from performance issues such as limited bandwidth, impedance mismatches, and nonlinearities which degrade the efficacy of the filter. The proposed filter structures will be evaluated via numerical simulation, and a comparison with standard FFE/DFE techniques will be made.
{"title":"Two enhanced decision feedback equalizers for 10Gb/s optical communications","authors":"M. Hagman, T. Kwasniewski","doi":"10.1109/MNRC.2008.4683394","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683394","url":null,"abstract":"In this work, two unique decision feedback equalizers (DFE) for use in 10 Gb/s optical communications are presented. These equalizers are effective at cancelling post-cursor ISI as well as pre-cursor ISI without the use of a feed-forward equalizer (FFE). The removal of the FFE equalizer is desirable as it is very expensive from a chip real-estate perspective. The synthetic transmission lines used to achieve the analog delay in FFE filters also suffer from performance issues such as limited bandwidth, impedance mismatches, and nonlinearities which degrade the efficacy of the filter. The proposed filter structures will be evaluated via numerical simulation, and a comparison with standard FFE/DFE techniques will be made.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116435122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683365
S. Amini, C. Plett
The design and analysis of very low-voltage driven charge pumps powered by RF telemetry is proposed. The use of thick oxide zero threshold voltage transistors along with appropriately sized boosting capacitors and matching techniques allows for charge pumps capable of achieving high voltage DC outputs with very low input voltages. Two test chips have been fabricated, an 11 stage pump and a 12 stage pump in 1.2 V 0.13-mum standard CMOS process. The pumps are capable of generating an output voltage above 1.2 volts with input voltages below 100 mV making them ideal for generating DC supplies from low RF scavenged sources.
提出了一种基于射频遥测技术的极低压驱动电荷泵的设计与分析。使用厚氧化物零阈值电压晶体管以及适当尺寸的升压电容器和匹配技术，可以使电荷泵能够以非常低的输入电压实现高压直流输出。两个测试芯片，一个11级泵和一个12级泵在1.2 V 0.13妈标准CMOS工艺。该泵能够产生1.2伏以上的输出电压，输入电压低于100毫伏，使其成为从低射频清除源产生直流电源的理想选择。
{"title":"Design and analysis of very low voltage charge pumps for RFID tags","authors":"S. Amini, C. Plett","doi":"10.1109/MNRC.2008.4683365","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683365","url":null,"abstract":"The design and analysis of very low-voltage driven charge pumps powered by RF telemetry is proposed. The use of thick oxide zero threshold voltage transistors along with appropriately sized boosting capacitors and matching techniques allows for charge pumps capable of achieving high voltage DC outputs with very low input voltages. Two test chips have been fabricated, an 11 stage pump and a 12 stage pump in 1.2 V 0.13-mum standard CMOS process. The pumps are capable of generating an output voltage above 1.2 volts with input voltages below 100 mV making them ideal for generating DC supplies from low RF scavenged sources.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129919277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683368
P. Petrashin, G. Peretti, E. Romero
In this work, we explore the ability of oscillation-based test (OBT) for testing OTA-C filters. Adopting a second-order band pass filter as a case study, we present a scheme that uses a non linear characteristic in the feedback loop. The effectiveness of the strategy is qualified by means of fault simulation.
{"title":"Oscillation-Based Test in OTA-C filters: A case study","authors":"P. Petrashin, G. Peretti, E. Romero","doi":"10.1109/MNRC.2008.4683368","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683368","url":null,"abstract":"In this work, we explore the ability of oscillation-based test (OBT) for testing OTA-C filters. Adopting a second-order band pass filter as a case study, we present a scheme that uses a non linear characteristic in the feedback loop. The effectiveness of the strategy is qualified by means of fault simulation.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131045185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683391
M. Byers, J. Di
Exponentiation is an important mathematical operation in many areas, and is constantly being researched for more efficient methods. This paper presents a power efficient implementation of integer modular exponentiation using discrete logarithm transformation. By transforming the base of an exponent, this method is able to perform modular exponentiation without the use of multipliers. Originally developed and implemented for high speed applications, this method has been modified and implemented for low power while maintaining comparable performance. The design is created and simulated with a repeative-square design for comparison purpose. The two circuits are compared in terms of speed and power consumption. Results show that for bus sizes greater than 32 bit, the proposed design is able to use only approximately 40% of the power that the repeative-square counterpart consumes.
{"title":"Low power modular integer exponentiation using discrete logarithm transformation","authors":"M. Byers, J. Di","doi":"10.1109/MNRC.2008.4683391","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683391","url":null,"abstract":"Exponentiation is an important mathematical operation in many areas, and is constantly being researched for more efficient methods. This paper presents a power efficient implementation of integer modular exponentiation using discrete logarithm transformation. By transforming the base of an exponent, this method is able to perform modular exponentiation without the use of multipliers. Originally developed and implemented for high speed applications, this method has been modified and implemented for low power while maintaining comparable performance. The design is created and simulated with a repeative-square design for comparison purpose. The two circuits are compared in terms of speed and power consumption. Results show that for bus sizes greater than 32 bit, the proposed design is able to use only approximately 40% of the power that the repeative-square counterpart consumes.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132913903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683417
Q. Zeng, G. Delisle
In this paper, an efficient time domain technique is developed to solve the impulse response of a Debye half space without performing tedious and complicated mathematical manipulations. Both horizontally and vertically polarized plane waves that are obliquely incident onto the interface between free space and a Debye medium are discussed. This technique is based on numerical inversion of Laplace transform, leads to good accuracy, and has a simple algorithm, short calculation time, small required memory size, readily controlled error and wide application range. The achieved results are meaningful and useful in microelectronics, phonics, material science and biomedical engineering, and agree very well with those published in the literature, validating the correctness and effectiveness of our technique.
{"title":"Transient analysis of plane wave reflection from a Debye half space","authors":"Q. Zeng, G. Delisle","doi":"10.1109/MNRC.2008.4683417","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683417","url":null,"abstract":"In this paper, an efficient time domain technique is developed to solve the impulse response of a Debye half space without performing tedious and complicated mathematical manipulations. Both horizontally and vertically polarized plane waves that are obliquely incident onto the interface between free space and a Debye medium are discussed. This technique is based on numerical inversion of Laplace transform, leads to good accuracy, and has a simple algorithm, short calculation time, small required memory size, readily controlled error and wide application range. The achieved results are meaningful and useful in microelectronics, phonics, material science and biomedical engineering, and agree very well with those published in the literature, validating the correctness and effectiveness of our technique.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121688038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683387
M. Boule, Z. Zilic
This paper outlines the MBAC tool for the generation of assertion checkers in hardware. We begin with a high-level presentation of the automated compilation of assertions into checkers, and proceed to overview the multitude of applications of resource-efficient circuit-level checkers in the field of logic design and verification. A summary of experimental results is also given to show the current state of the MBAC tool, compared to the best known checker generator from IBM.
{"title":"Assertion checkers - enablers of quality design","authors":"M. Boule, Z. Zilic","doi":"10.1109/MNRC.2008.4683387","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683387","url":null,"abstract":"This paper outlines the MBAC tool for the generation of assertion checkers in hardware. We begin with a high-level presentation of the automated compilation of assertions into checkers, and proceed to overview the multitude of applications of resource-efficient circuit-level checkers in the field of logic design and verification. A summary of experimental results is also given to show the current state of the MBAC tool, compared to the best known checker generator from IBM.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121862707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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