Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683382
N. Sarkar, R. Mansour
We report on an integrated scanning probe microscope (SPM) fabricated in a CMOS-MEMS process. The design of this device is driven by the requirements of an atomically precise manufacturing (APM) approach based on patterned atomic layer epitaxy (ALE). A scan range of 10 mum times 10 mum is achieved with in-plane electrothermal actuation, and the cantileverpsilas out-of-plane range of motion enables a 30 mum sample approach. A test structure to optimize the in-plane actuator design is preseented, and its results are compared to an FEA model. Piezoresistive strain gauges and temperature sensors are strategically located in the in-plane actuators and the out-of-plane cantilever for use in an off-chip closed-loop positioning system.
报道了一种基于CMOS-MEMS工艺的集成扫描探针显微镜(SPM)。该器件的设计是由基于图像化原子层外延(ALE)的原子精密制造(APM)方法的需求驱动的。通过平面内电热驱动，可以实现10 μ m × 10 μ m的扫描范围，而悬臂悬臂的平面外运动范围可以实现30 μ m的样品接近。提出了一种优化平面内作动器设计的试验结构，并将其结果与有限元模型进行了比较。压阻式应变片和温度传感器被巧妙地放置在平面内执行器和平面外悬臂上，用于片外闭环定位系统。
{"title":"A CMOS-MEMS scanning probe microscope with integrated position sensors","authors":"N. Sarkar, R. Mansour","doi":"10.1109/MNRC.2008.4683382","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683382","url":null,"abstract":"We report on an integrated scanning probe microscope (SPM) fabricated in a CMOS-MEMS process. The design of this device is driven by the requirements of an atomically precise manufacturing (APM) approach based on patterned atomic layer epitaxy (ALE). A scan range of 10 mum times 10 mum is achieved with in-plane electrothermal actuation, and the cantileverpsilas out-of-plane range of motion enables a 30 mum sample approach. A test structure to optimize the in-plane actuator design is preseented, and its results are compared to an FEA model. Piezoresistive strain gauges and temperature sensors are strategically located in the in-plane actuators and the out-of-plane cantilever for use in an off-chip closed-loop positioning system.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121361557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683372
S. Bourduas, Z. Zilic
This paper uses high-level simulation models written in SystemC to compare the performance characteristics of two wormhole-routed multistage ring architectures: a hierarchical ring and a two-dimensional hyper ring. The hierarchical ring architecture has a single global ring, which limits its bisection bandwidth. The hyper ring is presented as an improvement over the hierarchical ring, whereby a second global ring is used to double the bisection bandwidth. Furthermore, a ldquofatrdquo variant of each architecture is considered, which use bidirectional global rings to increase the bisection bandwidth of the original architectures.
{"title":"A comparison of two multistage ring architectures for NoC using high-level simulation models","authors":"S. Bourduas, Z. Zilic","doi":"10.1109/MNRC.2008.4683372","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683372","url":null,"abstract":"This paper uses high-level simulation models written in SystemC to compare the performance characteristics of two wormhole-routed multistage ring architectures: a hierarchical ring and a two-dimensional hyper ring. The hierarchical ring architecture has a single global ring, which limits its bisection bandwidth. The hyper ring is presented as an improvement over the hierarchical ring, whereby a second global ring is used to double the bisection bandwidth. Furthermore, a ldquofatrdquo variant of each architecture is considered, which use bidirectional global rings to increase the bisection bandwidth of the original architectures.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126963542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683395
S. R. Hasan, N. Bélanger, Y. Savaria
As deep sub-micron (DSM) technology improves, the need for interfacing modules in multiple clock domains (MCD) is increasing. This work proposes a novel interfacing method for point-to-point communication between modules whose frequencies are rationally related. The introduction of two stages of FIFO-like interfacing registers makes this method skew tolerant. It also allows a slower module to receive or transmit safely data to or from a faster module without slowing down the frequency of the faster module, which is a quality that is required for serializers and deserializers. A complete functional validation of the proposed interfacing method is performed using RTL-level simulation.
{"title":"All-digital skew-tolerant interfacing method for systems with rational frequency ratios among Multiple Clock Domains: Leveraging a priori timing information","authors":"S. R. Hasan, N. Bélanger, Y. Savaria","doi":"10.1109/MNRC.2008.4683395","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683395","url":null,"abstract":"As deep sub-micron (DSM) technology improves, the need for interfacing modules in multiple clock domains (MCD) is increasing. This work proposes a novel interfacing method for point-to-point communication between modules whose frequencies are rationally related. The introduction of two stages of FIFO-like interfacing registers makes this method skew tolerant. It also allows a slower module to receive or transmit safely data to or from a faster module without slowing down the frequency of the faster module, which is a quality that is required for serializers and deserializers. A complete functional validation of the proposed interfacing method is performed using RTL-level simulation.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114663036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683397
Y. Hosseini, S. Ikram, K. Kaler
We report on the development of a feedback control system that utilizes a custom CMOS optical sensor, to facilitate controlled and precise dispensing and transport of nano-liter liquid sample droplets by leveraging liquid-DEP (L-DEP) and droplet-DEP (D-DEP) actuation schemes. Operationally, L-DEP and D-DEP typically require application of AC voltages across a pair of coplanar microelectrodes for a very short duration of time (~50 ms). The feedback control scheme, utilized to control the droplet dispensing and transport, relies on a CMOS optical sensor to detect perturbations in the light intensity induced by the liquid finger or spherical droplet, as they traverse over the optical sensor and interact with the incident illumination. A fully functional prototype was developed and its operation successfully tested using example L-DEP and D-DEP structures.
我们报告了一种反馈控制系统的开发，该系统利用定制的CMOS光学传感器，通过利用液体- dep (L-DEP)和液滴- dep (D-DEP)驱动方案，促进纳米升液体样品液滴的控制和精确分配和运输。操作上，L-DEP和D-DEP通常需要在一对共面微电极上施加交流电压，持续时间很短(~50 ms)。反馈控制方案用于控制液滴的分配和传输，它依靠CMOS光学传感器来检测液体手指或球形液滴在光学传感器上移动并与入射照明相互作用时引起的光强扰动。开发了一个功能齐全的原型，并使用示例L-DEP和D-DEP结构成功测试了其操作。
{"title":"A CMOS Optical feedback control for high-speed DEP based microfluidic actuation","authors":"Y. Hosseini, S. Ikram, K. Kaler","doi":"10.1109/MNRC.2008.4683397","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683397","url":null,"abstract":"We report on the development of a feedback control system that utilizes a custom CMOS optical sensor, to facilitate controlled and precise dispensing and transport of nano-liter liquid sample droplets by leveraging liquid-DEP (L-DEP) and droplet-DEP (D-DEP) actuation schemes. Operationally, L-DEP and D-DEP typically require application of AC voltages across a pair of coplanar microelectrodes for a very short duration of time (~50 ms). The feedback control scheme, utilized to control the droplet dispensing and transport, relies on a CMOS optical sensor to detect perturbations in the light intensity induced by the liquid finger or spherical droplet, as they traverse over the optical sensor and interact with the incident illumination. A fully functional prototype was developed and its operation successfully tested using example L-DEP and D-DEP structures.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114892384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683367
Ming Zeng, B. Shastri, N. Zicha, M. V. Schueren, D. Plant
We demonstrate a 5 Gb/s burst-mode receiver (BMRx) featuring automatic phase acquisition using a clock phase aligner, and forward-error correction using (64, 57) Hamming codes. This BMRx provides instantaneous (0-bit) phase acquisition with packet-loss ratio < 10-6 and bit-error rate < 10-10 for any phase step (plusmn2pi rads) between consecutive packets. Our design is based on an oversampling local oscillator operated at twice the bit rate and a phase picking algorithm.
{"title":"5 Gb/s burst-mode clock phase aligner with (64, 57) Hamming codes for GPON applications","authors":"Ming Zeng, B. Shastri, N. Zicha, M. V. Schueren, D. Plant","doi":"10.1109/MNRC.2008.4683367","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683367","url":null,"abstract":"We demonstrate a 5 Gb/s burst-mode receiver (BMRx) featuring automatic phase acquisition using a clock phase aligner, and forward-error correction using (64, 57) Hamming codes. This BMRx provides instantaneous (0-bit) phase acquisition with packet-loss ratio < 10-6 and bit-error rate < 10-10 for any phase step (plusmn2pi rads) between consecutive packets. Our design is based on an oversampling local oscillator operated at twice the bit rate and a phase picking algorithm.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128207537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683408
Bo Wang, Dianyong Chen, B. Liang, T. Kwasniewski
This paper presents a biasing optimization technique for high-speed digital circuits design with advanced CMOS nanotechnology. Modern CMOS nanotechnology introduces several new problems in high-speed circuits design. As the fastest signal frequency components approach the peak transition frequency of the MOSFET, which depends heavily on the biasing voltage, the optimized biasing techniques become very important in high-speed circuits. Many trade-offs in the high-speed circuits need to be considered, and either power or headroom may be traded for higher speed. The optimized biasing technique is thoroughly analyzed first in this paper, and a typical high-speed CML circuit is designed based on this technique.
{"title":"Optimized biasing technique for high-speed digital circuits with advanced CMOS nanotechnology","authors":"Bo Wang, Dianyong Chen, B. Liang, T. Kwasniewski","doi":"10.1109/MNRC.2008.4683408","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683408","url":null,"abstract":"This paper presents a biasing optimization technique for high-speed digital circuits design with advanced CMOS nanotechnology. Modern CMOS nanotechnology introduces several new problems in high-speed circuits design. As the fastest signal frequency components approach the peak transition frequency of the MOSFET, which depends heavily on the biasing voltage, the optimized biasing techniques become very important in high-speed circuits. Many trade-offs in the high-speed circuits need to be considered, and either power or headroom may be traded for higher speed. The optimized biasing technique is thoroughly analyzed first in this paper, and a typical high-speed CML circuit is designed based on this technique.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122937646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683370
J. Ho, G. Lemieux
PERG is an FPGA application for accelerating detection of computer virus signatures (patterns). A pattern consists of a sequence of one or more segments separated by gaps of fixed lengths. PERG preprocesses a database of these patterns into hardware. To our knowledge, PERG is the first pattern matching hardware targeting viruses, as well as the first among network intrusion detection systems (NIDS), which are similar in nature to PERG, to implement Bloomier filters. This makes guarding against false positives faster than traditional Bloom filters because verification requires checking against one pattern instead of several patterns. Using the ClamAV antivirus database, PERG fits 80,282 patterns containing over 8,224,848 characters into one modest FPGA chip with a small (4 MB) off-chip memory. The architecture achieves roughly 26x improved density (characters per memory bit) compared to the next-best NIDS pattern-matching engine which fits only 1/250th the characters. With an estimated throughput of about 200MB/s, PERG keeps up with most network or disk interfaces.
{"title":"PERG: A scalable pattern-matching accelerator","authors":"J. Ho, G. Lemieux","doi":"10.1109/MNRC.2008.4683370","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683370","url":null,"abstract":"PERG is an FPGA application for accelerating detection of computer virus signatures (patterns). A pattern consists of a sequence of one or more segments separated by gaps of fixed lengths. PERG preprocesses a database of these patterns into hardware. To our knowledge, PERG is the first pattern matching hardware targeting viruses, as well as the first among network intrusion detection systems (NIDS), which are similar in nature to PERG, to implement Bloomier filters. This makes guarding against false positives faster than traditional Bloom filters because verification requires checking against one pattern instead of several patterns. Using the ClamAV antivirus database, PERG fits 80,282 patterns containing over 8,224,848 characters into one modest FPGA chip with a small (4 MB) off-chip memory. The architecture achieves roughly 26x improved density (characters per memory bit) compared to the next-best NIDS pattern-matching engine which fits only 1/250th the characters. With an estimated throughput of about 200MB/s, PERG keeps up with most network or disk interfaces.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121468562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683415
G. Wijeweera, C. Shafai, A. Rajapakse
This paper describes a new type of miniature electric field sensor that can be used to measure power system voltages remotely. The ability to measure both ac and dc voltage is a significant advantage of this sensor in comparison to other sensors, which can only measure either ac or dc voltage. Micromachining technology was used to fabricate the sensor. The sensing area of this sensor is only 1 mm2 and it requires only 75 mV and 70 muW to drive its shutter. The use of a miniature sensor also helps to measure local electric field accurately since the field distortion caused by the sensor is minimum.
{"title":"Measuring power system voltage remotely using micromachined electric field sensor","authors":"G. Wijeweera, C. Shafai, A. Rajapakse","doi":"10.1109/MNRC.2008.4683415","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683415","url":null,"abstract":"This paper describes a new type of miniature electric field sensor that can be used to measure power system voltages remotely. The ability to measure both ac and dc voltage is a significant advantage of this sensor in comparison to other sensors, which can only measure either ac or dc voltage. Micromachining technology was used to fabricate the sensor. The sensing area of this sensor is only 1 mm2 and it requires only 75 mV and 70 muW to drive its shutter. The use of a miniature sensor also helps to measure local electric field accurately since the field distortion caused by the sensor is minimum.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129117503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683381
R. Griffin, H. Le, D.T. Jack, N. G. Tarr
A custom integrated circuit (ldquoalphaRAMrdquo) capable of detecting the alpha particles emitted in the decay of radon and its progeny has been designed, fabricated and successfully tested. The alphaRAM has been incorporated in a complete radon monitor using electrostatic concentration of radon progeny. The monitor can detect hazardous levels of radon within hours.
{"title":"αRAM: An α particle detecting MOS IC for radon monitoring","authors":"R. Griffin, H. Le, D.T. Jack, N. G. Tarr","doi":"10.1109/MNRC.2008.4683381","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683381","url":null,"abstract":"A custom integrated circuit (ldquoalphaRAMrdquo) capable of detecting the alpha particles emitted in the decay of radon and its progeny has been designed, fabricated and successfully tested. The alphaRAM has been incorporated in a complete radon monitor using electrostatic concentration of radon progeny. The monitor can detect hazardous levels of radon within hours.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124812500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-11-21DOI: 10.1109/MNRC.2008.4683398
M. Ibrahim, Y. H. Ghalab, Wael Badawy
This paper presents a 3D model for a differential electric-field sensitive field effect transistor (DeFET), which is a new CMOS electric-field sensor. The DeFET is used to detect very small partials especially for environmental purposes. This paper also describes the DeFETpsilas theory of operation in addition to simulation results that confirm the DeFETpsilas theory of operation.
{"title":"Toward a 3D model of Differential Electric-Field Sensitive Field Effect Transistor (DeFET)","authors":"M. Ibrahim, Y. H. Ghalab, Wael Badawy","doi":"10.1109/MNRC.2008.4683398","DOIUrl":"https://doi.org/10.1109/MNRC.2008.4683398","url":null,"abstract":"This paper presents a 3D model for a differential electric-field sensitive field effect transistor (DeFET), which is a new CMOS electric-field sensor. The DeFET is used to detect very small partials especially for environmental purposes. This paper also describes the DeFETpsilas theory of operation in addition to simulation results that confirm the DeFETpsilas theory of operation.","PeriodicalId":247684,"journal":{"name":"2008 1st Microsystems and Nanoelectronics Research Conference","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125476302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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