Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773190
M. Kondo, H. Onodera, K. Tamaru
A statistical method applicable to MOSFET compact models for circuit simulation is proposed. A salient feature of the method is that correlation between device parameters is formulated by independent physical parameters which dominate MOSFET characteristics. The key idea is the introduction of an intermediate model. With the use of the intermediate model, physical parameter fluctuations are systematically mapped into the parameters of many device models. As the device parameters are expressed as functions of the independent physical parameters, the worst-case parameters can be accurately derived from the statistical model. The efficiency of the proposed method is shown with experimental results from a 0.3 /spl mu/m CMOS processing technology.
提出了一种适用于MOSFET紧凑模型电路仿真的统计方法。该方法的一个显著特点是，器件参数之间的相关性由支配MOSFET特性的独立物理参数表示。关键思想是引入一个中间模型。通过使用中间模型，物理参数波动被系统地映射到许多器件模型的参数中。由于器件参数表示为独立物理参数的函数，因此可以从统计模型中准确地推导出最坏情况参数。在0.3 /spl μ m CMOS加工工艺上的实验结果表明了该方法的有效性。
{"title":"A systematic and physical application of multivariate statistics to MOSFET I-V models","authors":"M. Kondo, H. Onodera, K. Tamaru","doi":"10.1109/IWSTM.1999.773190","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773190","url":null,"abstract":"A statistical method applicable to MOSFET compact models for circuit simulation is proposed. A salient feature of the method is that correlation between device parameters is formulated by independent physical parameters which dominate MOSFET characteristics. The key idea is the introduction of an intermediate model. With the use of the intermediate model, physical parameter fluctuations are systematically mapped into the parameters of many device models. As the device parameters are expressed as functions of the independent physical parameters, the worst-case parameters can be accurately derived from the statistical model. The efficiency of the proposed method is shown with experimental results from a 0.3 /spl mu/m CMOS processing technology.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116057817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773192
M. Redford, A. J. Walton, D. Sprevak, R. S. Ferguson
Experimental design together with the response surface methodology (RSM) are important tools that can be employed to help optimise IC processes (Walton et al, 1997). This paper presents a method of fitting a response surface to experimental data when there are one or more data points that are poorly fitted by conventional polynomial models. The method is based on first fitting the data with a polynomial model and using this to calculate a worksheet for the combinations of control factors that were used in the original experiment. The actual experimental conditions for the poorly fitting points are then substituted into this worksheet and a covariance fit used to fit the data. The resulting surface follows the general trend while also fitting measurement points where there is confidence that there is no significant experimental error.
{"title":"Application of covariance based models to fit response surfaces to experimental data","authors":"M. Redford, A. J. Walton, D. Sprevak, R. S. Ferguson","doi":"10.1109/IWSTM.1999.773192","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773192","url":null,"abstract":"Experimental design together with the response surface methodology (RSM) are important tools that can be employed to help optimise IC processes (Walton et al, 1997). This paper presents a method of fitting a response surface to experimental data when there are one or more data points that are poorly fitted by conventional polynomial models. The method is based on first fitting the data with a polynomial model and using this to calculate a worksheet for the combinations of control factors that were used in the original experiment. The actual experimental conditions for the poorly fitting points are then substituted into this worksheet and a covariance fit used to fit the data. The resulting surface follows the general trend while also fitting measurement points where there is confidence that there is no significant experimental error.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124687494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773196
T. Miwa, T. Noda, T. Akiyama, S. Sugimoto
Yield and device characteristics in VLSI become more sensitive to process variations with finer patterns and enlargement of wafer size. Thus, process integration should take account of the inter- and intra-wafer process variations for elimination of yield loss. However, it is difficult to perform experiments which cover possible process variations because of cost and time. In this paper, we describe a new method for calculating a process margin for processes such as etching and deposition with consideration of process variations using the Monte Carlo method.
{"title":"A new method for calculating one-dimensional process margin in consideration of process variations","authors":"T. Miwa, T. Noda, T. Akiyama, S. Sugimoto","doi":"10.1109/IWSTM.1999.773196","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773196","url":null,"abstract":"Yield and device characteristics in VLSI become more sensitive to process variations with finer patterns and enlargement of wafer size. Thus, process integration should take account of the inter- and intra-wafer process variations for elimination of yield loss. However, it is difficult to perform experiments which cover possible process variations because of cost and time. In this paper, we describe a new method for calculating a process margin for processes such as etching and deposition with consideration of process variations using the Monte Carlo method.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125338020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773193
Taber Smith, Duane Boning, Simon Fang, Greg Shinn, Jeny Stefani
This work reconsiders within-wafer nonuniformity (WIWNU) metrics for semiconductor processes. Simulations of typical chemical-mechanical polishing (CMP) scenarios are used to demonstrate that these metrics may vary with the pre-process thickness profile, the removal rate characteristics, and processing time. These metrics are compared and contrasted. Some of these metrics are shown to be biased with processing time, while others are shown to be insensitive to improvements in WIWNU. Finally, experimental data is compared with these simulations. It is suggested that multiple metrics may be necessary to determine the actual characteristics of a process.
{"title":"A study of within-wafer non-uniformity metrics","authors":"Taber Smith, Duane Boning, Simon Fang, Greg Shinn, Jeny Stefani","doi":"10.1109/IWSTM.1999.773193","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773193","url":null,"abstract":"This work reconsiders within-wafer nonuniformity (WIWNU) metrics for semiconductor processes. Simulations of typical chemical-mechanical polishing (CMP) scenarios are used to demonstrate that these metrics may vary with the pre-process thickness profile, the removal rate characteristics, and processing time. These metrics are compared and contrasted. Some of these metrics are shown to be biased with processing time, while others are shown to be insensitive to improvements in WIWNU. Finally, experimental data is compared with these simulations. It is suggested that multiple metrics may be necessary to determine the actual characteristics of a process.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125592677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773191
H. Kunitomo, H. Sato, K. Tsuneno, R. Ikematsu, H. Masuda
An industrial statistical worst case modeling process for 0.2 /spl mu/m CMOS is presented. It is based on new TCAD-prototyping with efficient correlation analysis for CMOS performance goals under process variability. Since the manufacturing process undergoes ongoing improvement, well-calibrated TCAD is primary tool to construct realistic performance corner models. A robust TCAD calibration method is one of the keys to achieving accurate prediction. Statistically least conservative "worst case" conditions are newly identified, which state that 99.7% of device performance is contained between the FF (fast fast) and SS (slow slow) worst corners. This reduces the design guardband by 10% compared with conventional worst case approaches.
{"title":"TCAD-prototyping with new accurate worst-case definition for a 0.2 micron CMOS-ASIC process","authors":"H. Kunitomo, H. Sato, K. Tsuneno, R. Ikematsu, H. Masuda","doi":"10.1109/IWSTM.1999.773191","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773191","url":null,"abstract":"An industrial statistical worst case modeling process for 0.2 /spl mu/m CMOS is presented. It is based on new TCAD-prototyping with efficient correlation analysis for CMOS performance goals under process variability. Since the manufacturing process undergoes ongoing improvement, well-calibrated TCAD is primary tool to construct realistic performance corner models. A robust TCAD calibration method is one of the keys to achieving accurate prediction. Statistically least conservative \"worst case\" conditions are newly identified, which state that 99.7% of device performance is contained between the FF (fast fast) and SS (slow slow) worst corners. This reduces the design guardband by 10% compared with conventional worst case approaches.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114451731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-12DOI: 10.1109/IWSTM.1999.773182
Y. Nishi
Summary form only given. As we have gone through the era of integrated circuits, more strictly silicon-based CMOS integrated circuits, where integration density has increased from hundreds of transistors on a chip to almost one quarter of a billion transistors on a chip, a way to develop technology itself has come to the point where we must examine any possible new model for research and development. Technology trends which have been well discussed in forums such as consortia in the USA, Japan, Europe, South-east Asian countries are now converging reasonably, with some differences due to the differences of so-called "technology drivers". Common parameters are the minimum geometries, though they have increasingly become more conceptual parameters as opposed to what can be found on a real chip. Obviously, the density of active elements per unit area and the number of interconnect layers are more important parameters for high-density memories and high performance processors, respectively. The purpose of this talk is not to discuss the technology trend itself, but to examine how we have developed technology and how we can possibly continue in the future.
{"title":"IC technology R&D for the next century","authors":"Y. Nishi","doi":"10.1109/IWSTM.1999.773182","DOIUrl":"https://doi.org/10.1109/IWSTM.1999.773182","url":null,"abstract":"Summary form only given. As we have gone through the era of integrated circuits, more strictly silicon-based CMOS integrated circuits, where integration density has increased from hundreds of transistors on a chip to almost one quarter of a billion transistors on a chip, a way to develop technology itself has come to the point where we must examine any possible new model for research and development. Technology trends which have been well discussed in forums such as consortia in the USA, Japan, Europe, South-east Asian countries are now converging reasonably, with some differences due to the differences of so-called \"technology drivers\". Common parameters are the minimum geometries, though they have increasingly become more conceptual parameters as opposed to what can be found on a real chip. Obviously, the density of active elements per unit area and the number of interconnect layers are more important parameters for high-density memories and high performance processors, respectively. The purpose of this talk is not to discuss the technology trend itself, but to examine how we have developed technology and how we can possibly continue in the future.","PeriodicalId":253336,"journal":{"name":"1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131764191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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