Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236114
Zhigang Hao, G. Shi
Capacitive and inductive coupling issues are hard to analyze in general; however, they are critical for signal integrity (SI) analysis in the contemporary integrated circuit technology. This paper presents a sensitivity based computation approach to coupled RLC trees for statistical signal integrity analysis. This technique is intended for use in SI-driven placement and routing.
{"title":"Sensitivity approach to statistical signal integrity analysis of coupled interconnect trees","authors":"Zhigang Hao, G. Shi","doi":"10.1109/MWSCAS.2009.5236114","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236114","url":null,"abstract":"Capacitive and inductive coupling issues are hard to analyze in general; however, they are critical for signal integrity (SI) analysis in the contemporary integrated circuit technology. This paper presents a sensitivity based computation approach to coupled RLC trees for statistical signal integrity analysis. This technique is intended for use in SI-driven placement and routing.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130579571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236013
A. Mvuma, S. Nishimura, T. Hinamoto
This paper investigates tracking characteristics of a complex-coefficient adaptive infinite-impulse response (IIR) notch filter with a gradient-based algorithm. Two cases are investigated, i.e., linear chirp and randomly-varying frequency input complex signals buried in a complex zero-mean white Gaussian noise. First-order real-coefficient difference equations with respect to steady-state instantaneous frequency tracking error are derived. Closed-form expressions for frequency tracking mean square error (MSE) are derived from the difference equations. In addition, closed-form expressions for optimum notch bandwidth coefficient and step size constant are presented. Computer simulations are included to validate the analyses.
{"title":"Complex coefficient adaptive IIR notch filter tracking characteristics","authors":"A. Mvuma, S. Nishimura, T. Hinamoto","doi":"10.1109/MWSCAS.2009.5236013","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236013","url":null,"abstract":"This paper investigates tracking characteristics of a complex-coefficient adaptive infinite-impulse response (IIR) notch filter with a gradient-based algorithm. Two cases are investigated, i.e., linear chirp and randomly-varying frequency input complex signals buried in a complex zero-mean white Gaussian noise. First-order real-coefficient difference equations with respect to steady-state instantaneous frequency tracking error are derived. Closed-form expressions for frequency tracking mean square error (MSE) are derived from the difference equations. In addition, closed-form expressions for optimum notch bandwidth coefficient and step size constant are presented. Computer simulations are included to validate the analyses.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130800327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236130
J. Zeng, V. Joyner, J. Liao, Shengling Deng, Z. Huang
A 7-channel diversity receiver front-end based on current-summing for broadband free-space optical (FSO) MIMO communication is presented in this paper. This diversity receiver is designed for flip-chip bonding to a custom InGaAs metal-semiconductor-metal (MSM) photodetector array. Each channel employs a low input-impedance current mirror (CM) as the input stage, which allows the implementation of direct current-summing for equal-gain combining (EGC). The summed-up current signal drives a second stage transimpedance amplifier (TIA) to generate the output voltage. Implemented in an 180 nm CMOS technology, a total gain of 58.5 dBΩ, and −3dB bandwidth of 3.7 GHz for 0.25 pF photodiode capacitance is achieved. The power consumption for a single front-end amplifier circuit is 4.2 mW, and for the second stage TIA is 10.3mW with a single 1.8V supply.
{"title":"A 5Gb/s 7-channel current-mode imaging receiver front-end for free-space optical MIMO","authors":"J. Zeng, V. Joyner, J. Liao, Shengling Deng, Z. Huang","doi":"10.1109/MWSCAS.2009.5236130","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236130","url":null,"abstract":"A 7-channel diversity receiver front-end based on current-summing for broadband free-space optical (FSO) MIMO communication is presented in this paper. This diversity receiver is designed for flip-chip bonding to a custom InGaAs metal-semiconductor-metal (MSM) photodetector array. Each channel employs a low input-impedance current mirror (CM) as the input stage, which allows the implementation of direct current-summing for equal-gain combining (EGC). The summed-up current signal drives a second stage transimpedance amplifier (TIA) to generate the output voltage. Implemented in an 180 nm CMOS technology, a total gain of 58.5 dBΩ, and −3dB bandwidth of 3.7 GHz for 0.25 pF photodiode capacitance is achieved. The power consumption for a single front-end amplifier circuit is 4.2 mW, and for the second stage TIA is 10.3mW with a single 1.8V supply.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131137815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236121
S. Ethier, M. Sawan, E. Aboulhamid, M. El-Gamal
A high-voltage electrode driver dedicated to intracortical microstimulation is presented. It is intended to significantly increase the voltage swing in order to maintain constant current stimulation through high-impedance electrode-tissue contacts. Charge pumps are used to generate high-voltage supplies of 8.615 V and −8.348 V from 3.3 V with low ripples (less than 1.6 %) while driving a maximal stimulation current of 200 µA. The negative charge pump architecture has been carefully implemented to suppress latch-up triggering. This high-voltage system is fully integrated and has been implemented with the C08E CMOS 0.8µm 5V/20V process from DALSA Semiconductor. The final output voltage compliance is 14.82 V, allowing constant current stimulation for an implantable in-vivo prototype.
{"title":"A ±9 V fully integrated CMOS electrode driver for high-impedance microstimulation","authors":"S. Ethier, M. Sawan, E. Aboulhamid, M. El-Gamal","doi":"10.1109/MWSCAS.2009.5236121","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236121","url":null,"abstract":"A high-voltage electrode driver dedicated to intracortical microstimulation is presented. It is intended to significantly increase the voltage swing in order to maintain constant current stimulation through high-impedance electrode-tissue contacts. Charge pumps are used to generate high-voltage supplies of 8.615 V and −8.348 V from 3.3 V with low ripples (less than 1.6 %) while driving a maximal stimulation current of 200 µA. The negative charge pump architecture has been carefully implemented to suppress latch-up triggering. This high-voltage system is fully integrated and has been implemented with the C08E CMOS 0.8µm 5V/20V process from DALSA Semiconductor. The final output voltage compliance is 14.82 V, allowing constant current stimulation for an implantable in-vivo prototype.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128812967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235941
O. González-Díaz, M. Linares-Aranda, R. Torres‐Torres
In this work, a systematic analysis of the transmission line models used for high-frequency global interconnection lines is presented. As part of this analysis, two model implementations are carried out using: i) the technology parameters provided by the manufacturer, and ii) the scattering (Sij ) parameters associated with a transmission line. In order to serve as test vehicles, a chain of inverters and several ring oscillators with lines of width wi=2 µm and length li=1.0 to 3.0 mm were implemented using an Austriamiscrosystems 0.35 µm process technology and a power supply of 3.3 V. The simulation results using the equivalent model obtained from S-parameters show the lowest average error when they are compared with post layout simulations. In addition, the obtained results show that the total delay in a chain on three inverters is increased up to 120% and the operation frequency of ring oscillator is reduced up to 58.8% when long interconnections (li=3 mm) are used.
{"title":"High-frequency interconnect modeling for global signal networks","authors":"O. González-Díaz, M. Linares-Aranda, R. Torres‐Torres","doi":"10.1109/MWSCAS.2009.5235941","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235941","url":null,"abstract":"In this work, a systematic analysis of the transmission line models used for high-frequency global interconnection lines is presented. As part of this analysis, two model implementations are carried out using: i) the technology parameters provided by the manufacturer, and ii) the scattering (Sij ) parameters associated with a transmission line. In order to serve as test vehicles, a chain of inverters and several ring oscillators with lines of width wi=2 µm and length li=1.0 to 3.0 mm were implemented using an Austriamiscrosystems 0.35 µm process technology and a power supply of 3.3 V. The simulation results using the equivalent model obtained from S-parameters show the lowest average error when they are compared with post layout simulations. In addition, the obtained results show that the total delay in a chain on three inverters is increased up to 120% and the operation frequency of ring oscillator is reduced up to 58.8% when long interconnections (li=3 mm) are used.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124346227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236081
T. Oshima, Tomomi Takahashi, T. Yamawaki
Novel sampling-timing background calibration for time-interleaved A/D converters has been proposed and verified by simulation. An FIR(Finite Impulse Response)-filter structure exploiting the sampling theorem provides simple but accurate time derivative of converted signal and hence enables reliable estimation and compensation of sampling-timing deviation of each unit ADC assisted by reference converter and LMS(Least Mean Square) algorithm. It has also been confirmed that the sampling-timing calibration can successfully be combined with proposed gain and DC-offset calibrations.
{"title":"Novel sampling timing background calibration for time-interleaved A/D converters","authors":"T. Oshima, Tomomi Takahashi, T. Yamawaki","doi":"10.1109/MWSCAS.2009.5236081","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236081","url":null,"abstract":"Novel sampling-timing background calibration for time-interleaved A/D converters has been proposed and verified by simulation. An FIR(Finite Impulse Response)-filter structure exploiting the sampling theorem provides simple but accurate time derivative of converted signal and hence enables reliable estimation and compensation of sampling-timing deviation of each unit ADC assisted by reference converter and LMS(Least Mean Square) algorithm. It has also been confirmed that the sampling-timing calibration can successfully be combined with proposed gain and DC-offset calibrations.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125469405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236090
N. E. C. Rodriguez, Jose Ivan Guevara Juarez, Rodrigo Savage, Marcial Roberto Leyva Fernandez
The development of this project has the goal of controlling an android robot that has 17 digital servomotors; the position of each of the servomotors is controlled by pulse width modulation. The android also has a distance sensor that allows the android to turn around when encountered with an object that obstructs its way. To implement the control of the android Max II Micro board card from Altera Company is used.. This board is equipped with an Altera MAX® II EPM2210F324C3 CPLD (Complex Programmable Logic Device).
该项目的开发目标是控制一个拥有17个数字伺服电机的机器人;每个伺服电机的位置由脉宽调制控制。这个机器人还有一个距离传感器，当遇到障碍物时，它可以转身。为了实现对android Max II的控制，使用了Altera公司的微板卡。该板配备Altera MAX®II EPM2210F324C3 CPLD(复杂可编程逻辑器件)。
{"title":"Design and implementation of an android","authors":"N. E. C. Rodriguez, Jose Ivan Guevara Juarez, Rodrigo Savage, Marcial Roberto Leyva Fernandez","doi":"10.1109/MWSCAS.2009.5236090","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236090","url":null,"abstract":"The development of this project has the goal of controlling an android robot that has 17 digital servomotors; the position of each of the servomotors is controlled by pulse width modulation. The android also has a distance sensor that allows the android to turn around when encountered with an object that obstructs its way. To implement the control of the android Max II Micro board card from Altera Company is used.. This board is equipped with an Altera MAX® II EPM2210F324C3 CPLD (Complex Programmable Logic Device).","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128303054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236100
Omar R. Avila-Lopez, R. Parra-Michel, F. Sandoval-Ibarra, M. Aguirre-Hernandez
The design and implementation of digital circuitry for building a 900MHz passive tag in a standard 0.5µm CMOS technology is presented. The digital circuitry (hereafter called Digital Section, DS) including a voltage-controlled oscillator (VCO) satisfies the baseband requirements of ISO/IEC18000-6 type A standard. To verify the DS's functionality, a basic Tag-Reader was designed in order to apply test sequences. Power consumption, maximum operation frequency, and area utilization analyses were done using Synopsys' Design Compiler. The obtained results show that the proposed architecture fulfils the requirements stated for the implementation.
{"title":"Design and implementation of the baseband section for a 900MHz passive tag in a 0.5µm CMOS process","authors":"Omar R. Avila-Lopez, R. Parra-Michel, F. Sandoval-Ibarra, M. Aguirre-Hernandez","doi":"10.1109/MWSCAS.2009.5236100","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236100","url":null,"abstract":"The design and implementation of digital circuitry for building a 900MHz passive tag in a standard 0.5µm CMOS technology is presented. The digital circuitry (hereafter called Digital Section, DS) including a voltage-controlled oscillator (VCO) satisfies the baseband requirements of ISO/IEC18000-6 type A standard. To verify the DS's functionality, a basic Tag-Reader was designed in order to apply test sequences. Power consumption, maximum operation frequency, and area utilization analyses were done using Synopsys' Design Compiler. The obtained results show that the proposed architecture fulfils the requirements stated for the implementation.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126464330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235920
H. Patangia, D. Gregory
The paper extends previous work on a novel multilevel PWM strategy to design and implement an optimal inverter for a stand-alone PV application. This modulation strategy produces a much higher fundamental output compared to conventional SPWM without any pulse dropping. Phase-shifted carriers have been used to produce a harmonically superior SPWM signal. A higher fundamental coupled with harmonic elimination through phase shifted carriers reduces THD and improves conversion efficiency. The simulation results have been validated through an experimental prototype.
{"title":"A class of optimal multilevel inverters based on sectionalized PWM (S-PWM) modulation strategy","authors":"H. Patangia, D. Gregory","doi":"10.1109/MWSCAS.2009.5235920","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235920","url":null,"abstract":"The paper extends previous work on a novel multilevel PWM strategy to design and implement an optimal inverter for a stand-alone PV application. This modulation strategy produces a much higher fundamental output compared to conventional SPWM without any pulse dropping. Phase-shifted carriers have been used to produce a harmonically superior SPWM signal. A higher fundamental coupled with harmonic elimination through phase shifted carriers reduces THD and improves conversion efficiency. The simulation results have been validated through an experimental prototype.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127055028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235999
Jing Li, Chunyan Wang
In this paper, a procedure of edge detection for a high dynamic range image with damaged edge information is proposed. This procedure is based on a scheme of multiple filtering processes which does not include any segmentation of the image. Three different filtering processes are designed to generate three gradient maps, in each of which gradients are calculated and modulated by using a specific filter. The enhanced gradients, i.e. those modulated correctly, are identified in each of the three gradient maps by using a selection algorithm. They are taken to generate a complete edge map. This procedure allows varieties of edge gradient enhancements applied in the same image by employing a set of simple filters without segmentation. The effectiveness of the detection process has been confirmed by simulations.
{"title":"Multiple-filtering process and its application in edge detection","authors":"Jing Li, Chunyan Wang","doi":"10.1109/MWSCAS.2009.5235999","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235999","url":null,"abstract":"In this paper, a procedure of edge detection for a high dynamic range image with damaged edge information is proposed. This procedure is based on a scheme of multiple filtering processes which does not include any segmentation of the image. Three different filtering processes are designed to generate three gradient maps, in each of which gradients are calculated and modulated by using a specific filter. The enhanced gradients, i.e. those modulated correctly, are identified in each of the three gradient maps by using a selection algorithm. They are taken to generate a complete edge map. This procedure allows varieties of edge gradient enhancements applied in the same image by employing a set of simple filters without segmentation. The effectiveness of the detection process has been confirmed by simulations.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127069180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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