Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236038
Jin-Hua Hong, Wei-Chung Wu
In this paper, we propose an elliptic curve cryptographic (ECC) architecture for a lower hardware resource. In our work, the different paths of encryption and decryption could be chosen, and the elliptic curve (EC) is based on GF (2163). The EC scalar multiplication is a main operation module that includes add, Montgomery multiplier and inverse in ECC architecture. All modules are organized in a hierarchical structure according to their complexity. In the hardware implementations using a 0.18µ m TSMC cell library, a 69 K gate count is possessed, and the maximum speed is 181 MHz. The EC multiplication time is from 1.26 ms to 2.52 ms. The private key k is a 163-bit random number. If the private key k is chosen to be a small one, the EC multiplication time would be faster.
{"title":"The design of high performance elliptic curve cryptographic","authors":"Jin-Hua Hong, Wei-Chung Wu","doi":"10.1109/MWSCAS.2009.5236038","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236038","url":null,"abstract":"In this paper, we propose an elliptic curve cryptographic (ECC) architecture for a lower hardware resource. In our work, the different paths of encryption and decryption could be chosen, and the elliptic curve (EC) is based on GF (2163). The EC scalar multiplication is a main operation module that includes add, Montgomery multiplier and inverse in ECC architecture. All modules are organized in a hierarchical structure according to their complexity. In the hardware implementations using a 0.18µ m TSMC cell library, a 69 K gate count is possessed, and the maximum speed is 181 MHz. The EC multiplication time is from 1.26 ms to 2.52 ms. The private key k is a 163-bit random number. If the private key k is chosen to be a small one, the EC multiplication time would be faster.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124099742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235987
Israel Olguin Carbajal, Enrique Cisneros Sedano, Blanca Alicia Rico Jimenez
This work depicts the development of an electrical energy distribution systems protection microprocessor based digital relay, commercialization viable, first in its kind in Mexico. It is an overcurrent relay with independent protection elements such as ground, phases, negative sequence, low frequency protection, recloser, directional elements, fault locator, oscilography and other auxiliary elements that constitute a first level protection system achieved by Mexican engineers.
{"title":"An electric energy distribution systems protection microprocessor based relay","authors":"Israel Olguin Carbajal, Enrique Cisneros Sedano, Blanca Alicia Rico Jimenez","doi":"10.1109/MWSCAS.2009.5235987","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235987","url":null,"abstract":"This work depicts the development of an electrical energy distribution systems protection microprocessor based digital relay, commercialization viable, first in its kind in Mexico. It is an overcurrent relay with independent protection elements such as ground, phases, negative sequence, low frequency protection, recloser, directional elements, fault locator, oscilography and other auxiliary elements that constitute a first level protection system achieved by Mexican engineers.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126757943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236100
Omar R. Avila-Lopez, R. Parra-Michel, F. Sandoval-Ibarra, M. Aguirre-Hernandez
The design and implementation of digital circuitry for building a 900MHz passive tag in a standard 0.5µm CMOS technology is presented. The digital circuitry (hereafter called Digital Section, DS) including a voltage-controlled oscillator (VCO) satisfies the baseband requirements of ISO/IEC18000-6 type A standard. To verify the DS's functionality, a basic Tag-Reader was designed in order to apply test sequences. Power consumption, maximum operation frequency, and area utilization analyses were done using Synopsys' Design Compiler. The obtained results show that the proposed architecture fulfils the requirements stated for the implementation.
{"title":"Design and implementation of the baseband section for a 900MHz passive tag in a 0.5µm CMOS process","authors":"Omar R. Avila-Lopez, R. Parra-Michel, F. Sandoval-Ibarra, M. Aguirre-Hernandez","doi":"10.1109/MWSCAS.2009.5236100","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236100","url":null,"abstract":"The design and implementation of digital circuitry for building a 900MHz passive tag in a standard 0.5µm CMOS technology is presented. The digital circuitry (hereafter called Digital Section, DS) including a voltage-controlled oscillator (VCO) satisfies the baseband requirements of ISO/IEC18000-6 type A standard. To verify the DS's functionality, a basic Tag-Reader was designed in order to apply test sequences. Power consumption, maximum operation frequency, and area utilization analyses were done using Synopsys' Design Compiler. The obtained results show that the proposed architecture fulfils the requirements stated for the implementation.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126464330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235941
O. González-Díaz, M. Linares-Aranda, R. Torres‐Torres
In this work, a systematic analysis of the transmission line models used for high-frequency global interconnection lines is presented. As part of this analysis, two model implementations are carried out using: i) the technology parameters provided by the manufacturer, and ii) the scattering (Sij ) parameters associated with a transmission line. In order to serve as test vehicles, a chain of inverters and several ring oscillators with lines of width wi=2 µm and length li=1.0 to 3.0 mm were implemented using an Austriamiscrosystems 0.35 µm process technology and a power supply of 3.3 V. The simulation results using the equivalent model obtained from S-parameters show the lowest average error when they are compared with post layout simulations. In addition, the obtained results show that the total delay in a chain on three inverters is increased up to 120% and the operation frequency of ring oscillator is reduced up to 58.8% when long interconnections (li=3 mm) are used.
{"title":"High-frequency interconnect modeling for global signal networks","authors":"O. González-Díaz, M. Linares-Aranda, R. Torres‐Torres","doi":"10.1109/MWSCAS.2009.5235941","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235941","url":null,"abstract":"In this work, a systematic analysis of the transmission line models used for high-frequency global interconnection lines is presented. As part of this analysis, two model implementations are carried out using: i) the technology parameters provided by the manufacturer, and ii) the scattering (Sij ) parameters associated with a transmission line. In order to serve as test vehicles, a chain of inverters and several ring oscillators with lines of width wi=2 µm and length li=1.0 to 3.0 mm were implemented using an Austriamiscrosystems 0.35 µm process technology and a power supply of 3.3 V. The simulation results using the equivalent model obtained from S-parameters show the lowest average error when they are compared with post layout simulations. In addition, the obtained results show that the total delay in a chain on three inverters is increased up to 120% and the operation frequency of ring oscillator is reduced up to 58.8% when long interconnections (li=3 mm) are used.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124346227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236143
E. López-Delgadillo, J. A. Díaz-Méndez, M. A. Garcia-Andrade, M. Magaña, F. Maloberti
A system for self tuning of on-die terminators in current mode off-chip signaling is presented. The proposed method is based on an algorithm that uses the sign of the impedance matching error and the sign of the coupling branch current to perform the self tuning operation. The circuit implementation of the system is described and computer simulations at the transistor level are presented for process, temperature and load impedance variations.
{"title":"A self tuning system for on-die terminators in current mode off-chip signaling","authors":"E. López-Delgadillo, J. A. Díaz-Méndez, M. A. Garcia-Andrade, M. Magaña, F. Maloberti","doi":"10.1109/MWSCAS.2009.5236143","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236143","url":null,"abstract":"A system for self tuning of on-die terminators in current mode off-chip signaling is presented. The proposed method is based on an algorithm that uses the sign of the impedance matching error and the sign of the coupling branch current to perform the self tuning operation. The circuit implementation of the system is described and computer simulations at the transistor level are presented for process, temperature and load impedance variations.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236077
P. Su, H. Chiueh
This paper presents the design and implementation of a low power sigma-delta modulator (SDM) with a standard 0.18-µm CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational trans-conductance amplifier(OTA). Using a chain of Integrators with weighted feed-forward summation (CIFF) structure and optimized single-stage class-A OTA with positive feedback to minimize the power consumption, the second-order SDM achieves a SNR of 64dB that be able to process the signal form DC to 16 KHz. The power consumption is only 18.1 uW from a 1-V supply.
{"title":"The design of low-power CIFF structure second-order sigma-delta modulator","authors":"P. Su, H. Chiueh","doi":"10.1109/MWSCAS.2009.5236077","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236077","url":null,"abstract":"This paper presents the design and implementation of a low power sigma-delta modulator (SDM) with a standard 0.18-µm CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational trans-conductance amplifier(OTA). Using a chain of Integrators with weighted feed-forward summation (CIFF) structure and optimized single-stage class-A OTA with positive feedback to minimize the power consumption, the second-order SDM achieves a SNR of 64dB that be able to process the signal form DC to 16 KHz. The power consumption is only 18.1 uW from a 1-V supply.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127717089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236121
S. Ethier, M. Sawan, E. Aboulhamid, M. El-Gamal
A high-voltage electrode driver dedicated to intracortical microstimulation is presented. It is intended to significantly increase the voltage swing in order to maintain constant current stimulation through high-impedance electrode-tissue contacts. Charge pumps are used to generate high-voltage supplies of 8.615 V and −8.348 V from 3.3 V with low ripples (less than 1.6 %) while driving a maximal stimulation current of 200 µA. The negative charge pump architecture has been carefully implemented to suppress latch-up triggering. This high-voltage system is fully integrated and has been implemented with the C08E CMOS 0.8µm 5V/20V process from DALSA Semiconductor. The final output voltage compliance is 14.82 V, allowing constant current stimulation for an implantable in-vivo prototype.
{"title":"A ±9 V fully integrated CMOS electrode driver for high-impedance microstimulation","authors":"S. Ethier, M. Sawan, E. Aboulhamid, M. El-Gamal","doi":"10.1109/MWSCAS.2009.5236121","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236121","url":null,"abstract":"A high-voltage electrode driver dedicated to intracortical microstimulation is presented. It is intended to significantly increase the voltage swing in order to maintain constant current stimulation through high-impedance electrode-tissue contacts. Charge pumps are used to generate high-voltage supplies of 8.615 V and −8.348 V from 3.3 V with low ripples (less than 1.6 %) while driving a maximal stimulation current of 200 µA. The negative charge pump architecture has been carefully implemented to suppress latch-up triggering. This high-voltage system is fully integrated and has been implemented with the C08E CMOS 0.8µm 5V/20V process from DALSA Semiconductor. The final output voltage compliance is 14.82 V, allowing constant current stimulation for an implantable in-vivo prototype.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128812967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5236013
A. Mvuma, S. Nishimura, T. Hinamoto
This paper investigates tracking characteristics of a complex-coefficient adaptive infinite-impulse response (IIR) notch filter with a gradient-based algorithm. Two cases are investigated, i.e., linear chirp and randomly-varying frequency input complex signals buried in a complex zero-mean white Gaussian noise. First-order real-coefficient difference equations with respect to steady-state instantaneous frequency tracking error are derived. Closed-form expressions for frequency tracking mean square error (MSE) are derived from the difference equations. In addition, closed-form expressions for optimum notch bandwidth coefficient and step size constant are presented. Computer simulations are included to validate the analyses.
{"title":"Complex coefficient adaptive IIR notch filter tracking characteristics","authors":"A. Mvuma, S. Nishimura, T. Hinamoto","doi":"10.1109/MWSCAS.2009.5236013","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5236013","url":null,"abstract":"This paper investigates tracking characteristics of a complex-coefficient adaptive infinite-impulse response (IIR) notch filter with a gradient-based algorithm. Two cases are investigated, i.e., linear chirp and randomly-varying frequency input complex signals buried in a complex zero-mean white Gaussian noise. First-order real-coefficient difference equations with respect to steady-state instantaneous frequency tracking error are derived. Closed-form expressions for frequency tracking mean square error (MSE) are derived from the difference equations. In addition, closed-form expressions for optimum notch bandwidth coefficient and step size constant are presented. Computer simulations are included to validate the analyses.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130800327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235993
J. A. Hernández, F. G. Castañeda, J. Cadenas
Edge detection is an important preprocessing task in artificial vision systems. In this paper the utility of a recently reported CNN template for edge detection was verified over a set of black and white images. These images were obtained applying an threshold procedure to their corresponding associated gray level images. An optimal threshold value for preserving a large number of features from the original gray level input images was used. Combining the threshold and edge detection templates, a procedure to obtain edges on gray level images was implemented.
{"title":"A method for edge detection in gray level images, based on cellular neural networks","authors":"J. A. Hernández, F. G. Castañeda, J. Cadenas","doi":"10.1109/MWSCAS.2009.5235993","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235993","url":null,"abstract":"Edge detection is an important preprocessing task in artificial vision systems. In this paper the utility of a recently reported CNN template for edge detection was verified over a set of black and white images. These images were obtained applying an threshold procedure to their corresponding associated gray level images. An optimal threshold value for preserving a large number of features from the original gray level input images was used. Combining the threshold and edge detection templates, a procedure to obtain edges on gray level images was implemented.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117001523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-15DOI: 10.1109/MWSCAS.2009.5235879
B. Carvajal-Gámez, F. Gallegos-Funes, J. López-Bonilla
When we talk about steganographic algorithms, it is imperative to study the quality of the image hosting and image retrieval, and is also necessary to consider the robustness of the algorithm. This paper presents the experimental results obtained by applying a steganographic algorithm to RGB images. The measures used are qualitative and quantitative related to the multichannel of Human Vision System. When this algorithm is employed we see that the numerical calculations performed by the computer cause errors and alterations in the images chosen, so we applied a scaling factor depending on the number of bits of the image to adjust these errors.
{"title":"Energy adjustment RGB images in steganography applications","authors":"B. Carvajal-Gámez, F. Gallegos-Funes, J. López-Bonilla","doi":"10.1109/MWSCAS.2009.5235879","DOIUrl":"https://doi.org/10.1109/MWSCAS.2009.5235879","url":null,"abstract":"When we talk about steganographic algorithms, it is imperative to study the quality of the image hosting and image retrieval, and is also necessary to consider the robustness of the algorithm. This paper presents the experimental results obtained by applying a steganographic algorithm to RGB images. The measures used are qualitative and quantitative related to the multichannel of Human Vision System. When this algorithm is employed we see that the numerical calculations performed by the computer cause errors and alterations in the images chosen, so we applied a scaling factor depending on the number of bits of the image to adjust these errors.","PeriodicalId":254577,"journal":{"name":"2009 52nd IEEE International Midwest Symposium on Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132384897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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