Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488835
A. Ivanov
The past five decades amount to mind boggling progress in IC design and manufacturing technology. In this period, we have gone from the inception of ICs to now what literally amounts to the integration of systems of systems on chip. Whereas experts debate the continued evolution of ICs according to Moore's law beyond the next decade, the advent of the complex integration of multi-physics systems is just in its infancy and is predicted to grow exponentially in the coming years. Designing and manufacturing complex ICs is of course a feat in itself. Testing and testability has often been taken for granted as a necessary (not to say evil) requirement. But who wants of an IC that cannot be duly tested, to ensure quality and reliability, especially when deployed in life-critical applications? Test technology, along with design technology has had to make enormous and rapid progress over the past half-century. Here, we highlight some of the key elements of IC test technology. We briefly mention some directions and challenges and opportunities for test technology in the near future, especially as multi-physics integrated systems of systems continue to emerge and progress on the volume production curves.
{"title":"From (integrated) circuits to systems of systems on chip in five decades: How did and will (IC) test technology keep up?","authors":"A. Ivanov","doi":"10.1109/MWSCAS.2007.4488835","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488835","url":null,"abstract":"The past five decades amount to mind boggling progress in IC design and manufacturing technology. In this period, we have gone from the inception of ICs to now what literally amounts to the integration of systems of systems on chip. Whereas experts debate the continued evolution of ICs according to Moore's law beyond the next decade, the advent of the complex integration of multi-physics systems is just in its infancy and is predicted to grow exponentially in the coming years. Designing and manufacturing complex ICs is of course a feat in itself. Testing and testability has often been taken for granted as a necessary (not to say evil) requirement. But who wants of an IC that cannot be duly tested, to ensure quality and reliability, especially when deployed in life-critical applications? Test technology, along with design technology has had to make enormous and rapid progress over the past half-century. Here, we highlight some of the key elements of IC test technology. We briefly mention some directions and challenges and opportunities for test technology in the near future, especially as multi-physics integrated systems of systems continue to emerge and progress on the volume production curves.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125854032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488568
E. Ghafar-Zadeh, M. Sawan, M. Hajj-Hassan, M. A. Miled
In this paper, we describe a 0.18 mum CMOS capacitive sensor for microfluidic applications. This sensor features an interface circuit, which is incorporated with a calibration circuitry. We present the design and thereafter simulation and experimental results in the support of discussed issues throughout this paper. The proposed interface circuit offers the advantage of low complexity as well as sub femto Farad resolution.
本文介绍了一种用于微流体应用的0.18 μ m CMOS电容式传感器。该传感器具有接口电路，该接口电路与校准电路相结合。我们给出了设计和随后的仿真和实验结果，以支持本文所讨论的问题。所提出的接口电路具有低复杂度和亚飞法拉分辨率的优点。
{"title":"A CMOS based microfluidic detector: Design, calibration and experimental results","authors":"E. Ghafar-Zadeh, M. Sawan, M. Hajj-Hassan, M. A. Miled","doi":"10.1109/MWSCAS.2007.4488568","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488568","url":null,"abstract":"In this paper, we describe a 0.18 mum CMOS capacitive sensor for microfluidic applications. This sensor features an interface circuit, which is incorporated with a calibration circuitry. We present the design and thereafter simulation and experimental results in the support of discussed issues throughout this paper. The proposed interface circuit offers the advantage of low complexity as well as sub femto Farad resolution.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126399228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488784
Yunsi Fei, Hai Lin, Xuan Guan
Application-specific instruction set processor (ASIP) has emerged as an important design choice for embedded systems. It can achieve both high flexibility offered by the base processor core and high performance and energy-efficiency offered by the dedicated hardware extensions. Although a lot of efforts have been devoted to computation acceleration (e.g., automatic custom instruction identification and synthesis), the limited on-chip data storage elements, including the register file and data cache, have become a potential performance bottleneck. In this paper, we propose a hardware/software cooperative approach to utilize the custom registers for reducing the data traffic between the processor and memory through efficient communications between the base processor core and custom hardware extensions. Our experimental results demonstrate that promising performance improvements can be achieved.
{"title":"A hardware/software cooperative approach for reducing memory traffic in application-specific instruction set processors","authors":"Yunsi Fei, Hai Lin, Xuan Guan","doi":"10.1109/MWSCAS.2007.4488784","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488784","url":null,"abstract":"Application-specific instruction set processor (ASIP) has emerged as an important design choice for embedded systems. It can achieve both high flexibility offered by the base processor core and high performance and energy-efficiency offered by the dedicated hardware extensions. Although a lot of efforts have been devoted to computation acceleration (e.g., automatic custom instruction identification and synthesis), the limited on-chip data storage elements, including the register file and data cache, have become a potential performance bottleneck. In this paper, we propose a hardware/software cooperative approach to utilize the custom registers for reducing the data traffic between the processor and memory through efficient communications between the base processor core and custom hardware extensions. Our experimental results demonstrate that promising performance improvements can be achieved.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121524740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488606
R. Ranganathan, Thomas T. Yang, W. Mikhael
This paper presents a novel realization of the complex block adaptive independent component analysis algorithm. The algorithm optimally updates the real and imaginary components of the weight vector independently. The new implementation is employed for the separation of complex signals with known source distributions, a scenario frequently encountered in practice. Under time-varying channel conditions, the performance of the proposed method is compared with the widely known Complex Fast-ICA. Simulation results show that this new technique exhibits superior performance in time varying channel conditions in terms of convergence speed. In addition, the performance of the proposed method is independent of the processing block length and is achieved without any additional cost in computational complexity.
{"title":"Separation of complex signals with known source distributions in time-varying channels using optimum complex block adaptive ICA","authors":"R. Ranganathan, Thomas T. Yang, W. Mikhael","doi":"10.1109/MWSCAS.2007.4488606","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488606","url":null,"abstract":"This paper presents a novel realization of the complex block adaptive independent component analysis algorithm. The algorithm optimally updates the real and imaginary components of the weight vector independently. The new implementation is employed for the separation of complex signals with known source distributions, a scenario frequently encountered in practice. Under time-varying channel conditions, the performance of the proposed method is compared with the widely known Complex Fast-ICA. Simulation results show that this new technique exhibits superior performance in time varying channel conditions in terms of convergence speed. In addition, the performance of the proposed method is independent of the processing block length and is achieved without any additional cost in computational complexity.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127915745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488819
Y. Kang, J. Draper
Memory latency is a critical issue for conventional high-speed computing platforms, and it is becoming a common problem in embedded and CMP (chip multiprocessing) systems as well. Conventional processors typically adopt caches and a load/store queue (LSQ) to address the processor-to-memory bottleneck. However, the conventional LSQ design, which has a large number of entries, is not appropriate for embedded systems due to its area and power hungry out-of- order speculation. A compact, low-power load/store buffer that also provides significant performance improvement is essential for such systems. In this paper, we propose an area-efficient wideword load/store buffer (WLSB) which supports both WideWord (256-bit) and scalar (32-bit) load/store instructions for a recently fabricated PIM (processing-in-memory) device. Given its small size, the 4 entry WLSB yields a 57.33% load hit rate on SPEC2K benchmarks. This result is 5.72% better as compared to a less area-efficient 32-entry fully associative scalar load/store buffer (SLSB). The WLSB was synthesized in IBM 90 nm technology, and the resulting implementation occupies less than a seventh of a square mm and is projected to run at 1.6 ns cycle time with 15.72 mW of dynamic power dissipation. This paper demonstrates how this very small-entry buffer can affect the load hit rate and quantifies the design trade-offs between wide small-entry and narrow large-entry buffers with respect to size, power, load hit ratio and clock speed. Although this WLSB has been specifically designed to benefit a PIM architecture, it is expected to be useful for other embedded processing platforms and CMPs due to emphasized area/power constraints.
{"title":"Design trade-offs for load/store buffers in embedded processing environments","authors":"Y. Kang, J. Draper","doi":"10.1109/MWSCAS.2007.4488819","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488819","url":null,"abstract":"Memory latency is a critical issue for conventional high-speed computing platforms, and it is becoming a common problem in embedded and CMP (chip multiprocessing) systems as well. Conventional processors typically adopt caches and a load/store queue (LSQ) to address the processor-to-memory bottleneck. However, the conventional LSQ design, which has a large number of entries, is not appropriate for embedded systems due to its area and power hungry out-of- order speculation. A compact, low-power load/store buffer that also provides significant performance improvement is essential for such systems. In this paper, we propose an area-efficient wideword load/store buffer (WLSB) which supports both WideWord (256-bit) and scalar (32-bit) load/store instructions for a recently fabricated PIM (processing-in-memory) device. Given its small size, the 4 entry WLSB yields a 57.33% load hit rate on SPEC2K benchmarks. This result is 5.72% better as compared to a less area-efficient 32-entry fully associative scalar load/store buffer (SLSB). The WLSB was synthesized in IBM 90 nm technology, and the resulting implementation occupies less than a seventh of a square mm and is projected to run at 1.6 ns cycle time with 15.72 mW of dynamic power dissipation. This paper demonstrates how this very small-entry buffer can affect the load hit rate and quantifies the design trade-offs between wide small-entry and narrow large-entry buffers with respect to size, power, load hit ratio and clock speed. Although this WLSB has been specifically designed to benefit a PIM architecture, it is expected to be useful for other embedded processing platforms and CMPs due to emphasized area/power constraints.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129076283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488621
E. Eschenko, M. S. Candidate, K. Entesari
A state of the art 16/17 prescaler using current mode logic (CML) D-Flip Flops, CMOS inverters, and transmission gates for the .18mu TSMC process with a 1.8 V supply voltage is presented. The prescaler consists of a 4/5 synchronous core and a feedback loop which modulates the 4/5 core to produce a division ratio of 16/17. Instead of employing power hungry CML, the feedback circuit takes advantage of low power NOR and AND gates realized in transmission gate logic (TGL) to reduce the power consumption. To the best of our knowledge, this technique has never been used in a high frequency prescaler before. Additionally, this work will serve as a comprehensive description of the numerous considerations of prescaler design including explanation of gate-level design and transistor level optimization. Furthermore, digital circuit output is efficiently buffered with CMOS inverters for rail- to-rail operation, maximizing slew rate which minimizes phase noise. The simulated phase noise is -150 dBc/Hz @ 1 MHz and the input bandwidth is 2 GHz (11 GHz and 13 GHz). The power consumption of the entire prescaler is 18.5 mW. All of the above results were obtained from post-layout simulations. Circuit layout has been completed and sent for fabrication.
{"title":"A low noise 13 GHz power efficient 16/17 prescaler with rail to rail output amplitude","authors":"E. Eschenko, M. S. Candidate, K. Entesari","doi":"10.1109/MWSCAS.2007.4488621","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488621","url":null,"abstract":"A state of the art 16/17 prescaler using current mode logic (CML) D-Flip Flops, CMOS inverters, and transmission gates for the .18mu TSMC process with a 1.8 V supply voltage is presented. The prescaler consists of a 4/5 synchronous core and a feedback loop which modulates the 4/5 core to produce a division ratio of 16/17. Instead of employing power hungry CML, the feedback circuit takes advantage of low power NOR and AND gates realized in transmission gate logic (TGL) to reduce the power consumption. To the best of our knowledge, this technique has never been used in a high frequency prescaler before. Additionally, this work will serve as a comprehensive description of the numerous considerations of prescaler design including explanation of gate-level design and transistor level optimization. Furthermore, digital circuit output is efficiently buffered with CMOS inverters for rail- to-rail operation, maximizing slew rate which minimizes phase noise. The simulated phase noise is -150 dBc/Hz @ 1 MHz and the input bandwidth is 2 GHz (11 GHz and 13 GHz). The power consumption of the entire prescaler is 18.5 mW. All of the above results were obtained from post-layout simulations. Circuit layout has been completed and sent for fabrication.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133650212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488822
N. Beilleau, C. Ouffoue, H. Aboushady
In this paper, we present a systematic technique to design bandpass LC Sigma Delta modulators with sinusoidal feedback DACs. The output resistance of the DAC degrades the quality factor of the LC resonator and the DAC output capacitance modifies its resonance frequency. It is shown that the DAC output resistance should be taken into account while designing the Q enhancement circuit of the integrated LC resonator. The resonance frequency is adjusted by modifiying the parallel capacitor of the LC resonator. Using the proposed method, different sinusoidal 3.256 GHz DACs are designed in a CMOS 0.13 mum process. Simulation results are presented to compare their performances in the context of an undersampled LC SigmaDelta modulator.
{"title":"Sinusoidal RF DACs for undersampled LC bandpass ∑Δ modulabrs","authors":"N. Beilleau, C. Ouffoue, H. Aboushady","doi":"10.1109/MWSCAS.2007.4488822","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488822","url":null,"abstract":"In this paper, we present a systematic technique to design bandpass LC Sigma Delta modulators with sinusoidal feedback DACs. The output resistance of the DAC degrades the quality factor of the LC resonator and the DAC output capacitance modifies its resonance frequency. It is shown that the DAC output resistance should be taken into account while designing the Q enhancement circuit of the integrated LC resonator. The resonance frequency is adjusted by modifiying the parallel capacitor of the LC resonator. Using the proposed method, different sinusoidal 3.256 GHz DACs are designed in a CMOS 0.13 mum process. Simulation results are presented to compare their performances in the context of an undersampled LC SigmaDelta modulator.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130761914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488690
Ramesh Bharadwaj, A. Biswas, J. James, S. Mukhopadhyay
We present an event-driven synchronous programming environment for coordinating and reorganizing sensor networks. More precisely, we present a synchronous programming language uSOL (secure operations language with uncertainty) that has capabilities of handling service invocations asynchronously, provides strong typing to ensure enforcement of information flow and security policies, has constructs for handling uncertainty, and has the ability to deal with failures (both benign and byzantine) of network components.
{"title":"uSOL: A programming language for sensor networks","authors":"Ramesh Bharadwaj, A. Biswas, J. James, S. Mukhopadhyay","doi":"10.1109/MWSCAS.2007.4488690","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488690","url":null,"abstract":"We present an event-driven synchronous programming environment for coordinating and reorganizing sensor networks. More precisely, we present a synchronous programming language uSOL (secure operations language with uncertainty) that has capabilities of handling service invocations asynchronously, provides strong typing to ensure enforcement of information flow and security policies, has constructs for handling uncertainty, and has the ability to deal with failures (both benign and byzantine) of network components.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128470556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488611
C. Shahnaz, W. Zhu, M. Ahmad
In this paper, a robust pitch detection algorithm is proposed for speech signals severely corrupted by a non-stationary noise. Using low-frequency band of noisy speech, an effective noise reduction approach is first formulated for power spectral subtraction to track the time-variation of the non-stationary noise prior to pitch detection. Then, a new normalized circular difference function of the enhanced speech, which almost conquers the constraint of overlapping between the first formant and the pitch, is proposed. Simulation results using the Keele reference database demonstrate a better efficacy of the proposed algorithm relative to some of the existing methods in a practical multi-talker babble noise environment.
{"title":"A robust pitch detection algorithm for speech signals in a practical noisy environment","authors":"C. Shahnaz, W. Zhu, M. Ahmad","doi":"10.1109/MWSCAS.2007.4488611","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488611","url":null,"abstract":"In this paper, a robust pitch detection algorithm is proposed for speech signals severely corrupted by a non-stationary noise. Using low-frequency band of noisy speech, an effective noise reduction approach is first formulated for power spectral subtraction to track the time-variation of the non-stationary noise prior to pitch detection. Then, a new normalized circular difference function of the enhanced speech, which almost conquers the constraint of overlapping between the first formant and the pitch, is proposed. Simulation results using the Keele reference database demonstrate a better efficacy of the proposed algorithm relative to some of the existing methods in a practical multi-talker babble noise environment.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"52 24","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131639237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488702
O. Alonso, R. Casanova, A. Sanuy, A. Arbat, J. Canals, Á. Diéguez, J. Samitier
In this paper a low power transceiver for short-range IR-communications between robots is described. The mm3- sized robots will be deployed in an arena of A4 sheet size with controlled illumination conditions. The transceiver can manage variations of background light from point to point in the arena, interferences induced by other robots and deals with the inter-robot distance, i.e., the amplitude of the signal to be detected.
{"title":"A low power IC to enable optical communications in a robotic swarm","authors":"O. Alonso, R. Casanova, A. Sanuy, A. Arbat, J. Canals, Á. Diéguez, J. Samitier","doi":"10.1109/MWSCAS.2007.4488702","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488702","url":null,"abstract":"In this paper a low power transceiver for short-range IR-communications between robots is described. The mm3- sized robots will be deployed in an arena of A4 sheet size with controlled illumination conditions. The transceiver can manage variations of background light from point to point in the arena, interferences induced by other robots and deals with the inter-robot distance, i.e., the amplitude of the signal to be detected.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134299252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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