Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488589
L. Sugavaneswaran, M. Swamy, Chunyan Wang
A perceptual non-expansive image compression scheme using the nearly-orthogonal wavelets is presented in this paper. The proposed approach differs from the conventional design scheme by incorporating the human visual system characteristics directly in each sub-band of the wavelet decomposed image. The enhancement in the visual quality of the reconstructed image is achieved by using the proposed contrast sensitivity function masking at each decomposition level during wavelet transformation phase in the compression system. The explored biorthogonal nearly coiflet wavelet is used to achieve an improvement in the compression performance for low and medium bit rate applications. Extensive simulations are carried out using the proposed approach and the results compared with those of some of the existing techniques.
{"title":"Masked nearly-orthogonal wavelet-based image compression and its application to medical imaging","authors":"L. Sugavaneswaran, M. Swamy, Chunyan Wang","doi":"10.1109/MWSCAS.2007.4488589","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488589","url":null,"abstract":"A perceptual non-expansive image compression scheme using the nearly-orthogonal wavelets is presented in this paper. The proposed approach differs from the conventional design scheme by incorporating the human visual system characteristics directly in each sub-band of the wavelet decomposed image. The enhancement in the visual quality of the reconstructed image is achieved by using the proposed contrast sensitivity function masking at each decomposition level during wavelet transformation phase in the compression system. The explored biorthogonal nearly coiflet wavelet is used to achieve an improvement in the compression performance for low and medium bit rate applications. Extensive simulations are carried out using the proposed approach and the results compared with those of some of the existing techniques.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125171691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488536
Dean Wheatley, Torsten Lehmann
A low-power and low-noise CMOS OTA-based amplifier which minimises stimulus artefacts (SAs) in electrically evoked compound action potential (ECAP) measurements is presented. The amplifier is to be incorporated into an electrical stimulation epi-retinal vision prothesis ECAP measurement system. The amplifier has four gain settings (50, 60, 70, 80 dB) over a 7.4-9.9 kHz bandwidth, an input-referred noise of 5.6 muVrms (0.1-10 kHz) and consumes only 12.6 muA quiescent current. The amplifier is simulated using a high voltage 0.35 mum CMOS process and demonstrates an excellent tradeoff of key performance measures.
提出了一种低功耗、低噪声的CMOS ota放大器，可最大限度地减少电诱发复合动作电位(ECAP)测量中的刺激伪影(sa)。该放大器将集成到电刺激视网膜外视假体ECAP测量系统中。该放大器具有4种增益设置(50,60,70,80db)，带宽为7.4-9.9 kHz，输入参考噪声为5.6 muVrms (0.1-10 kHz)，静态电流仅为12.6 muA。该放大器使用高压0.35 μ m CMOS工艺进行仿真，并展示了关键性能指标的出色权衡。
{"title":"Electrically evoked compound action potential (ECAP) stimulus-artefact (SA) blanking low-power low-noise CMOS amplifier","authors":"Dean Wheatley, Torsten Lehmann","doi":"10.1109/MWSCAS.2007.4488536","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488536","url":null,"abstract":"A low-power and low-noise CMOS OTA-based amplifier which minimises stimulus artefacts (SAs) in electrically evoked compound action potential (ECAP) measurements is presented. The amplifier is to be incorporated into an electrical stimulation epi-retinal vision prothesis ECAP measurement system. The amplifier has four gain settings (50, 60, 70, 80 dB) over a 7.4-9.9 kHz bandwidth, an input-referred noise of 5.6 muVrms (0.1-10 kHz) and consumes only 12.6 muA quiescent current. The amplifier is simulated using a high voltage 0.35 mum CMOS process and demonstrates an excellent tradeoff of key performance measures.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122511308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488725
B. Mesgarzadeh, M. Hansson, A. Alvandpour
The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.
{"title":"Low-power bufferless resonant clock distribution networks","authors":"B. Mesgarzadeh, M. Hansson, A. Alvandpour","doi":"10.1109/MWSCAS.2007.4488725","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488725","url":null,"abstract":"The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122648053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488759
Cheng Shen, Zhiguo Shi
A novel single-channel digital secure communication scheme based on dual synchronization of chaos in Colpitts circuits is proposed. Two binary messages, modulated by the OOK scheme and mixed together with two chaotic waveforms, serve as the only transmission signal through a single channel. Simulation results show that two messages can be successfully recovered at their respective receivers. The proposed scheme shows tremendous advantages in terms of effective utilization of spectrum resource for multi-user communications and potential applications in secret sharing systems.
{"title":"Single-channel communication scheme based on dual synchronization of chaos","authors":"Cheng Shen, Zhiguo Shi","doi":"10.1109/MWSCAS.2007.4488759","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488759","url":null,"abstract":"A novel single-channel digital secure communication scheme based on dual synchronization of chaos in Colpitts circuits is proposed. Two binary messages, modulated by the OOK scheme and mixed together with two chaotic waveforms, serve as the only transmission signal through a single channel. Simulation results show that two messages can be successfully recovered at their respective receivers. The proposed scheme shows tremendous advantages in terms of effective utilization of spectrum resource for multi-user communications and potential applications in secret sharing systems.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"475 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122741478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488800
A. Al-Mousa, S. Mourad
This paper presents a method to detect delay faults in wave-pipeline high speed arithmetic circuits that are constructed of dual-rail self-reset logic gates with input-disable. For this category of circuits we develop a fault model and show that standard test pattern generation algorithm can be used after using a 9-valued logic set. Also, we demonstrate that as soon as a delay fault occurs at any stage of the pipeline, the fault is eventually manifested at the output of the circuit as if a stuck-at fault existed in the circuit for that wave.
{"title":"Delay faults in dual-rail, self-reset wave-pipelined circuits","authors":"A. Al-Mousa, S. Mourad","doi":"10.1109/MWSCAS.2007.4488800","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488800","url":null,"abstract":"This paper presents a method to detect delay faults in wave-pipeline high speed arithmetic circuits that are constructed of dual-rail self-reset logic gates with input-disable. For this category of circuits we develop a fault model and show that standard test pattern generation algorithm can be used after using a 9-valued logic set. Also, we demonstrate that as soon as a delay fault occurs at any stage of the pipeline, the fault is eventually manifested at the output of the circuit as if a stuck-at fault existed in the circuit for that wave.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131480030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488695
C. Cao, B. Oelmann
Benchmarking is a common way to evaluate the effectiveness of finite state machine (FSM) low-power methodologies. The serious problem in the existing standard benchmarks is that power-related characteristics are not provided, and therefore these benchmarks are not complete for reliable evaluation and comparison of low-power methods and tools. To address this problem, this paper introduces the coefficient of variation, which is very useful for quantitative analysis of power-related features of an FSM, and for indicating the power optimization opportunity of the corresponding circuit. Based on the coefficient of variation, input-sensitivity analysis of the whole standard benchmark set is conducted. It reveals that the benchmark set is input-data dependant, and the set is insufficient for low-power FSM researches due to the limited coverage of power-related characteristics.
{"title":"The analysis of power-related characteristics of FSM benchmarks","authors":"C. Cao, B. Oelmann","doi":"10.1109/MWSCAS.2007.4488695","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488695","url":null,"abstract":"Benchmarking is a common way to evaluate the effectiveness of finite state machine (FSM) low-power methodologies. The serious problem in the existing standard benchmarks is that power-related characteristics are not provided, and therefore these benchmarks are not complete for reliable evaluation and comparison of low-power methods and tools. To address this problem, this paper introduces the coefficient of variation, which is very useful for quantitative analysis of power-related features of an FSM, and for indicating the power optimization opportunity of the corresponding circuit. Based on the coefficient of variation, input-sensitivity analysis of the whole standard benchmark set is conducted. It reveals that the benchmark set is input-data dependant, and the set is insufficient for low-power FSM researches due to the limited coverage of power-related characteristics.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127020924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488767
R. Becker, N. Haandbaek
This paper presents the implementation of an audio codec suitable for 3rd generation mobile telecom standards in a state-of-the-art 65-nm CMOS process. The overall design of the codec together with measurement results of key features are presented. The codec is a mixed-signal design, containing A/D and D/A converters, as well as the digital signal processing blocks needed to support them. Buffers capable of driving low-ohmic loads are also included.
{"title":"A high-quality mixed-signal audio codec in 65-nm CMOS","authors":"R. Becker, N. Haandbaek","doi":"10.1109/MWSCAS.2007.4488767","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488767","url":null,"abstract":"This paper presents the implementation of an audio codec suitable for 3rd generation mobile telecom standards in a state-of-the-art 65-nm CMOS process. The overall design of the codec together with measurement results of key features are presented. The codec is a mixed-signal design, containing A/D and D/A converters, as well as the digital signal processing blocks needed to support them. Buffers capable of driving low-ohmic loads are also included.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133995944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488810
P. Khaled, Jingye Xu, M. Chowdhury
Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual diode-Vth reduced power gating structure is proposed for better reduction of leakage currents, especially for low-power, high-performance portable devices. The proposed technique maintains an intermediate power saving state as well as the conventional power cut-off state. Experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF power saving modes. It has also been demonstrated that the proposed technique significantly reduces ground bounce due to power mode transition.
{"title":"Dual diode-Vth reduced power gating structure for better leakage reduction","authors":"P. Khaled, Jingye Xu, M. Chowdhury","doi":"10.1109/MWSCAS.2007.4488810","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488810","url":null,"abstract":"Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual diode-Vth reduced power gating structure is proposed for better reduction of leakage currents, especially for low-power, high-performance portable devices. The proposed technique maintains an intermediate power saving state as well as the conventional power cut-off state. Experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF power saving modes. It has also been demonstrated that the proposed technique significantly reduces ground bounce due to power mode transition.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"48 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133051603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488640
Chun-Ming Chang
Though the current-mode odd-nth-order operational transconductance amplifier and capacitor (OTA-C) elliptic filter structure with the minimum number of active and passive components was presented recently, yet none of its counterpart, the voltage-mode ones, have been reported. After a new analytical synthesis method, namely, an innovative algebraic decomposition of a complex nth-order transfer function into n simple and feasible equations, the voltage-mode odd-nth-order OTA-C elliptic filter structure with the minimum number of components is proposed in this paper. The Hspice simulation with 0.35 mum process for a voltage-mode third-order OTA-C elliptic low-pass filter, employing only four OTAs and three grounded capacitors, validates not only precise filtering parameters but low sensitivity and low power consumption performances.
{"title":"Analytical synthesis of low-sensitivity voltage-mode odd-nth-order OTA-C elliptic filter structure with the minimum number of components","authors":"Chun-Ming Chang","doi":"10.1109/MWSCAS.2007.4488640","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488640","url":null,"abstract":"Though the current-mode odd-nth-order operational transconductance amplifier and capacitor (OTA-C) elliptic filter structure with the minimum number of active and passive components was presented recently, yet none of its counterpart, the voltage-mode ones, have been reported. After a new analytical synthesis method, namely, an innovative algebraic decomposition of a complex nth-order transfer function into n simple and feasible equations, the voltage-mode odd-nth-order OTA-C elliptic filter structure with the minimum number of components is proposed in this paper. The Hspice simulation with 0.35 mum process for a voltage-mode third-order OTA-C elliptic low-pass filter, employing only four OTAs and three grounded capacitors, validates not only precise filtering parameters but low sensitivity and low power consumption performances.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133378151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488794
Xin Cai, M. Brooke
Due to the single binary bitstream output nature of delta-sigma analog-to-digital converters, a compact serial processor that can perform general purpose computation as well as signal processing for the delta-sigma converter is proposed. The advantages of the architecture are its low area consumption and program flexibility, and suitable for silicon microsensor system-on-a-chip applications. The processor achieves small size partly through use of low cost serial off-chip memory circuits for all non-register storage. In this paper we present the design, performance specifications, and IC layout for such a processor.
{"title":"General purpose serial processor for delta sigma ADC digital filter","authors":"Xin Cai, M. Brooke","doi":"10.1109/MWSCAS.2007.4488794","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488794","url":null,"abstract":"Due to the single binary bitstream output nature of delta-sigma analog-to-digital converters, a compact serial processor that can perform general purpose computation as well as signal processing for the delta-sigma converter is proposed. The advantages of the architecture are its low area consumption and program flexibility, and suitable for silicon microsensor system-on-a-chip applications. The processor achieves small size partly through use of low cost serial off-chip memory circuits for all non-register storage. In this paper we present the design, performance specifications, and IC layout for such a processor.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133539105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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