Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488668
Shi Chen, C. Hsieh, Ke-Horng Chen
This paper proposes a compact size DC-DC buck converter toward on-chip inductors and minimized external components. Multi-phase, high switching frequency and pseudo continuous conduction mode (PCCM) techniques achieve the possibility to implement on-chip inductors. The effective inductance is about 20nH. Due to high switching frequency above 20MHz, it is a challenge to have a highly accurate current sense for high performance of converters. Simulation results demonstrate that the accuracy of high-speed current sensor is about 95%. Besides, mode switch between pulse width modulation (PWM) and pulse frequency modulation (PFM) alleviates the limitation of high-speed current sensor in case of light load condition. Compact size design of converter is an advanced technique as a power module for system-on-chip (SOC) designs.
{"title":"Challenge on compact size DC-DC buck converters with high-speed current sensor and on-chip inductors","authors":"Shi Chen, C. Hsieh, Ke-Horng Chen","doi":"10.1109/MWSCAS.2007.4488668","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488668","url":null,"abstract":"This paper proposes a compact size DC-DC buck converter toward on-chip inductors and minimized external components. Multi-phase, high switching frequency and pseudo continuous conduction mode (PCCM) techniques achieve the possibility to implement on-chip inductors. The effective inductance is about 20nH. Due to high switching frequency above 20MHz, it is a challenge to have a highly accurate current sense for high performance of converters. Simulation results demonstrate that the accuracy of high-speed current sensor is about 95%. Besides, mode switch between pulse width modulation (PWM) and pulse frequency modulation (PFM) alleviates the limitation of high-speed current sensor in case of light load condition. Compact size design of converter is an advanced technique as a power module for system-on-chip (SOC) designs.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122662377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488781
J. Joshi, K. Karandikar, S. Bade, M. Bodke, R. Adyanthaya, B. Ahirwal
Real time image processing (I.P.) systems, involving on board multiprocessor communication, use standard bus based communication. The load on the system to deliver the output towards real time standards call for high speeds , but for data intensive application such as IP algorithms require constant transfer of data between the logic cores. This would need either dedicated connections or additional bus controllers. networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of a bus-based solution. This paper deals with the design and implementation of a multi-core image processing system consisting of different modules. All the cores have been designed targeting real time frame rates. The design has been prototyped on a Virtex II FPGA. The timing results for different video files pertaining to different standards have been presented and processing speeds for standard image sizes have also been given.
实时图像处理(ip)系统采用基于标准总线的通信方式，涉及车载多处理器通信。向实时标准提供输出的系统负载要求高速，但对于数据密集型应用(如IP算法)需要在逻辑核心之间不断传输数据。这将需要专用连接或额外的总线控制器。片上网络(NoC)提供了一种在硅上实现互连的结构化方法，并消除了基于总线的解决方案的局限性。本文介绍了一个由不同模块组成的多核图像处理系统的设计与实现。所有的核心都是针对实时帧率设计的。该设计已在Virtex II FPGA上进行了原型设计。给出了不同标准下不同视频文件的时序结果，并给出了标准图像尺寸下的处理速度。
{"title":"Multi-core Image processing system using Network on Chip interconnect","authors":"J. Joshi, K. Karandikar, S. Bade, M. Bodke, R. Adyanthaya, B. Ahirwal","doi":"10.1109/MWSCAS.2007.4488781","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488781","url":null,"abstract":"Real time image processing (I.P.) systems, involving on board multiprocessor communication, use standard bus based communication. The load on the system to deliver the output towards real time standards call for high speeds , but for data intensive application such as IP algorithms require constant transfer of data between the logic cores. This would need either dedicated connections or additional bus controllers. networks-on-chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of a bus-based solution. This paper deals with the design and implementation of a multi-core image processing system consisting of different modules. All the cores have been designed targeting real time frame rates. The design has been prototyped on a Virtex II FPGA. The timing results for different video files pertaining to different standards have been presented and processing speeds for standard image sizes have also been given.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128427759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488798
B. Mihajlovic, Z. Zilic, K. Radecka
This paper considers the in-system testing of wireless sensor network (WSN) nodes that operate with strict limits on energy and cost, and are prone to malicious interference. We show that while performing testing using software-based self-test (SBST) programs has clear advantages, node energy efficiency can be increased by compressing self-test programs before distributing them over the wireless interface. We demonstrate a node energy savings by using an adaptive test program compression scheme with a small memory footprint based upon the BSTW algorithm in conjunction with Golomb-Rice coding. As well, we assist in providing security during the testing process by offloading cryptographic functions to hardware for a measure of protection against malicious interference during testing.
{"title":"Compression and encryption of self-test programs for wireless sensor network nodes","authors":"B. Mihajlovic, Z. Zilic, K. Radecka","doi":"10.1109/MWSCAS.2007.4488798","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488798","url":null,"abstract":"This paper considers the in-system testing of wireless sensor network (WSN) nodes that operate with strict limits on energy and cost, and are prone to malicious interference. We show that while performing testing using software-based self-test (SBST) programs has clear advantages, node energy efficiency can be increased by compressing self-test programs before distributing them over the wireless interface. We demonstrate a node energy savings by using an adaptive test program compression scheme with a small memory footprint based upon the BSTW algorithm in conjunction with Golomb-Rice coding. As well, we assist in providing security during the testing process by offloading cryptographic functions to hardware for a measure of protection against malicious interference during testing.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128366147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488787
Hwang-Cherng Chow, Chaung-Lin Hsieh
A new charge transfer sense amplifier scheme is proposed for high speed 0.5 V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.
提出了一种适用于高速0.5 V dram的电荷转移感测放大方案。该传感放大器的交叉耦合结构和升压电容的结合使得传感节点之间的电压差最大，并且比现有技术电路的运行速度快40%。
{"title":"A 0.5V high speed DRAM charge transfer sense amplifier","authors":"Hwang-Cherng Chow, Chaung-Lin Hsieh","doi":"10.1109/MWSCAS.2007.4488787","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488787","url":null,"abstract":"A new charge transfer sense amplifier scheme is proposed for high speed 0.5 V DRAMs. The combination of both cross-coupled structure and boost capacitance of the proposed sense amplifier leads to the maximum voltage difference between sense nodes and 40% faster operation than prior art circuits.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129254291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488545
G. Bawa, Uei-Ming Jow, Maysam Ghovanloo
In this paper, a high efficiency full-wave integrated voltage rectifier, implemented in AMI 0.5-mum 3M/2P n-well standard CMOS process, is presented. The rectifier takes advantage of the dynamic voltage control of separated n-well regions, where the main rectifying PMOS elements have been implemented, to eliminate latchup and body effect. In measurements, an AC input sinusoid of 5 V peak at 0.5 MHz yield a 4.36 V DC output across a 1 kOmega load, resulting in a measured power conversion efficiency of 85%.
本文介绍了一种采用AMI 0.5 μ m 3M/2P n阱标准CMOS工艺实现的高效全波集成电压整流器。整流器利用分离的n阱区动态电压控制，其中主要整流PMOS元件已经实现，以消除锁存和体效应。在测量中，交流输入正弦波在0.5 MHz时峰值为5 V，在1 kOmega负载上产生4.36 V的直流输出，导致测量的功率转换效率为85%。
{"title":"A high efficiency full-wave rectifier in standard CMOS Technology","authors":"G. Bawa, Uei-Ming Jow, Maysam Ghovanloo","doi":"10.1109/MWSCAS.2007.4488545","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488545","url":null,"abstract":"In this paper, a high efficiency full-wave integrated voltage rectifier, implemented in AMI 0.5-mum 3M/2P n-well standard CMOS process, is presented. The rectifier takes advantage of the dynamic voltage control of separated n-well regions, where the main rectifying PMOS elements have been implemented, to eliminate latchup and body effect. In measurements, an AC input sinusoid of 5 V peak at 0.5 MHz yield a 4.36 V DC output across a 1 kOmega load, resulting in a measured power conversion efficiency of 85%.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124623870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488713
I. Padilla-Cantoya, J. E. Molinar-Solís, G.O. Ducoudary
A modification of the flipped voltage follower (FVF) that provides efficient Class-AB operation is presented. The modified circuit has the capability to source and sink large output currents and, compared to previous approaches, it is able to maintain the output node at a constant voltage with respect to the input. This is achieved with a very small increase in the power dissipation and very small additional devices. Simulation results of this structure verifying the proposed operation are provided.
{"title":"Class AB low-voltage CMOS Voltage Follower","authors":"I. Padilla-Cantoya, J. E. Molinar-Solís, G.O. Ducoudary","doi":"10.1109/MWSCAS.2007.4488713","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488713","url":null,"abstract":"A modification of the flipped voltage follower (FVF) that provides efficient Class-AB operation is presented. The modified circuit has the capability to source and sink large output currents and, compared to previous approaches, it is able to maintain the output node at a constant voltage with respect to the input. This is achieved with a very small increase in the power dissipation and very small additional devices. Simulation results of this structure verifying the proposed operation are provided.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121657159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488723
Y. Xu, A. Srivastava
In this paper, new energy recovery CMOS XNOR/XOR gates have been proposed. These circuits have been simulated using Cadence/Spectre along with three other XNOR/XOR gates. The results show that the new CMOS XNOR/XOR gates consume 30% less power than in the clocked adiabatic logic (CAL). Experimental results on new energy recovery CMOS XNOR/XOR gates fabricated in standard 0.5 mum n-well CMOS process follow the simulation results.
本文提出了一种新型能量回收CMOS XNOR/XOR门。这些电路已经使用Cadence/Spectre以及其他三个XNOR/XOR门进行了模拟。结果表明，与时钟绝热逻辑(CAL)相比，新型CMOS XNOR/XOR门功耗降低30%。采用标准的0.5 μ m n阱CMOS工艺制作的新型能量回收CMOS XNOR/XOR门的实验结果与仿真结果一致。
{"title":"New energy recovery CMOS XNOR/XOR gates","authors":"Y. Xu, A. Srivastava","doi":"10.1109/MWSCAS.2007.4488723","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488723","url":null,"abstract":"In this paper, new energy recovery CMOS XNOR/XOR gates have been proposed. These circuits have been simulated using Cadence/Spectre along with three other XNOR/XOR gates. The results show that the new CMOS XNOR/XOR gates consume 30% less power than in the clocked adiabatic logic (CAL). Experimental results on new energy recovery CMOS XNOR/XOR gates fabricated in standard 0.5 mum n-well CMOS process follow the simulation results.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124476366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488565
H. Nejati, T. Ragheb, A. Hosseini, Y. Massoud
In this paper, we present a chaotic oscillator structure that generates different chaotic oscillation behaviors depending on the number of excitation pulses as well as the pulse width. The oscillator is a programmable chaotic oscillator that can work in both autonomous mode and non-autonomous mode, which can be used in programmable and low-power applications such as cryptography and communication channel verification.
{"title":"A programmable input-pulse dependent chaotic oscillator","authors":"H. Nejati, T. Ragheb, A. Hosseini, Y. Massoud","doi":"10.1109/MWSCAS.2007.4488565","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488565","url":null,"abstract":"In this paper, we present a chaotic oscillator structure that generates different chaotic oscillation behaviors depending on the number of excitation pulses as well as the pulse width. The oscillator is a programmable chaotic oscillator that can work in both autonomous mode and non-autonomous mode, which can be used in programmable and low-power applications such as cryptography and communication channel verification.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126331225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488715
I. Padilla-Cantoya
A new dual-polarity floating battery with accurate quiescent current control for Class AB output stages is presented. The proposed circuit has the capability to operate at very low voltages, close to the threshold voltage of a transistor. It can also operate at very high voltages with accurate quiescent current control and minimum power dissipation. Simulation results of this structure verifying the described operation are provided.
{"title":"Dual-polarity floating battery for class AB output stages with accurate quiescent current control","authors":"I. Padilla-Cantoya","doi":"10.1109/MWSCAS.2007.4488715","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488715","url":null,"abstract":"A new dual-polarity floating battery with accurate quiescent current control for Class AB output stages is presented. The proposed circuit has the capability to operate at very low voltages, close to the threshold voltage of a transistor. It can also operate at very high voltages with accurate quiescent current control and minimum power dissipation. Simulation results of this structure verifying the described operation are provided.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125494716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488687
Shih-Chih Chen, Ruey-Lue Wang, Cheng-Lung Tsai, Jui-Hao Shang, Chien-Hsuan Liu
This paper presents a full band (3.1 GHz to 10.6 GHz) current-reused low noise amplifier (LNA) for ultra wide band (UWB) system based on the TSMC 0.35 m bipolar silicon-germanium (SiGe) processes. The implemented LNA achieves the gain of 14.3 dB, the noise figure (NF) minimum of 2.5 dB and good input and output matching from 3.1 GHz to 10.6 GHz. The power consumption is only 5.4 mW under a 1.5 supply voltage. By adding a feedback resister in the second stage of the adopted current-reused topology, the gain flatness is less than 0.5 dB in every band group. The circuit occupies an area of 1.33 mm2.
{"title":"A low power, good gain flatness SiGe low noise amplifier for 3.1–10.6GHz ultra wide band radio","authors":"Shih-Chih Chen, Ruey-Lue Wang, Cheng-Lung Tsai, Jui-Hao Shang, Chien-Hsuan Liu","doi":"10.1109/MWSCAS.2007.4488687","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488687","url":null,"abstract":"This paper presents a full band (3.1 GHz to 10.6 GHz) current-reused low noise amplifier (LNA) for ultra wide band (UWB) system based on the TSMC 0.35 m bipolar silicon-germanium (SiGe) processes. The implemented LNA achieves the gain of 14.3 dB, the noise figure (NF) minimum of 2.5 dB and good input and output matching from 3.1 GHz to 10.6 GHz. The power consumption is only 5.4 mW under a 1.5 supply voltage. By adding a feedback resister in the second stage of the adopted current-reused topology, the gain flatness is less than 0.5 dB in every band group. The circuit occupies an area of 1.33 mm2.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128179210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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