Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488755
Hsin-Hsiung Huang, Tung-Fu Chiu, Yu-Cheng Lin, T. Hsieh
In the paper, we provide a timing-driven rectilinear routing tree algorithm which applies top-down partitioning followed by the bottom-up routing tree construction in the presence of the obstacles. The objective is to simultaneously minimize the source-to-terminal delay and the total wirelength. First, a top-down partitioning method is used to divide the chip into four sub-regions according to the position of the source. Then, the terminals in each sub-region are connected by a fast sequential routing tree algorithm. The major steps of the routing algorithm include minimal spanning tree constructing, invalid edges pushing and routing. It shows experimentally that the maximum source-to-terminal delay of the routing tree is improved by 74%. Compared to previous results, total wirelength is significantly reduced by 34.7%.
{"title":"Large-scale timing-driven rectilinear steiner tree construction in presence of obstacles","authors":"Hsin-Hsiung Huang, Tung-Fu Chiu, Yu-Cheng Lin, T. Hsieh","doi":"10.1109/MWSCAS.2007.4488755","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488755","url":null,"abstract":"In the paper, we provide a timing-driven rectilinear routing tree algorithm which applies top-down partitioning followed by the bottom-up routing tree construction in the presence of the obstacles. The objective is to simultaneously minimize the source-to-terminal delay and the total wirelength. First, a top-down partitioning method is used to divide the chip into four sub-regions according to the position of the source. Then, the terminals in each sub-region are connected by a fast sequential routing tree algorithm. The major steps of the routing algorithm include minimal spanning tree constructing, invalid edges pushing and routing. It shows experimentally that the maximum source-to-terminal delay of the routing tree is improved by 74%. Compared to previous results, total wirelength is significantly reduced by 34.7%.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132316025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488836
M. Jamal Deen, M. El-Desouki, H. M. Jafari, S. Asgaran
This paper discusses our efforts in designing different low-power RF transceiver blocks, starting with the LNA and power amplifier (PA). The paper discusses the effect of four different input matching methodologies on the gain of narrow-band LNAs. Measurement results of two LNAs fabricated in a 0.18 mum CMOS technology are also presented. Two ultra-wideband (UWB) LNA designs that aim for low- voltage and low-power operation are also discussed in this paper. The UWB LNAs consume a power of 5.8 mW from a 0.8 V supply voltage, while achieving a maximum gain of 12.5 dB and an input matching better than -10 dB from 2-10 GHz with a NF of 3.5 dB. A fully integrated, 2.4 GHz class-E PA, with a class-F driver stage is also discussed in this work, demonstrating the feasibility of using CMOS class-E PAs for low-transmit power applications. The circuit was fabricated in a standard 0.18 mum CMOS technology with a maximum drain efficiency of 53%. When operating from a 1.2 V supply, the PA delivers an output power of 14.5 mW with a power-added efficiency (PAE) of 51%. The supply voltage can go down to 0.6 V with an output power of 3.5 mW and a PAE of 43%. Finally, the paper also discusses a simple transmitter and receiver front-end, in addition to a single-block simplified, low- power PLL transmitter design.
{"title":"Low-power integrated CMOS RF transceiver circuits for short-range applications","authors":"M. Jamal Deen, M. El-Desouki, H. M. Jafari, S. Asgaran","doi":"10.1109/MWSCAS.2007.4488836","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488836","url":null,"abstract":"This paper discusses our efforts in designing different low-power RF transceiver blocks, starting with the LNA and power amplifier (PA). The paper discusses the effect of four different input matching methodologies on the gain of narrow-band LNAs. Measurement results of two LNAs fabricated in a 0.18 mum CMOS technology are also presented. Two ultra-wideband (UWB) LNA designs that aim for low- voltage and low-power operation are also discussed in this paper. The UWB LNAs consume a power of 5.8 mW from a 0.8 V supply voltage, while achieving a maximum gain of 12.5 dB and an input matching better than -10 dB from 2-10 GHz with a NF of 3.5 dB. A fully integrated, 2.4 GHz class-E PA, with a class-F driver stage is also discussed in this work, demonstrating the feasibility of using CMOS class-E PAs for low-transmit power applications. The circuit was fabricated in a standard 0.18 mum CMOS technology with a maximum drain efficiency of 53%. When operating from a 1.2 V supply, the PA delivers an output power of 14.5 mW with a power-added efficiency (PAE) of 51%. The supply voltage can go down to 0.6 V with an output power of 3.5 mW and a PAE of 43%. Finally, the paper also discusses a simple transmitter and receiver front-end, in addition to a single-block simplified, low- power PLL transmitter design.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130871886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488753
R. Z. Bhatti, M. Denneau, J. Draper
This paper presents a new way to tackle critical bus cycle timing issues related to DDR/DDR2 bus operations using a statistical random sampling technique. The technique allows a pure standard cell based design which is inherently area, power and design time efficient compared to existing solutions proposed in the literature. The proposed design employs a statistical random sampling technique to measure and correct the duty cycle of a clock to produce source synchronous signals and to adjust the phase of the incoming strobe to correctly capture data. The proposed circuits are used to interface Samsung K4T51163QB_D5 DDR2 chips to a massively parallel processing logic ASIC chip, targeted to IBM Cu-08 90 nm technology. The proposed design is a fully digital solution based on standard cell components and does not require any custom designed component. This makes it extremely design time efficient and portable across most ASIC and FPGA technologies.
{"title":"Data strobe timing of DDR2 using a statistical random sampling technique","authors":"R. Z. Bhatti, M. Denneau, J. Draper","doi":"10.1109/MWSCAS.2007.4488753","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488753","url":null,"abstract":"This paper presents a new way to tackle critical bus cycle timing issues related to DDR/DDR2 bus operations using a statistical random sampling technique. The technique allows a pure standard cell based design which is inherently area, power and design time efficient compared to existing solutions proposed in the literature. The proposed design employs a statistical random sampling technique to measure and correct the duty cycle of a clock to produce source synchronous signals and to adjust the phase of the incoming strobe to correctly capture data. The proposed circuits are used to interface Samsung K4T51163QB_D5 DDR2 chips to a massively parallel processing logic ASIC chip, targeted to IBM Cu-08 90 nm technology. The proposed design is a fully digital solution based on standard cell components and does not require any custom designed component. This makes it extremely design time efficient and portable across most ASIC and FPGA technologies.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130922816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488680
Guoji Zhu, A. Opal
Sensitivity analysis is useful in comparing the quality of two different designs. It is also used to evaluate the gradient, Jacobian or Hessian matrices in analog computer aided design. In (Zhu and Opal, 2006) the authors presented a Volterra series based sensitivity analysis of mildly nonlinear circuits in the frequency domain. This sensitivity calculation can be expensive in certain circumstances because of multiple mixing effects (Zhu, 2007). In this paper, we propose the concept of nonlinear transfer matrix (NTM) to improve computational efficiency. Examples show that NTM improves the efficiency of sensitivity analysis of mildly nonlinear circuits, e.g. two orders of magnitude speedup for large circuits.
{"title":"Efficient volterra series based sensitivity analysis of mildly nonlinear circuits","authors":"Guoji Zhu, A. Opal","doi":"10.1109/MWSCAS.2007.4488680","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488680","url":null,"abstract":"Sensitivity analysis is useful in comparing the quality of two different designs. It is also used to evaluate the gradient, Jacobian or Hessian matrices in analog computer aided design. In (Zhu and Opal, 2006) the authors presented a Volterra series based sensitivity analysis of mildly nonlinear circuits in the frequency domain. This sensitivity calculation can be expensive in certain circumstances because of multiple mixing effects (Zhu, 2007). In this paper, we propose the concept of nonlinear transfer matrix (NTM) to improve computational efficiency. Examples show that NTM improves the efficiency of sensitivity analysis of mildly nonlinear circuits, e.g. two orders of magnitude speedup for large circuits.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131004658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488534
Basab Datta, W. Burleson
The increasing significance of thermal issues in modern VLSI motivates the need for a large number of lightweight, robust and power efficient thermal sensors for accurate thermal mapping and management. We propose use of differential ring oscillators (DRO) for thermal sensing, utilizing the temperature dependence of the oscillation frequency. In current starved inverter topology using the 45 nm technology node, they have a resolution of 2degC and a low active power consumption of less than 25 muW which can be reduced further by 60-80% by gating the design. A high threshold design proves to be better in terms of leakage, non-linearity error, overall power consumption as well as sensitivity to power supply variations. The standard deviation in measurement (%) caused by process variations and supply noise is within 3% for low Vt design; it increases to 5% for a high Vt design. In a reduced supply bounce configuration, the measurement error caused due to supply noise can be reduced by 15-60%.
{"title":"Low-power and robust on-chip thermal sensing using differential ring oscillators","authors":"Basab Datta, W. Burleson","doi":"10.1109/MWSCAS.2007.4488534","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488534","url":null,"abstract":"The increasing significance of thermal issues in modern VLSI motivates the need for a large number of lightweight, robust and power efficient thermal sensors for accurate thermal mapping and management. We propose use of differential ring oscillators (DRO) for thermal sensing, utilizing the temperature dependence of the oscillation frequency. In current starved inverter topology using the 45 nm technology node, they have a resolution of 2degC and a low active power consumption of less than 25 muW which can be reduced further by 60-80% by gating the design. A high threshold design proves to be better in terms of leakage, non-linearity error, overall power consumption as well as sensitivity to power supply variations. The standard deviation in measurement (%) caused by process variations and supply noise is within 3% for low Vt design; it increases to 5% for a high Vt design. In a reduced supply bounce configuration, the measurement error caused due to supply noise can be reduced by 15-60%.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126628249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488675
R. Kumar, V. Kursun
Temperature dependent propagation delay characteristics of CMOS circuits will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of standard zero-body-biased circuits in a 32 nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. The enhancement of circuit speed provides new opportunities to lower the energy consumed by active circuits at elevated temperatures. Temperature-adaptive supply and threshold voltage tuning techniques are proposed in this paper to reduce the high temperature active mode energy consumption without degrading the circuit speed. Results indicate that the energy consumption can be lowered by up to 21% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body-bias exponentially reduces the leakage currents as well as the parasitic junction capacitances of the MOSFETs. The temperature-adaptive threshold voltage tuning through reverse body-bias yields an active mode energy reduction by up to 29.8% as compared to the standard zero body-biased circuits at high temperatures.
{"title":"Temperature-adaptive body-bias and supply voltage scaling for enhanced energy efficiency in nano-CMOS circuits","authors":"R. Kumar, V. Kursun","doi":"10.1109/MWSCAS.2007.4488675","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488675","url":null,"abstract":"Temperature dependent propagation delay characteristics of CMOS circuits will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of standard zero-body-biased circuits in a 32 nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. The enhancement of circuit speed provides new opportunities to lower the energy consumed by active circuits at elevated temperatures. Temperature-adaptive supply and threshold voltage tuning techniques are proposed in this paper to reduce the high temperature active mode energy consumption without degrading the circuit speed. Results indicate that the energy consumption can be lowered by up to 21% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body-bias exponentially reduces the leakage currents as well as the parasitic junction capacitances of the MOSFETs. The temperature-adaptive threshold voltage tuning through reverse body-bias yields an active mode energy reduction by up to 29.8% as compared to the standard zero body-biased circuits at high temperatures.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"369 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126707519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488813
Changzhong Chen, M. Nakhla, R. Achar, E. Gad
This paper presents a new technique for the analysis of interconnects characterized by frequency dependent per-unit-length (FD-PUL) parameters. The proposed technique is based on using the idea of integrated congruence transform (ICT) to construct a reduced model in the form of ordinary differential equations (ODEs). The passivity of the reduced model is guaranteed. Numerical results demonstrate the validity of the proposed technique.
{"title":"Model-order reduction of frequency-dependent interconnects based on integrated congruence transform","authors":"Changzhong Chen, M. Nakhla, R. Achar, E. Gad","doi":"10.1109/MWSCAS.2007.4488813","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488813","url":null,"abstract":"This paper presents a new technique for the analysis of interconnects characterized by frequency dependent per-unit-length (FD-PUL) parameters. The proposed technique is based on using the idea of integrated congruence transform (ICT) to construct a reduced model in the form of ordinary differential equations (ODEs). The passivity of the reduced model is guaranteed. Numerical results demonstrate the validity of the proposed technique.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126244983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488585
N. Ekekwe, R. Etienne-Cummings
This paper describes the design of a CMOS automatic gain control chip for use in hearing aids and similar applications. It uses linearized MOS resistive circuit to implement the amplifier variable gain thereby overcoming discrete gain step limitation set by using resistors or capacitors. With input stage fully differential operational transconductance amplifier (OTA) whose current outputs drive a high gain transimpedance amplifier (TIA), noise is minimized. To improve gain and performance, a common mode feedback stage is incorporated within the OTA. The chip has a simulated power consumption of 2.45 mW. At frequency of 20 MHz, the harmonic distortion is -48 dB for a 2 MHz 2 Vpp input voltage. A robust design with a single external control, it is designed in 0.5 mum 2P3M CMOS process.
本文介绍了一种用于助听器和类似应用的CMOS自动增益控制芯片的设计。它采用线性化MOS电阻电路实现放大器可变增益，从而克服了使用电阻或电容设置的离散增益阶跃限制。采用输入级全差分运算跨导放大器(OTA)，其电流输出驱动高增益跨阻放大器(TIA)，可将噪声降至最低。为了提高增益和性能，在OTA中加入了一个公共模式反馈阶段。该芯片的模拟功耗为2.45 mW。在20mhz频率下，当输入电压为2mhz 2vpp时，谐波失真为- 48db。它具有单一外部控制的稳健设计，采用0.5 μ m 2P3M CMOS工艺设计。
{"title":"A robust multi-application automatic gain control chip","authors":"N. Ekekwe, R. Etienne-Cummings","doi":"10.1109/MWSCAS.2007.4488585","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488585","url":null,"abstract":"This paper describes the design of a CMOS automatic gain control chip for use in hearing aids and similar applications. It uses linearized MOS resistive circuit to implement the amplifier variable gain thereby overcoming discrete gain step limitation set by using resistors or capacitors. With input stage fully differential operational transconductance amplifier (OTA) whose current outputs drive a high gain transimpedance amplifier (TIA), noise is minimized. To improve gain and performance, a common mode feedback stage is incorporated within the OTA. The chip has a simulated power consumption of 2.45 mW. At frequency of 20 MHz, the harmonic distortion is -48 dB for a 2 MHz 2 Vpp input voltage. A robust design with a single external control, it is designed in 0.5 mum 2P3M CMOS process.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121430327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488777
S. Dhokkar, P. Lagonotte, A. Piteau
Non-contact optical methods can be used for submicron surface thermal characterization of active semiconductor devices. In this work, an experimental device based on near infra-red radiometric method is presented. This device is breadboard to analyze a thermal behaviour of electronic component in steadied and transient state. The absolute temperature distribution is measured at the micron scale. The obtained results highlight the excellent spatial resolution of the experimental measurement apparatus and its great sensitivity for detection of weak thermal emission variations.
{"title":"Experimental setup for the measurement of local temperature in electronic component during the steady and transient state","authors":"S. Dhokkar, P. Lagonotte, A. Piteau","doi":"10.1109/MWSCAS.2007.4488777","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488777","url":null,"abstract":"Non-contact optical methods can be used for submicron surface thermal characterization of active semiconductor devices. In this work, an experimental device based on near infra-red radiometric method is presented. This device is breadboard to analyze a thermal behaviour of electronic component in steadied and transient state. The absolute temperature distribution is measured at the micron scale. The obtained results highlight the excellent spatial resolution of the experimental measurement apparatus and its great sensitivity for detection of weak thermal emission variations.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123870728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488685
Jongsoo Lee, P. Roblin, S. Bibyk, Chang-Woo Kim, Hyo-Dal Park, Young-Gi Kim
This paper describes a new Darlington AC-coupled mixer operating at 8 GHz with improved figure-of-merits. This Darlington AC-coupled mixer along with a simple AC- coupling mixer used for reference are implemented in a 0.35 mum SiGe bipolar process. The supply voltage and current consumption are 3.2 V and 28 mA. In the Darlington AC-coupling mixer, the conversion gain, the operating bandwidth, and the NF are found to be improved by 13 dB, 180 MHz, and 10 dB, respectively. These improved figure-of-merit results from the use of the Darlington cell in the transconductance stage of the AC-coupling mixer.
本文介绍了一种新的达林顿交流耦合混频器，工作在8 GHz，具有改进的优点系数。这种达林顿交流耦合混合器以及用于参考的简单交流耦合混合器在0.35 μ m SiGe双极过程中实现。电源电压和电流消耗为3.2 V和28 mA。在达林顿交流耦合混频器中，转换增益、工作带宽和NF分别提高了13 dB、180 MHz和10 dB。这些改进的性能因数是在交流耦合混频器的跨导阶段使用达林顿电池的结果。
{"title":"8 GHz high conversion gain Darlington mixer","authors":"Jongsoo Lee, P. Roblin, S. Bibyk, Chang-Woo Kim, Hyo-Dal Park, Young-Gi Kim","doi":"10.1109/MWSCAS.2007.4488685","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488685","url":null,"abstract":"This paper describes a new Darlington AC-coupled mixer operating at 8 GHz with improved figure-of-merits. This Darlington AC-coupled mixer along with a simple AC- coupling mixer used for reference are implemented in a 0.35 mum SiGe bipolar process. The supply voltage and current consumption are 3.2 V and 28 mA. In the Darlington AC-coupling mixer, the conversion gain, the operating bandwidth, and the NF are found to be improved by 13 dB, 180 MHz, and 10 dB, respectively. These improved figure-of-merit results from the use of the Darlington cell in the transconductance stage of the AC-coupling mixer.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121528432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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