Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488605
T. Williams, M. Ahmadi, W. Miller
A common way of implementing multiplication in digital filters is by a series of shift and add operations. If the multiplier is represented in canonical signed digit (CSD) format then the number of additions (subtractions) needed will be reduced. This can be further reduced through subexpression elimination in the vertical, horizontal or both dimensions. This paper presents a method to graphically transform the subexpression elimination problem into one that is easily solved by a standard genetic algorithm. It operates in the vertical or horizontal dimensions or optimises simultaneously in both dimensions.
{"title":"A graphical transform for subexpression elimination using genetic algorithms","authors":"T. Williams, M. Ahmadi, W. Miller","doi":"10.1109/MWSCAS.2007.4488605","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488605","url":null,"abstract":"A common way of implementing multiplication in digital filters is by a series of shift and add operations. If the multiplier is represented in canonical signed digit (CSD) format then the number of additions (subtractions) needed will be reduced. This can be further reduced through subexpression elimination in the vertical, horizontal or both dimensions. This paper presents a method to graphically transform the subexpression elimination problem into one that is easily solved by a standard genetic algorithm. It operates in the vertical or horizontal dimensions or optimises simultaneously in both dimensions.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133461889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488558
H. San, Hajime Konagaya, Feng Xu, A. Motozawa, Haruo Kobayashi, Kazumasa Ando, H. Yoshida, Chieto Murayama
This paper proposes novel feedforward architecture of a second-order DeltaSigmaAD modulator with single DAC- feedback topology. DeltaSigmaAD modulator realizes high resolution by oversampling and noise shaping technique. However, its SNDR (signal to noise and distortion ratio) is limited by the dynamic range of the input signal and non-idealities of building blocks, particularly by the harmonic distortion in amplifier circuits. Compared with a feed backed DeltaSigmaAD modulator, in a full feedforward DeltaSigmaAD modulator structure, the signal transfer function is unity under ideal circumstances. It means that the signal swings through the loop filter become smaller. Therefore, the harmonic distortion generated inside the loop filter can be significantly reduced because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. Moreover, the reduction of the internal signal swings also relaxes output swing requirement for amplifiers in low-voltage design. However, in conventional feedforward DeltaSigmaAD modulator, an analog adder is needed before quantizer. Especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to large chip area and extra power dissipation. In this paper, we propose a novel architecture of a feedforward DeltaSigmaAD modulator. It realizes the summation of feedforward signals without additional amplifier that is equivalent to the conventional one but smaller chip area and low-power dissipation. We also conducted MATLAB and SPICE simulations to verify the proposed architecture and modulator circuits.
{"title":"Second-order ΔΣAD modulator with novel feedforward architecture","authors":"H. San, Hajime Konagaya, Feng Xu, A. Motozawa, Haruo Kobayashi, Kazumasa Ando, H. Yoshida, Chieto Murayama","doi":"10.1109/MWSCAS.2007.4488558","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488558","url":null,"abstract":"This paper proposes novel feedforward architecture of a second-order DeltaSigmaAD modulator with single DAC- feedback topology. DeltaSigmaAD modulator realizes high resolution by oversampling and noise shaping technique. However, its SNDR (signal to noise and distortion ratio) is limited by the dynamic range of the input signal and non-idealities of building blocks, particularly by the harmonic distortion in amplifier circuits. Compared with a feed backed DeltaSigmaAD modulator, in a full feedforward DeltaSigmaAD modulator structure, the signal transfer function is unity under ideal circumstances. It means that the signal swings through the loop filter become smaller. Therefore, the harmonic distortion generated inside the loop filter can be significantly reduced because the effect of non-idealities in amplifiers can be suppressed when signal swing is small. Moreover, the reduction of the internal signal swings also relaxes output swing requirement for amplifiers in low-voltage design. However, in conventional feedforward DeltaSigmaAD modulator, an analog adder is needed before quantizer. Especially in a multibit modulator, an additional amplifier is necessary to realize the summation of feedforward signals, which leads to large chip area and extra power dissipation. In this paper, we propose a novel architecture of a feedforward DeltaSigmaAD modulator. It realizes the summation of feedforward signals without additional amplifier that is equivalent to the conventional one but smaller chip area and low-power dissipation. We also conducted MATLAB and SPICE simulations to verify the proposed architecture and modulator circuits.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132143471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488704
O.-L. Cristobal, A.-P. Ruben, V.-G. Jose
This paper presents the development of a fuzzy carom player who considers the necessary reaction and the path distance necessary to hit a billiard ball and the effect necessary to obtain a carom. The controller is incorporated to a mechanism, also developed in this project, which is the one in charge to fire. The blow can be to different heights and with different force intensities. The capacity to decide that shot to do becomes according to the situation of the balls on the table of billiards given by a user mean an interface The development process from each one of the stages that implementing it is explained, putting special attention in its assembly and programming, including tests and results. Options to future works are also considered.
{"title":"Fuzzy control of a carom player","authors":"O.-L. Cristobal, A.-P. Ruben, V.-G. Jose","doi":"10.1109/MWSCAS.2007.4488704","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488704","url":null,"abstract":"This paper presents the development of a fuzzy carom player who considers the necessary reaction and the path distance necessary to hit a billiard ball and the effect necessary to obtain a carom. The controller is incorporated to a mechanism, also developed in this project, which is the one in charge to fire. The blow can be to different heights and with different force intensities. The capacity to decide that shot to do becomes according to the situation of the balls on the table of billiards given by a user mean an interface The development process from each one of the stages that implementing it is explained, putting special attention in its assembly and programming, including tests and results. Options to future works are also considered.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134457601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488655
J. Mukherjee
Phase Noise is an important consideration in oscillators. A procedure to obtain low phase noise through MOSFET channel width optimization is described in this paper. The impact of channel width is different for white and flicker noise. The Phase Model used for this purpose is based on a circuit based model. While the Phase Noise due to white noise increases with channel width increase, that due to flicker noise decreases, thereby setting up the conditions for optimization. We derive mathematically that optimum channel width that results in the lowest phase noise with other parameters remaining constant and verify our results by simulation.
{"title":"Optimizing MOSFET channel width for low phase noise in LC oscillators","authors":"J. Mukherjee","doi":"10.1109/MWSCAS.2007.4488655","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488655","url":null,"abstract":"Phase Noise is an important consideration in oscillators. A procedure to obtain low phase noise through MOSFET channel width optimization is described in this paper. The impact of channel width is different for white and flicker noise. The Phase Model used for this purpose is based on a circuit based model. While the Phase Noise due to white noise increases with channel width increase, that due to flicker noise decreases, thereby setting up the conditions for optimization. We derive mathematically that optimum channel width that results in the lowest phase noise with other parameters remaining constant and verify our results by simulation.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115720412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488714
Zhiyu Liu, V. Kursun
A new circuit technique is proposed in this paper to lower the energy overhead of mode transitions for effective energy reduction with the MTCMOS circuits. The charge stored at the virtual rails and the sleep signal lines are recycled during the active-to-sleep-to-active mode transitions with the proposed technique. Applying the charge recycling MTCMOS circuit technique to a 32-bit Brent-Kung adder reduces the energy overhead due to the mode transitions by up to 12.2% as compared to the conventional MTCMOS circuits. Furthermore, the standby mode power consumption is reduced by up to 92.8% as compared to a standard Brent-Kung adder in a 65 nm CMOS technology.
{"title":"Low energy MTCMOS with sleep transistor charge recycling","authors":"Zhiyu Liu, V. Kursun","doi":"10.1109/MWSCAS.2007.4488714","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488714","url":null,"abstract":"A new circuit technique is proposed in this paper to lower the energy overhead of mode transitions for effective energy reduction with the MTCMOS circuits. The charge stored at the virtual rails and the sleep signal lines are recycled during the active-to-sleep-to-active mode transitions with the proposed technique. Applying the charge recycling MTCMOS circuit technique to a 32-bit Brent-Kung adder reduces the energy overhead due to the mode transitions by up to 12.2% as compared to the conventional MTCMOS circuits. Furthermore, the standby mode power consumption is reduced by up to 92.8% as compared to a standard Brent-Kung adder in a 65 nm CMOS technology.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115799258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488586
R. Wu, F. J. Lidgey, K. Hayatleh
A novel amplifier design technique based on the negative impedance compensation is presented for amplifiers with feedback. The theoretical and simulation results have shown that the proposed technique is very effective and can provide high gain accuracy and high linearity with relatively low open-loop gain amplifiers, hence the technique has a very good potential for high frequency applications.
{"title":"Design of amplifiers with high gain accuracy and high linearity","authors":"R. Wu, F. J. Lidgey, K. Hayatleh","doi":"10.1109/MWSCAS.2007.4488586","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488586","url":null,"abstract":"A novel amplifier design technique based on the negative impedance compensation is presented for amplifiers with feedback. The theoretical and simulation results have shown that the proposed technique is very effective and can provide high gain accuracy and high linearity with relatively low open-loop gain amplifiers, hence the technique has a very good potential for high frequency applications.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"345 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124263851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488696
G. Marinova, M. Bellanger, V. Guliashki
The paper presents a study on the realization of equalizer IP (intellectual property) blocks for FPGA-based realization of multicarrier modem cores applying filter bank based principle and OQAM modulation. New equalization IP blocks with appropriate architectures for two different modem applications are proposed - following the ADSL standard and according to the 802.11 wireless communication standard (WiFi). We estimated the impact of equalization IPs on the frequency, the area efficiency and the SNR of the FPGA-based modem realizations.
{"title":"Equalization in FPGA-based realization of a multicarrier modem core","authors":"G. Marinova, M. Bellanger, V. Guliashki","doi":"10.1109/MWSCAS.2007.4488696","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488696","url":null,"abstract":"The paper presents a study on the realization of equalizer IP (intellectual property) blocks for FPGA-based realization of multicarrier modem cores applying filter bank based principle and OQAM modulation. New equalization IP blocks with appropriate architectures for two different modem applications are proposed - following the ADSL standard and according to the 802.11 wireless communication standard (WiFi). We estimated the impact of equalization IPs on the frequency, the area efficiency and the SNR of the FPGA-based modem realizations.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114863480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488634
S. Milicevic, L. MacEachern
This paper presents a formula for predicting the frequency of oscillation of a cross-coupled voltage-controlled oscillator (VCO). The VCO was implemented in a CMOS 0.13 mum technology. The calculated frequency of operation shows a close agreement with the simulated results. The VCO operates at 10 GHz and consumes 490 muW from a IV supply. The simulated phase noise at a 1 MHz offset is -114.4 dBc/Hz resulting in a figure of merit (FOM) of -197.6 dB. The VCO can cover a 748 MHz frequency range and occupies 0.096 mm2 of chip area. The simulated sensitivity of the frequency of operation and peak-to-peak amplitude due to temperature is 4.58 MHz/degC and 3.6 mV/degC, respectively. The sensitivity of the frequency of operation and peak-to-peak amplitude due to power supply is 1.1 GHz/V and 1.82 V/V, respectively.
{"title":"Frequency of oscillation of a cross-coupled CMOS VCO with resistor tail biasing","authors":"S. Milicevic, L. MacEachern","doi":"10.1109/MWSCAS.2007.4488634","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488634","url":null,"abstract":"This paper presents a formula for predicting the frequency of oscillation of a cross-coupled voltage-controlled oscillator (VCO). The VCO was implemented in a CMOS 0.13 mum technology. The calculated frequency of operation shows a close agreement with the simulated results. The VCO operates at 10 GHz and consumes 490 muW from a IV supply. The simulated phase noise at a 1 MHz offset is -114.4 dBc/Hz resulting in a figure of merit (FOM) of -197.6 dB. The VCO can cover a 748 MHz frequency range and occupies 0.096 mm2 of chip area. The simulated sensitivity of the frequency of operation and peak-to-peak amplitude due to temperature is 4.58 MHz/degC and 3.6 mV/degC, respectively. The sensitivity of the frequency of operation and peak-to-peak amplitude due to power supply is 1.1 GHz/V and 1.82 V/V, respectively.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123596343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488542
N. Rafla
Systems on Reconfigurable Chips contain rich resources of logic, memory, and processor cores on the same fabric. This platform is suitable for implementation of Evolvable Reconfigurable Hardware Architectures (ERHA). It is based on the idea of combining reconfigurable Field Programmable Gate Arrays (FPGA) along with genetic algorithms (GA) to perform the reconfiguration operation. This architecture is a suitable candidate for implementation of early-processing stage operators of image processing such as filtering and edge detection. However, there are still fundamental issues need to be solved regarding the on-chip reprogramming of the logic. This paper presents a framework for implementing an evolvable hardware architecture for edge detection on Xilinx Virtex-4 chip. Some preliminary results are discussed.
{"title":"Evolvable Reconfigurable Hardare framework for edge detection","authors":"N. Rafla","doi":"10.1109/MWSCAS.2007.4488542","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488542","url":null,"abstract":"Systems on Reconfigurable Chips contain rich resources of logic, memory, and processor cores on the same fabric. This platform is suitable for implementation of Evolvable Reconfigurable Hardware Architectures (ERHA). It is based on the idea of combining reconfigurable Field Programmable Gate Arrays (FPGA) along with genetic algorithms (GA) to perform the reconfiguration operation. This architecture is a suitable candidate for implementation of early-processing stage operators of image processing such as filtering and edge detection. However, there are still fundamental issues need to be solved regarding the on-chip reprogramming of the logic. This paper presents a framework for implementing an evolvable hardware architecture for edge detection on Xilinx Virtex-4 chip. Some preliminary results are discussed.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122010818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488672
H. Madanayake, L. Bruton
A systolic-array architecture for real-time implementation of M number of independent 2D IIR spatio-temporal frequency-planar beam filters is proposed. The proposed architecture enables M time-multiplexed beam filters to be implemented on hardware using the arithmetic circuit real-estate required for a single beam filter. The architecture is a building block for highly-selective 2D IIR spatio-temporal fan filter banks for real-time broadband plane-wave fan filtering applications in ultrasonic imaging, intermediate-frequency (IF) digital beamforming, directional audio, and sonar imaging. A prototype of the systolic-array for M=4 beam filters is demonstrated using FPGA circuit implementations having W-bit (W=13,14,...,17) finite-precision arithmetic circuits, and is shown to operate in real-time at up to FCLK= 125 MHz on a single Xilinx Virtex-4 sx35 10ff668 device.
{"title":"Time-multiplexed systolic-array processors for real-time 2D IIR beam plane-wave filters","authors":"H. Madanayake, L. Bruton","doi":"10.1109/MWSCAS.2007.4488672","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488672","url":null,"abstract":"A systolic-array architecture for real-time implementation of M number of independent 2D IIR spatio-temporal frequency-planar beam filters is proposed. The proposed architecture enables M time-multiplexed beam filters to be implemented on hardware using the arithmetic circuit real-estate required for a single beam filter. The architecture is a building block for highly-selective 2D IIR spatio-temporal fan filter banks for real-time broadband plane-wave fan filtering applications in ultrasonic imaging, intermediate-frequency (IF) digital beamforming, directional audio, and sonar imaging. A prototype of the systolic-array for M=4 beam filters is demonstrated using FPGA circuit implementations having W-bit (W=13,14,...,17) finite-precision arithmetic circuits, and is shown to operate in real-time at up to FCLK= 125 MHz on a single Xilinx Virtex-4 sx35 10ff668 device.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122173421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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