Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488756
Y. Yano, M. Kaneko
This paper proposes a reduced solution space for the sequence-pair based placement. Assuming that some "model placement" is given, we will extract relative spatial relation between modules from it. Based on this extracted information, we will impose some constraints on permutations Gamma+ and Gamma- of modules in a sequence pair code in order to reduce the solution space without losing good solutions. As a practical implementation of this concept, the result of the so called "Force Directed Placement" is used as our model placement, constraints are extracted from it, and Simulated Annealing is applied to the reduced sequence-pair solution space. The experimental results show us that the combination of the reduced solution space with SA search has an excellent potential in wire length minimization while keeping a comparable potential in area minimization.
{"title":"Solution space reduction of sequence pairs using model placement","authors":"Y. Yano, M. Kaneko","doi":"10.1109/MWSCAS.2007.4488756","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488756","url":null,"abstract":"This paper proposes a reduced solution space for the sequence-pair based placement. Assuming that some \"model placement\" is given, we will extract relative spatial relation between modules from it. Based on this extracted information, we will impose some constraints on permutations Gamma+ and Gamma- of modules in a sequence pair code in order to reduce the solution space without losing good solutions. As a practical implementation of this concept, the result of the so called \"Force Directed Placement\" is used as our model placement, constraints are extracted from it, and Simulated Annealing is applied to the reduced sequence-pair solution space. The experimental results show us that the combination of the reduced solution space with SA search has an excellent potential in wire length minimization while keeping a comparable potential in area minimization.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"351 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115896255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488643
K. Schulmeyer, C. Trehan, K. Chao
An architecture that reduces the effects of supply noise on the regulated output of a DC-DC converter has been proposed. The structure consists of a sigma-delta modulator which drives the half bridge switches directly. The output of the quantizer is taken as the feedback for the sigma-delta as usual, but this feedback signal goes to a one-bit digital-to- analog converter that uses the noisy voltage supply as a reference to suppress the supply noise at the output. The proposed structure, designed and simulated using a 2.5V TSMC 0.25u process, shows supply ripple suppression.
{"title":"A ∑Δ based DC-DC converter with supply noise suppression","authors":"K. Schulmeyer, C. Trehan, K. Chao","doi":"10.1109/MWSCAS.2007.4488643","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488643","url":null,"abstract":"An architecture that reduces the effects of supply noise on the regulated output of a DC-DC converter has been proposed. The structure consists of a sigma-delta modulator which drives the half bridge switches directly. The output of the quantizer is taken as the feedback for the sigma-delta as usual, but this feedback signal goes to a one-bit digital-to- analog converter that uses the noisy voltage supply as a reference to suppress the supply noise at the output. The proposed structure, designed and simulated using a 2.5V TSMC 0.25u process, shows supply ripple suppression.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132196234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488532
M. Mehran, N. Masoumi
The delay of global interconnects increases with technology scaling because their thickness to width aspect ratio tend to increase with scaling, while the lengths remain constant or even increase. The buffer insertion technique is generally used to reduce the delay of long global interconnects. In this paper, a new method for optimization of the global interconnects for high performance VLSI circuits in VDSM technologies is presented. A long global interconnect is divided into unequal segments with unequal buffer sizes between them. Following that a generalized analytical method is proposed to optimize the delay-energy product (FOM). In this work, we use the genetic algorithm (GA) to optimize the delay-energy product. Eventually, we compare our method with the method of equal wire segmentation with equal buffer sizing, which also has been optimized using GA algorithm.
{"title":"A tapered partitioning method for “delay energy product” optimization in global interconnects","authors":"M. Mehran, N. Masoumi","doi":"10.1109/MWSCAS.2007.4488532","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488532","url":null,"abstract":"The delay of global interconnects increases with technology scaling because their thickness to width aspect ratio tend to increase with scaling, while the lengths remain constant or even increase. The buffer insertion technique is generally used to reduce the delay of long global interconnects. In this paper, a new method for optimization of the global interconnects for high performance VLSI circuits in VDSM technologies is presented. A long global interconnect is divided into unequal segments with unequal buffer sizes between them. Following that a generalized analytical method is proposed to optimize the delay-energy product (FOM). In this work, we use the genetic algorithm (GA) to optimize the delay-energy product. Eventually, we compare our method with the method of equal wire segmentation with equal buffer sizing, which also has been optimized using GA algorithm.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132240509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488772
Jinseok Lee, Sangkil Jung, Y. Kyong, Xi Deng, Sangjin Hong, W. Cho
In this paper, we consider a wireless fusion sensor network where multiple types of sensors are incorporated in each sensor node. Each sensor node incorporates a RFID reader and a acoustic sensor. The RFID reader senses the proximity of target objects and acoustic sensors detect the objects for position estimations. The object positions estimated by both sensors are compensated by visual sensor to obtain more accurate object coordinates. In this paper, we perform network traffic analysis for the wireless fusion sensor network by using NS-2 simulations under various network scenarios. The analysis includes the feasibility of fusion network, hop-by-hop delay, and end-to-end delay.
{"title":"Data traffic analysis in wireless fusion network with multiple sensors","authors":"Jinseok Lee, Sangkil Jung, Y. Kyong, Xi Deng, Sangjin Hong, W. Cho","doi":"10.1109/MWSCAS.2007.4488772","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488772","url":null,"abstract":"In this paper, we consider a wireless fusion sensor network where multiple types of sensors are incorporated in each sensor node. Each sensor node incorporates a RFID reader and a acoustic sensor. The RFID reader senses the proximity of target objects and acoustic sensors detect the objects for position estimations. The object positions estimated by both sensors are compensated by visual sensor to obtain more accurate object coordinates. In this paper, we perform network traffic analysis for the wireless fusion sensor network by using NS-2 simulations under various network scenarios. The analysis includes the feasibility of fusion network, hop-by-hop delay, and end-to-end delay.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132302619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488642
A. Fardoun, A. Assi, E. Ismail
In this paper, a method is presented to reduce electro-magnetic emissions in AC drives. This method is applicable to many AC drives. It is proposed to dither the switching frequency of the power devices of the inverter in a pseudo-random way to spread out the emitted radio- frequency (RF) energy over larger frequency range. The proposed method requires only software changes. Practical constraints to implement the frequency dithering approach are discussed. Simulation & measurements shows an improvement of more than 10 dB. The proposed method also converts certain spikes at integer harmonics of the switching frequency from narrow band to broadband noise.
{"title":"Reduction of EMI through switching frequency dithering","authors":"A. Fardoun, A. Assi, E. Ismail","doi":"10.1109/MWSCAS.2007.4488642","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488642","url":null,"abstract":"In this paper, a method is presented to reduce electro-magnetic emissions in AC drives. This method is applicable to many AC drives. It is proposed to dither the switching frequency of the power devices of the inverter in a pseudo-random way to spread out the emitted radio- frequency (RF) energy over larger frequency range. The proposed method requires only software changes. Practical constraints to implement the frequency dithering approach are discussed. Simulation & measurements shows an improvement of more than 10 dB. The proposed method also converts certain spikes at integer harmonics of the switching frequency from narrow band to broadband noise.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132348418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488749
A. Beg
Architectural simulators are traditionally used to study the design trade-offs for processor systems. The simulators are implemented in a high-level programming language or a hardware descriptive language, and are used to estimate the system performance prior to the hardware implementation. The simulations, however, may need to run for long periods of time for even a small set of design variations. In this paper, we propose a machine learnt (neural network/NN) model for estimating the execution performance of a superscalar processor. Multiple runs for the model are finished in less than a few milliseconds as compared to days or weeks required for simulation-based methods. The model is able to predict the execution throughput of a processor system with over 85% accuracy when tested with six SPEC2000 CPU integer benchmarks. The proposed model has possible applications in computer architecture research and teaching.
{"title":"Predicting processor performance with a machine learnt model","authors":"A. Beg","doi":"10.1109/MWSCAS.2007.4488749","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488749","url":null,"abstract":"Architectural simulators are traditionally used to study the design trade-offs for processor systems. The simulators are implemented in a high-level programming language or a hardware descriptive language, and are used to estimate the system performance prior to the hardware implementation. The simulations, however, may need to run for long periods of time for even a small set of design variations. In this paper, we propose a machine learnt (neural network/NN) model for estimating the execution performance of a superscalar processor. Multiple runs for the model are finished in less than a few milliseconds as compared to days or weeks required for simulation-based methods. The model is able to predict the execution throughput of a processor system with over 85% accuracy when tested with six SPEC2000 CPU integer benchmarks. The proposed model has possible applications in computer architecture research and teaching.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"3 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134550006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488602
Lei Zhang, Kui Bo, Q. Zhang
This paper presents an overview of emerging artificial neural network (ANN) techniques for linear and nonlinear microwave modeling. ANN based models can automatically learn the microwave component or circuit behaviors with satisfactory accuracy, and the trained ANN models are able to implement into commercial circuit simulators for efficient design and optimization. ANN modeling techniques are successfully applied on EM, nonlinear device, and circuit behavior modeling, with speed and accuracy advantages over conventional techniques.
{"title":"Application of neural networks for linear/nonlinear microwave modeling","authors":"Lei Zhang, Kui Bo, Q. Zhang","doi":"10.1109/MWSCAS.2007.4488602","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488602","url":null,"abstract":"This paper presents an overview of emerging artificial neural network (ANN) techniques for linear and nonlinear microwave modeling. ANN based models can automatically learn the microwave component or circuit behaviors with satisfactory accuracy, and the trained ANN models are able to implement into commercial circuit simulators for efficient design and optimization. ANN modeling techniques are successfully applied on EM, nonlinear device, and circuit behavior modeling, with speed and accuracy advantages over conventional techniques.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133914987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488806
M. McCoy, C. Isert, D. Jackson, J. Naber
This paper describes a method for determining a digital representation of a value for a remote sensing element using a novel and lower power method of analog to digital conversion. This conversion process is most effective for low-frequency, radio frequency identification (RFID) sensing systems where the sensing element tags are powered by an inductively coupled carrier signal of fixed frequency. The method uses a specially gated frequency counter to create a digital value that is related to the system's carrier frequency and the frequency of variable oscillator used with the sensing element. This conversion method is highly scalable while maintaining a low current consumption. One configuration yields four bits of resolution with a conversion time of 1.34 ms and a current consumption of 30 muA. The ASIC was fabricated on a 1.5 mum CMOS process from AMI Semiconductor.
本文描述了一种确定遥感元件值的数字表示的方法，该方法使用一种新颖的低功率模拟到数字转换方法。这种转换过程对于低频射频识别(RFID)传感系统最为有效，其中传感元件标签由固定频率的电感耦合载波信号供电。该方法使用一个特殊的门控频率计数器来创建一个数字值，该数字值与系统的载波频率和与传感元件一起使用的可变振荡器的频率有关。这种转换方法在保持低电流消耗的同时具有高度可扩展性。一种配置产生4位分辨率，转换时间为1.34 ms，电流消耗为30 muA。ASIC是在AMI半导体的1.5 μ m CMOS工艺上制造的。
{"title":"A frequency counter based analog-to-digital converter for a RFID telemetry system","authors":"M. McCoy, C. Isert, D. Jackson, J. Naber","doi":"10.1109/MWSCAS.2007.4488806","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488806","url":null,"abstract":"This paper describes a method for determining a digital representation of a value for a remote sensing element using a novel and lower power method of analog to digital conversion. This conversion process is most effective for low-frequency, radio frequency identification (RFID) sensing systems where the sensing element tags are powered by an inductively coupled carrier signal of fixed frequency. The method uses a specially gated frequency counter to create a digital value that is related to the system's carrier frequency and the frequency of variable oscillator used with the sensing element. This conversion method is highly scalable while maintaining a low current consumption. One configuration yields four bits of resolution with a conversion time of 1.34 ms and a current consumption of 30 muA. The ASIC was fabricated on a 1.5 mum CMOS process from AMI Semiconductor.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134292099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488783
D.A. Ortiz, N. Santiago
Power consumption is an important constraint in the design of battery-operated embedded systems. The problem of minimizing power dissipation may be handled in terms of hardware or software optimizations. High-level language optimization techniques appear as an alternative to achieve low power consumption when programming embedded systems. In this work, software optimization techniques were applied to a set of code segments in a high-level language, in order to analyze the effect that source code optimizations have on the power dissipation of microprocessor-based systems. Design of experiments (DOE) techniques were used in order to reach statistical sound conclusions about the actual impact that software optimization techniques have on power consumption.
{"title":"High-level optimization for low power consumption on microprocessor-based systems","authors":"D.A. Ortiz, N. Santiago","doi":"10.1109/MWSCAS.2007.4488783","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488783","url":null,"abstract":"Power consumption is an important constraint in the design of battery-operated embedded systems. The problem of minimizing power dissipation may be handled in terms of hardware or software optimizations. High-level language optimization techniques appear as an alternative to achieve low power consumption when programming embedded systems. In this work, software optimization techniques were applied to a set of code segments in a high-level language, in order to analyze the effect that source code optimizations have on the power dissipation of microprocessor-based systems. Design of experiments (DOE) techniques were used in order to reach statistical sound conclusions about the actual impact that software optimization techniques have on power consumption.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"31 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131115988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-08-01DOI: 10.1109/MWSCAS.2007.4488662
J. Rice, J. Schultz, W. Osborn
Many data structures are proposed for managing spatial data. However, they are limited in their software implementations. This paper analyses two hardware implementations of an existing spatial data structure using a FPGA.
{"title":"Exploring different methods for 2DR-tree binary search on a FPGA","authors":"J. Rice, J. Schultz, W. Osborn","doi":"10.1109/MWSCAS.2007.4488662","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488662","url":null,"abstract":"Many data structures are proposed for managing spatial data. However, they are limited in their software implementations. This paper analyses two hardware implementations of an existing spatial data structure using a FPGA.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132884567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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