Pub Date : 1900-01-01DOI: 10.1109/ISSCC.2009.4977305
S. Rusu, S. Tam, H. Muljono, J. Stinson, D. Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli
A 2.3B transistors, 8-core, 16-thread 64-bit Xeon® EX processor with a 24MB shared L3 cache was implemented in a 45nm 9-metal process. Multiple clock and voltage domains are employed to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors using the same silicon die and package. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.
{"title":"A 45nm 8-core enterprise Xeon® processor","authors":"S. Rusu, S. Tam, H. Muljono, J. Stinson, D. Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli","doi":"10.1109/ISSCC.2009.4977305","DOIUrl":"https://doi.org/10.1109/ISSCC.2009.4977305","url":null,"abstract":"A 2.3B transistors, 8-core, 16-thread 64-bit Xeon® EX processor with a 24MB shared L3 cache was implemented in a 45nm 9-metal process. Multiple clock and voltage domains are employed to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors using the same silicon die and package. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132235986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/asscc.2009.5357218
A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida, Y. Fujimura, T. Yabe
This paper proposes a new scheme utilizing a small offset voltage (Vos) sense amplifier (SA) to reduce the deterioration of the read speed and the cell stability at the low power supply. This concept is introduced to realize a low supply voltage operation SRAM with a small area penalty. The transistor threshold voltage (Vth) shift caused by Hot Carrier Injection (HCI) [1] is used for Vos trimming after the chip fabrication. The SA with the offset trimming circuit is implemented in 40nm CMOS technology and the reduction of Vos by 76mV has been confirmed with the measurement and simulation results. This reduction corresponds to the improvement of read frequency by 40% and 8x failure rate improvements at 0.6V supply voltage.
{"title":"A low supply voltage operation SRAM with HCI trimmed sense amplifiers","authors":"A. Kawasumi, Y. Takeyama, O. Hirabayashi, K. Kushida, Y. Fujimura, T. Yabe","doi":"10.1109/asscc.2009.5357218","DOIUrl":"https://doi.org/10.1109/asscc.2009.5357218","url":null,"abstract":"This paper proposes a new scheme utilizing a small offset voltage (Vos) sense amplifier (SA) to reduce the deterioration of the read speed and the cell stability at the low power supply. This concept is introduced to realize a low supply voltage operation SRAM with a small area penalty. The transistor threshold voltage (Vth) shift caused by Hot Carrier Injection (HCI) [1] is used for Vos trimming after the chip fabrication. The SA with the offset trimming circuit is implemented in 40nm CMOS technology and the reduction of Vos by 76mV has been confirmed with the measurement and simulation results. This reduction corresponds to the improvement of read frequency by 40% and 8x failure rate improvements at 0.6V supply voltage.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132877811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/asscc.2009.5357174
Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee
This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Börck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.
{"title":"A 26.9K 314.5Mbps soft (32400, 32208) BCH decoder chip for DVB-S2 system","authors":"Yi-Min Lin, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/asscc.2009.5357174","DOIUrl":"https://doi.org/10.1109/asscc.2009.5357174","url":null,"abstract":"This paper provides a soft BCH decoder using error magnitudes to deal with least reliable bits. With soft information from the previous decoder defined in digital video broadcasting (DVB), the proposed soft BCH decoder provides much lower complexity and latency than the traditional hard BCH decoder while still maintaining performance. The proposed error locator evaluator architecture evaluates error locations without Chien search, leading to high throughput. Börck-Pereyra error magnitudes solvers (BP-EMS) is presented to improve decoding efficiency and hardware complexity. The experimental result reveals that our proposed soft (32400, 32208) BCH decoder defined in DVB-S2 system can save 50.0% gate-count and achieve 314.5Mbps in standard CMOS 90nm technology.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115688186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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