A 4×4 multi-input multi-output (MIMO) orthogonal frequency-division multiplexing (OFDM) modem with one-symbol-locked timing recovery, anti-I/Q mismatch frequency recovery, frequency-dependent I/Q mismatch estimation and adaptive equalization is implemented in 0.13-μm CMOS library. This chip occupies 4.6×4.6 mm2 and consumes 62.8 mW at 1.2 V.
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357277
D. Imanishi, K. Okada, A. Matsuzawa
A tunable power amplifier (PA) from 0.9 GHz to 3.0 GHz is presented. This paper proposes an output impedance tuning method by using resistive feedback and a parallel resonance consisting of an inductor and a tunable capacitor array. The proposed multi-band PA can adjust the output impedance to 50 Ω over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18 μm CMOS process, and the supply voltage is 3.3 V. Over all of the frequency range, the PA realizes output return loss S22 of smaller than −10 dB, power gain of larger than 16 dB, output 1-dB compression point of larger than 17 dBm, and power added efficiency (PAE) at 1-dB compression point of larger than 10%.
{"title":"A 0.9–3.0 GHz fully integrated tunable CMOS power amplifier for multi-band transmitters","authors":"D. Imanishi, K. Okada, A. Matsuzawa","doi":"10.1109/ASSCC.2009.5357277","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357277","url":null,"abstract":"A tunable power amplifier (PA) from 0.9 GHz to 3.0 GHz is presented. This paper proposes an output impedance tuning method by using resistive feedback and a parallel resonance consisting of an inductor and a tunable capacitor array. The proposed multi-band PA can adjust the output impedance to 50 Ω over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18 μm CMOS process, and the supply voltage is 3.3 V. Over all of the frequency range, the PA realizes output return loss S22 of smaller than −10 dB, power gain of larger than 16 dB, output 1-dB compression point of larger than 17 dBm, and power added efficiency (PAE) at 1-dB compression point of larger than 10%.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121136217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357163
T. Sai, Y. Sugimoto
In this study, a fast response time of less than 10 us has been realized for the sudden output current change between 220 mA and 20 mA of a MOS current-mode buck DC-DC converter which utilizes a quadratic and input-voltage-dependent compensation slope. By using a quadratic and input-voltage-dependent compensation slope, the frequency characteristics of the current feedback loop become constant, and the converter's overall frequency characteristics come to be determined by just adjusting the frequency characteristics in the voltage feedback loop. By changing the time constant in an error amplifier to manipulate the phase margin, the converter's output voltage change becomes small and its response time becomes fast. The test chip of a MOS current-mode buck DC-DC converter using a 0.35-um CMOS process and a 5 MHz clock realized a 40.8 mV output voltage change and a 7.2 us of the response time.
在这项研究中，利用二次型和输入电压相关的补偿斜率，MOS电流型降压DC-DC变换器的输出电流在220 mA和20 mA之间突然变化，实现了小于10 us的快速响应时间。通过采用二次型且与输入电压相关的补偿斜率，电流反馈回路的频率特性保持恒定，只需调整电压反馈回路的频率特性即可确定变换器的整体频率特性。通过改变误差放大器的时间常数来控制相位裕度，使变换器的输出电压变化变小，响应时间变快。采用0.35 um CMOS工艺和5 MHz时钟的MOS电流型降压DC-DC变换器测试芯片实现了40.8 mV的输出电压变化和7.2 us的响应时间。
{"title":"A method for realizing a fast response time for the output current change of a MOS current-mode buck DC-DC converter which utilizes a quadratic and vin-dependent compensation slope","authors":"T. Sai, Y. Sugimoto","doi":"10.1109/ASSCC.2009.5357163","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357163","url":null,"abstract":"In this study, a fast response time of less than 10 us has been realized for the sudden output current change between 220 mA and 20 mA of a MOS current-mode buck DC-DC converter which utilizes a quadratic and input-voltage-dependent compensation slope. By using a quadratic and input-voltage-dependent compensation slope, the frequency characteristics of the current feedback loop become constant, and the converter's overall frequency characteristics come to be determined by just adjusting the frequency characteristics in the voltage feedback loop. By changing the time constant in an error amplifier to manipulate the phase margin, the converter's output voltage change becomes small and its response time becomes fast. The test chip of a MOS current-mode buck DC-DC converter using a 0.35-um CMOS process and a 5 MHz clock realized a 40.8 mV output voltage change and a 7.2 us of the response time.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121365052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357259
Ha Le-Thai, Huy-Hieu Nguyen, Hoai-Nam Nguyen, Hongrae Cho, Jeong-Seon Lee, Sang-Gug Lee
A new linearity improvement technique is proposed to implement a low-distortion Gm-C band-pass filter working in high IF ranges. The purpose of the linearization technique is to eliminate Gm″ value of the transconductor by employing a superposition method that combines two opposite non-linear behaviors of the two parallel wings designed inside the transconductor. Instead of conventional biquad structure, a resonant-coupling structure is adopted for the band-pass filter working at center frequency of 80MHz to make the frequency response flat and stable and to allow a stable frequency tuning as well as a flexible bandwidth tuning. Fabricated in 65nm CMOS process, the implemented IF band-pass filter provides a flat band-pass whose ripple is smaller than 0.1dB, a third-order rejection of 27dB, an IIP3 of −2dBm, and a NF of 21.5dB, while consuming 11mA from 1.2-V supply. The filter occupies a chip size of 0.5 mm × 0.5 mm.
提出了一种新的线性度改进技术，以实现在高中频范围内工作的低失真Gm-C带通滤波器。线性化技术的目的是通过采用叠加方法，将设计在跨导体内部的两个平行翼的两种相反的非线性行为结合起来，消除跨导体的Gm″值。工作在80MHz中心频率的带通滤波器采用谐振耦合结构，而不是传统的四联体结构，使频率响应平坦稳定，频率调谐稳定，带宽调谐灵活。所实现的中频带通滤波器采用65nm CMOS工艺制造，提供纹波小于0.1dB的平坦带通，三阶抑制27dB, IIP3为- 2dBm, NF为21.5dB，同时从1.2 v电源消耗11mA。该滤波器的芯片尺寸为0.5 mm × 0.5 mm。
{"title":"A new low-distortion transconductor applied in a flat band-pass filter","authors":"Ha Le-Thai, Huy-Hieu Nguyen, Hoai-Nam Nguyen, Hongrae Cho, Jeong-Seon Lee, Sang-Gug Lee","doi":"10.1109/ASSCC.2009.5357259","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357259","url":null,"abstract":"A new linearity improvement technique is proposed to implement a low-distortion Gm-C band-pass filter working in high IF ranges. The purpose of the linearization technique is to eliminate Gm″ value of the transconductor by employing a superposition method that combines two opposite non-linear behaviors of the two parallel wings designed inside the transconductor. Instead of conventional biquad structure, a resonant-coupling structure is adopted for the band-pass filter working at center frequency of 80MHz to make the frequency response flat and stable and to allow a stable frequency tuning as well as a flexible bandwidth tuning. Fabricated in 65nm CMOS process, the implemented IF band-pass filter provides a flat band-pass whose ripple is smaller than 0.1dB, a third-order rejection of 27dB, an IIP3 of −2dBm, and a NF of 21.5dB, while consuming 11mA from 1.2-V supply. The filter occupies a chip size of 0.5 mm × 0.5 mm.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121736734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357251
Kazutaka Kasuga, Mitsuko Saito, Tsutomu Takeya, N. Miura, H. Ishikuro, T. Kuroda
This paper provides the method for Wafer test of an inductive-coupling link. The inductive-coupling link can be tested whether it operates correctly before stacking chips. We provided the method that verify the operation of an inductive-coupling link from the relation between coupling coefficient of inductors and power that transmitter consumes.
{"title":"A Wafer test method of inductive-coupling link","authors":"Kazutaka Kasuga, Mitsuko Saito, Tsutomu Takeya, N. Miura, H. Ishikuro, T. Kuroda","doi":"10.1109/ASSCC.2009.5357251","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357251","url":null,"abstract":"This paper provides the method for Wafer test of an inductive-coupling link. The inductive-coupling link can be tested whether it operates correctly before stacking chips. We provided the method that verify the operation of an inductive-coupling link from the relation between coupling coefficient of inductors and power that transmitter consumes.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134304474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357248
Mitsuko Saito, Kazutaka Kasuga, Tsutomu Takeya, N. Miura, T. Kuroda
Inductive-coupling link between stacked chips in a package communicates by using coils made by on-chip interconnections. An XY-coil layout style allows logic interconnections to go through the coil, which significantly saves interconnection resources consumed by the coil. However, the logic interconnections generate capacitive-coupling noise on the coil and degrade signal in the inductive-coupling link. In this paper, an extended XY coil with ground shields is presented for noise reduction. Simulation study shows that the noise voltage is reduced to 1/5 of the conventional XY coil. This noise reduction enables to reduce transmit power required for the same BER. Test-chip measurement in 0.18μm CMOS demonstrates that the transmit power at lGb/s with BER<10-12 is reduced by 60% compared to the conventional XY coil.
{"title":"An extended XY coil for noise reduction in inductive-coupling link","authors":"Mitsuko Saito, Kazutaka Kasuga, Tsutomu Takeya, N. Miura, T. Kuroda","doi":"10.1109/ASSCC.2009.5357248","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357248","url":null,"abstract":"Inductive-coupling link between stacked chips in a package communicates by using coils made by on-chip interconnections. An XY-coil layout style allows logic interconnections to go through the coil, which significantly saves interconnection resources consumed by the coil. However, the logic interconnections generate capacitive-coupling noise on the coil and degrade signal in the inductive-coupling link. In this paper, an extended XY coil with ground shields is presented for noise reduction. Simulation study shows that the noise voltage is reduced to 1/5 of the conventional XY coil. This noise reduction enables to reduce transmit power required for the same BER. Test-chip measurement in 0.18μm CMOS demonstrates that the transmit power at lGb/s with BER<10-12 is reduced by 60% compared to the conventional XY coil.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132833637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 μm CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.
{"title":"A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video","authors":"Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jiun-In Guo, Jia-Wei Chen, Jinn-Shan Wang, Chin-Hsien Wang, H. Huang, Ching-Hwa Cheng","doi":"10.1109/ASSCC.2009.5357147","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357147","url":null,"abstract":"The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 μm CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128271508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357184
Shoichi Hara, K. Okada, A. Matsuzawa
This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed oscillator has a core VCO and a tuning-range extension circuit, which consists of an injection-locked frequency divider (ILFD), and flip flop dividers. The 2-stage differential ILFD can generate quadrature outputs, and it realizes 2, 3, 4, and 6 of divide ratio with very wide output frequency range. The proposed circuit is implemented by using a 90nm CMOS process, and the chip area is 250μm × 200 μm. The measured results achieves 9.3 MHz-to-5.7 GHz (199%) of continuous frequency tuning range with −210 dBc/Hz of FoMT.
{"title":"A 9.3MHz to 5.7GHz tunable LC-based VCO using a divide-by-N injection-locked frequency divider","authors":"Shoichi Hara, K. Okada, A. Matsuzawa","doi":"10.1109/ASSCC.2009.5357184","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357184","url":null,"abstract":"This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed oscillator has a core VCO and a tuning-range extension circuit, which consists of an injection-locked frequency divider (ILFD), and flip flop dividers. The 2-stage differential ILFD can generate quadrature outputs, and it realizes 2, 3, 4, and 6 of divide ratio with very wide output frequency range. The proposed circuit is implemented by using a 90nm CMOS process, and the chip area is 250μm × 200 μm. The measured results achieves 9.3 MHz-to-5.7 GHz (199%) of continuous frequency tuning range with −210 dBc/Hz of FoMT.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124595632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357199
Yanfei Chen, Sanroku Tsukamoto, T. Kuroda
A 9b 100MS/s successive approximation register (SAR) ADC has been implemented in 65nm CMOS, with an active area of 0.012mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1dB (8.53 ENOB) and consumes 1.46mW from a 1.2V supply, resulting in an FOM of 39fJ/conversion-step.
{"title":"A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS","authors":"Yanfei Chen, Sanroku Tsukamoto, T. Kuroda","doi":"10.1109/ASSCC.2009.5357199","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357199","url":null,"abstract":"A 9b 100MS/s successive approximation register (SAR) ADC has been implemented in 65nm CMOS, with an active area of 0.012mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1dB (8.53 ENOB) and consumes 1.46mW from a 1.2V supply, resulting in an FOM of 39fJ/conversion-step.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124595719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357189
Tomoyuki Takahashi, T. Uezono, Michihiro Shintani, K. Masu, Takashi Sato
Device-parameter estimation through path-delay measurement, which facilitates fast on-die performance prediction and diagnosis, is proposed. With the proposed technique, delays of a set of paths consisting of different logic cells are monitored. Based on the pre-characterized parameter to delay sensitivity, the process variation of a chip is estimated as an inverse problem. Discussion of desirable logic cell combination to form paths that maximize estimation accuracy is presented. Measurement of ring oscillator arrays composed of standard and customized logic cells resulted in consistent estimation of threshold voltages. Measurement accuracy is greatly enhanced by the proposed good logic cell combinations.
{"title":"On-die parameter extraction from path-delay measurements","authors":"Tomoyuki Takahashi, T. Uezono, Michihiro Shintani, K. Masu, Takashi Sato","doi":"10.1109/ASSCC.2009.5357189","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357189","url":null,"abstract":"Device-parameter estimation through path-delay measurement, which facilitates fast on-die performance prediction and diagnosis, is proposed. With the proposed technique, delays of a set of paths consisting of different logic cells are monitored. Based on the pre-characterized parameter to delay sensitivity, the process variation of a chip is estimated as an inverse problem. Discussion of desirable logic cell combination to form paths that maximize estimation accuracy is presented. Measurement of ring oscillator arrays composed of standard and customized logic cells resulted in consistent estimation of threshold voltages. Measurement accuracy is greatly enhanced by the proposed good logic cell combinations.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122613353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：