A 4×4 multi-input multi-output (MIMO) orthogonal frequency-division multiplexing (OFDM) modem with one-symbol-locked timing recovery, anti-I/Q mismatch frequency recovery, frequency-dependent I/Q mismatch estimation and adaptive equalization is implemented in 0.13-μm CMOS library. This chip occupies 4.6×4.6 mm2 and consumes 62.8 mW at 1.2 V.
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357277
D. Imanishi, K. Okada, A. Matsuzawa
A tunable power amplifier (PA) from 0.9 GHz to 3.0 GHz is presented. This paper proposes an output impedance tuning method by using resistive feedback and a parallel resonance consisting of an inductor and a tunable capacitor array. The proposed multi-band PA can adjust the output impedance to 50 Ω over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18 μm CMOS process, and the supply voltage is 3.3 V. Over all of the frequency range, the PA realizes output return loss S22 of smaller than −10 dB, power gain of larger than 16 dB, output 1-dB compression point of larger than 17 dBm, and power added efficiency (PAE) at 1-dB compression point of larger than 10%.
{"title":"A 0.9–3.0 GHz fully integrated tunable CMOS power amplifier for multi-band transmitters","authors":"D. Imanishi, K. Okada, A. Matsuzawa","doi":"10.1109/ASSCC.2009.5357277","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357277","url":null,"abstract":"A tunable power amplifier (PA) from 0.9 GHz to 3.0 GHz is presented. This paper proposes an output impedance tuning method by using resistive feedback and a parallel resonance consisting of an inductor and a tunable capacitor array. The proposed multi-band PA can adjust the output impedance to 50 Ω over a wide frequency range, so external isolators following PAs can be eliminated. The PA is implemented by using a 0.18 μm CMOS process, and the supply voltage is 3.3 V. Over all of the frequency range, the PA realizes output return loss S22 of smaller than −10 dB, power gain of larger than 16 dB, output 1-dB compression point of larger than 17 dBm, and power added efficiency (PAE) at 1-dB compression point of larger than 10%.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121136217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357252
M. Phyu, Yuanjin Zheng, Bin Zhao, Liu Xin, Yi Wang
This paper presents for the first time Electrocardiograph (ECG) QRS detection algorithm implemented in Application Specific Integrated Circuit (ASIC). The algorithm based on the dyadic wavelet transform (DYWT) multiscale-product scheme is designed especially for real-time biomedical signal processing applications. The algorithm is evaluated based on the MIT-BIH database and achieves a sensitivity of 99.63% and a positive predictivity of 99.89% of R-waves detection. The results show that the algorithm outperforms several well-known QRS complex detection algorithms. The proposed algorithm is then implemented in ASIC and fabricated with 0.18-μm CMOS technology and it consumes 176 μW at an operating frequency of 1 MHz with a supply voltage of 1.8 V.
{"title":"A real-time ECG QRS detection ASIC based on wavelet multiscale analysis","authors":"M. Phyu, Yuanjin Zheng, Bin Zhao, Liu Xin, Yi Wang","doi":"10.1109/ASSCC.2009.5357252","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357252","url":null,"abstract":"This paper presents for the first time Electrocardiograph (ECG) QRS detection algorithm implemented in Application Specific Integrated Circuit (ASIC). The algorithm based on the dyadic wavelet transform (DYWT) multiscale-product scheme is designed especially for real-time biomedical signal processing applications. The algorithm is evaluated based on the MIT-BIH database and achieves a sensitivity of 99.63% and a positive predictivity of 99.89% of R-waves detection. The results show that the algorithm outperforms several well-known QRS complex detection algorithms. The proposed algorithm is then implemented in ASIC and fabricated with 0.18-μm CMOS technology and it consumes 176 μW at an operating frequency of 1 MHz with a supply voltage of 1.8 V.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114704979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357259
Ha Le-Thai, Huy-Hieu Nguyen, Hoai-Nam Nguyen, Hongrae Cho, Jeong-Seon Lee, Sang-Gug Lee
A new linearity improvement technique is proposed to implement a low-distortion Gm-C band-pass filter working in high IF ranges. The purpose of the linearization technique is to eliminate Gm″ value of the transconductor by employing a superposition method that combines two opposite non-linear behaviors of the two parallel wings designed inside the transconductor. Instead of conventional biquad structure, a resonant-coupling structure is adopted for the band-pass filter working at center frequency of 80MHz to make the frequency response flat and stable and to allow a stable frequency tuning as well as a flexible bandwidth tuning. Fabricated in 65nm CMOS process, the implemented IF band-pass filter provides a flat band-pass whose ripple is smaller than 0.1dB, a third-order rejection of 27dB, an IIP3 of −2dBm, and a NF of 21.5dB, while consuming 11mA from 1.2-V supply. The filter occupies a chip size of 0.5 mm × 0.5 mm.
提出了一种新的线性度改进技术，以实现在高中频范围内工作的低失真Gm-C带通滤波器。线性化技术的目的是通过采用叠加方法，将设计在跨导体内部的两个平行翼的两种相反的非线性行为结合起来，消除跨导体的Gm″值。工作在80MHz中心频率的带通滤波器采用谐振耦合结构，而不是传统的四联体结构，使频率响应平坦稳定，频率调谐稳定，带宽调谐灵活。所实现的中频带通滤波器采用65nm CMOS工艺制造，提供纹波小于0.1dB的平坦带通，三阶抑制27dB, IIP3为- 2dBm, NF为21.5dB，同时从1.2 v电源消耗11mA。该滤波器的芯片尺寸为0.5 mm × 0.5 mm。
{"title":"A new low-distortion transconductor applied in a flat band-pass filter","authors":"Ha Le-Thai, Huy-Hieu Nguyen, Hoai-Nam Nguyen, Hongrae Cho, Jeong-Seon Lee, Sang-Gug Lee","doi":"10.1109/ASSCC.2009.5357259","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357259","url":null,"abstract":"A new linearity improvement technique is proposed to implement a low-distortion Gm-C band-pass filter working in high IF ranges. The purpose of the linearization technique is to eliminate Gm″ value of the transconductor by employing a superposition method that combines two opposite non-linear behaviors of the two parallel wings designed inside the transconductor. Instead of conventional biquad structure, a resonant-coupling structure is adopted for the band-pass filter working at center frequency of 80MHz to make the frequency response flat and stable and to allow a stable frequency tuning as well as a flexible bandwidth tuning. Fabricated in 65nm CMOS process, the implemented IF band-pass filter provides a flat band-pass whose ripple is smaller than 0.1dB, a third-order rejection of 27dB, an IIP3 of −2dBm, and a NF of 21.5dB, while consuming 11mA from 1.2-V supply. The filter occupies a chip size of 0.5 mm × 0.5 mm.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121736734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357248
Mitsuko Saito, Kazutaka Kasuga, Tsutomu Takeya, N. Miura, T. Kuroda
Inductive-coupling link between stacked chips in a package communicates by using coils made by on-chip interconnections. An XY-coil layout style allows logic interconnections to go through the coil, which significantly saves interconnection resources consumed by the coil. However, the logic interconnections generate capacitive-coupling noise on the coil and degrade signal in the inductive-coupling link. In this paper, an extended XY coil with ground shields is presented for noise reduction. Simulation study shows that the noise voltage is reduced to 1/5 of the conventional XY coil. This noise reduction enables to reduce transmit power required for the same BER. Test-chip measurement in 0.18μm CMOS demonstrates that the transmit power at lGb/s with BER<10-12 is reduced by 60% compared to the conventional XY coil.
{"title":"An extended XY coil for noise reduction in inductive-coupling link","authors":"Mitsuko Saito, Kazutaka Kasuga, Tsutomu Takeya, N. Miura, T. Kuroda","doi":"10.1109/ASSCC.2009.5357248","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357248","url":null,"abstract":"Inductive-coupling link between stacked chips in a package communicates by using coils made by on-chip interconnections. An XY-coil layout style allows logic interconnections to go through the coil, which significantly saves interconnection resources consumed by the coil. However, the logic interconnections generate capacitive-coupling noise on the coil and degrade signal in the inductive-coupling link. In this paper, an extended XY coil with ground shields is presented for noise reduction. Simulation study shows that the noise voltage is reduced to 1/5 of the conventional XY coil. This noise reduction enables to reduce transmit power required for the same BER. Test-chip measurement in 0.18μm CMOS demonstrates that the transmit power at lGb/s with BER<10-12 is reduced by 60% compared to the conventional XY coil.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132833637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357251
Kazutaka Kasuga, Mitsuko Saito, Tsutomu Takeya, N. Miura, H. Ishikuro, T. Kuroda
This paper provides the method for Wafer test of an inductive-coupling link. The inductive-coupling link can be tested whether it operates correctly before stacking chips. We provided the method that verify the operation of an inductive-coupling link from the relation between coupling coefficient of inductors and power that transmitter consumes.
{"title":"A Wafer test method of inductive-coupling link","authors":"Kazutaka Kasuga, Mitsuko Saito, Tsutomu Takeya, N. Miura, H. Ishikuro, T. Kuroda","doi":"10.1109/ASSCC.2009.5357251","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357251","url":null,"abstract":"This paper provides the method for Wafer test of an inductive-coupling link. The inductive-coupling link can be tested whether it operates correctly before stacking chips. We provided the method that verify the operation of an inductive-coupling link from the relation between coupling coefficient of inductors and power that transmitter consumes.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134304474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357177
Ning Ma, Zhibo Pang, Jun Chen, H. Tenhunen, Lirong Zheng
A flexible and high performance SoC is developed for networked media applications by integrating two RISC cores, Ethernet interface and coarse-grained configurable video decoding unit. Real-time 1280×720@25fps MPEG-2/MPEG-4/RealVideo decoding is achieved for on-line video streams. The SoC is fabricated in 0.13um single-poly eight-metal CMOS technology with die size of 6.4mm × 6.4mm. To achieve low power design, flexible power management strategy is implemented including dynamic configuration of clock frequency synthesis and module level clock gating according to the workloads. The maximum power consumption is 414mW at 1.2V supply voltage with the corresponding system frequency of 216MHz, when real-time HD (1280×720@25fps) video streams are decoded. The power consumption is reduced to 95mW for real-time CIF (352×288@25fps) video stream decoding at 27MHz system frequency.
{"title":"A 5Mgate/414mW networked media SoC in 0.13um CMOS with 720p multi-standard video decoding","authors":"Ning Ma, Zhibo Pang, Jun Chen, H. Tenhunen, Lirong Zheng","doi":"10.1109/ASSCC.2009.5357177","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357177","url":null,"abstract":"A flexible and high performance SoC is developed for networked media applications by integrating two RISC cores, Ethernet interface and coarse-grained configurable video decoding unit. Real-time 1280×720@25fps MPEG-2/MPEG-4/RealVideo decoding is achieved for on-line video streams. The SoC is fabricated in 0.13um single-poly eight-metal CMOS technology with die size of 6.4mm × 6.4mm. To achieve low power design, flexible power management strategy is implemented including dynamic configuration of clock frequency synthesis and module level clock gating according to the workloads. The maximum power consumption is 414mW at 1.2V supply voltage with the corresponding system frequency of 216MHz, when real-time HD (1280×720@25fps) video streams are decoded. The power consumption is reduced to 95mW for real-time CIF (352×288@25fps) video stream decoding at 27MHz system frequency.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115446962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357148
M. Uchiyama, Kohei Oikawa, Naoto Date, Shin-ichiro Koto
We propose a rate-controllable near-lossless embedded compression algorithm "TLS-1". The algorithm guarantees a selected compression ratio with the smart combination of variable length coding and fixed length coding. It achieves near-lossless image quality under CR = 2. We apply the algorithm to an IP in an HDTV decoder LSI in order to reduce the required external memory capacity and its bandwidth. The LSI is fabricated in a 65nm CMOS technology.
{"title":"A rate-controllable near-lossless data compression IP for HDTV decoder LSI in 65nm CMOS","authors":"M. Uchiyama, Kohei Oikawa, Naoto Date, Shin-ichiro Koto","doi":"10.1109/ASSCC.2009.5357148","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357148","url":null,"abstract":"We propose a rate-controllable near-lossless embedded compression algorithm \"TLS-1\". The algorithm guarantees a selected compression ratio with the smart combination of variable length coding and fixed length coding. It achieves near-lossless image quality under CR = 2. We apply the algorithm to an IP in an HDTV decoder LSI in order to reduce the required external memory capacity and its bandwidth. The LSI is fabricated in a 65nm CMOS technology.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114059859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 μm CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.
{"title":"A 439K gates/10.9KB SRAM/2–328 mW dual mode video decoder supporting temporal/spatial scalable video","authors":"Cheng-An Chien, Yao-Chang Yang, Hsiu-Cheng Chang, Jiun-In Guo, Jia-Wei Chen, Jinn-Shan Wang, Chin-Hsien Wang, H. Huang, Ching-Hwa Cheng","doi":"10.1109/ASSCC.2009.5357147","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357147","url":null,"abstract":"The first dual mode video decoder with 4-level temporal/spatial scalability and 32/64-bit adjustable memory bus width is proposed. A design automation environment of simulation and verification is established to automatically verify the correctness and completeness of the proposed design. Using a 0.13 μm CMOS technology, it comprises 439Kgates/10.9KB SRAM and consumes 2~328mW in decoding CIF~HD1080 videos at 3.75~30fps when operating at 1~150MHz, respectively.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128271508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357189
Tomoyuki Takahashi, T. Uezono, Michihiro Shintani, K. Masu, Takashi Sato
Device-parameter estimation through path-delay measurement, which facilitates fast on-die performance prediction and diagnosis, is proposed. With the proposed technique, delays of a set of paths consisting of different logic cells are monitored. Based on the pre-characterized parameter to delay sensitivity, the process variation of a chip is estimated as an inverse problem. Discussion of desirable logic cell combination to form paths that maximize estimation accuracy is presented. Measurement of ring oscillator arrays composed of standard and customized logic cells resulted in consistent estimation of threshold voltages. Measurement accuracy is greatly enhanced by the proposed good logic cell combinations.
{"title":"On-die parameter extraction from path-delay measurements","authors":"Tomoyuki Takahashi, T. Uezono, Michihiro Shintani, K. Masu, Takashi Sato","doi":"10.1109/ASSCC.2009.5357189","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357189","url":null,"abstract":"Device-parameter estimation through path-delay measurement, which facilitates fast on-die performance prediction and diagnosis, is proposed. With the proposed technique, delays of a set of paths consisting of different logic cells are monitored. Based on the pre-characterized parameter to delay sensitivity, the process variation of a chip is estimated as an inverse problem. Discussion of desirable logic cell combination to form paths that maximize estimation accuracy is presented. Measurement of ring oscillator arrays composed of standard and customized logic cells resulted in consistent estimation of threshold voltages. Measurement accuracy is greatly enhanced by the proposed good logic cell combinations.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122613353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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