Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357166
Jeong-Cheol Lee, Myung-woon Hwang, Seokyong Hong, Moonkyung Ahn, S. Jeong, Y. Oh, Seungbum Lim, Hyunha Cho, Je-cheol Moon, Jong-Ryul Lee, Sangwoo Han, Che Handa, T. Fujie, Katsuya Hashimoto, Kengo Tamukai
This paper presents a 1.2 V 57 mW SoC using a 90 nm CMOS process in mobile ISDB-T application. This achieves −98.5 dBm sensitivity at QPSK, CR = −2/3 with 2.5 dB NF of RF tuner block and 5.6 dB C/N of OFDM block at UHF-band. To integrate RF tuner and OFDM in a small single die, a wideband single LC-VCO operating from 1.8 GHz to 3.3 GHz is proposed and OFDM is designed by hard-wired logic.
本文提出了一种采用90 nm CMOS工艺的1.2 V 57 mW SoC，用于移动ISDB-T应用。该方法在QPSK时达到了- 98.5 dBm的灵敏度，在RF调谐器块的2.5 dB NF和uhf频段OFDM块的5.6 dB C/N下，CR = - 2/3。为了将射频调谐器和OFDM集成到一个小的单芯片中，提出了一种工作频率为1.8 GHz ~ 3.3 GHz的宽带单LC-VCO，并采用硬接线逻辑设计了OFDM。
{"title":"A 1.2V 57mW mobile ISDB-T SoC in 90nm CMOS","authors":"Jeong-Cheol Lee, Myung-woon Hwang, Seokyong Hong, Moonkyung Ahn, S. Jeong, Y. Oh, Seungbum Lim, Hyunha Cho, Je-cheol Moon, Jong-Ryul Lee, Sangwoo Han, Che Handa, T. Fujie, Katsuya Hashimoto, Kengo Tamukai","doi":"10.1109/ASSCC.2009.5357166","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357166","url":null,"abstract":"This paper presents a 1.2 V 57 mW SoC using a 90 nm CMOS process in mobile ISDB-T application. This achieves −98.5 dBm sensitivity at QPSK, CR = −2/3 with 2.5 dB NF of RF tuner block and 5.6 dB C/N of OFDM block at UHF-band. To integrate RF tuner and OFDM in a small single die, a wideband single LC-VCO operating from 1.8 GHz to 3.3 GHz is proposed and OFDM is designed by hard-wired logic.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131656059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fully digital controlled low-EMI switching converter combining RPPM (Random Pulse Position Modulation), our improved version of Hybrid DPWM (Digital Pulse Width Modulator) and AEDPWM (Area-Efficient DPWM) schemes is proposed to achieve low-EMI (Electromagnetic Interference) with reduced area and power consumption. A FPGA-controlled prototype buck converter operating at 1 MHz switching frequency with 1.8 V input voltage and 0.6–1.2V output voltage is presented to demonstrate the technique. The resulting switching noise suppression capability is up to 18 dB in average.
{"title":"Digitally controlled low-EMI switching converter with random pulse position modulation","authors":"Jui-Chi Wu, Chin-Wei Mu, Chun-Hung Yang, Chien-Hung Tsai","doi":"10.1109/ASSCC.2009.5357164","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357164","url":null,"abstract":"A fully digital controlled low-EMI switching converter combining RPPM (Random Pulse Position Modulation), our improved version of Hybrid DPWM (Digital Pulse Width Modulator) and AEDPWM (Area-Efficient DPWM) schemes is proposed to achieve low-EMI (Electromagnetic Interference) with reduced area and power consumption. A FPGA-controlled prototype buck converter operating at 1 MHz switching frequency with 1.8 V input voltage and 0.6–1.2V output voltage is presented to demonstrate the technique. The resulting switching noise suppression capability is up to 18 dB in average.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"36 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134259166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357144
A. Kotabe, Y. Yanagawa, S. Akiyama, T. Sekiguchi
A novel CMOS low-VT preamplifier suitable for low-voltage and high-speed mid-point sensing was developed for gigabit DRAM. This preamplifier consists of a low-VT NMOS cross couple, a low-VT PMOS cross couple and a high-VT CMOS latch. The sensing speed of the proposed preamplifier at dataline voltage of 0.5 V is 62% higher than that of a conventional preamplifier. By activating the low-VT NMOS and PMOS cross couples temporarily during write operation, writing time is 72% shorter compared to the case with the high-VT CMOS latch only. Data-line charging current of a memory cell array with the proposed preamplifier is reduced by 26% by decreasing dataline voltage from 0.8 to 0.5V.
{"title":"CMOS low-VT preamplifier for 0.5-V gigabit-DRAM arrays","authors":"A. Kotabe, Y. Yanagawa, S. Akiyama, T. Sekiguchi","doi":"10.1109/ASSCC.2009.5357144","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357144","url":null,"abstract":"A novel CMOS low-VT preamplifier suitable for low-voltage and high-speed mid-point sensing was developed for gigabit DRAM. This preamplifier consists of a low-VT NMOS cross couple, a low-VT PMOS cross couple and a high-VT CMOS latch. The sensing speed of the proposed preamplifier at dataline voltage of 0.5 V is 62% higher than that of a conventional preamplifier. By activating the low-VT NMOS and PMOS cross couples temporarily during write operation, writing time is 72% shorter compared to the case with the high-VT CMOS latch only. Data-line charging current of a memory cell array with the proposed preamplifier is reduced by 26% by decreasing dataline voltage from 0.8 to 0.5V.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132441071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357258
Y. Takamatsu, R. Fujimoto, T. Yasuda, T. Sekine, T. Hirakawa, M. Ishii, M. Hayashi, N. Itoh
This paper presents a tunable low-noise amplifier (LNA) for digital TV (ISDB-T) applications. To receive all channels from 470MHz to 770MHz and to relax distortion characteristics of following circuit blocks such as an RF variable-gain amplifier and a mixer, tunable techniques for LNAs are required. A novel output matching configuration for tunable LNAs is proposed, and an input matching technique is also described. A tunable LNA using the proposed tunable techniques is fabricated using 90nm CMOS technology. Measured results show the proposed techniques are suitable for the LNAs for the ISDB-T.
{"title":"A tunable low-noise amplifier for digital TV applications","authors":"Y. Takamatsu, R. Fujimoto, T. Yasuda, T. Sekine, T. Hirakawa, M. Ishii, M. Hayashi, N. Itoh","doi":"10.1109/ASSCC.2009.5357258","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357258","url":null,"abstract":"This paper presents a tunable low-noise amplifier (LNA) for digital TV (ISDB-T) applications. To receive all channels from 470MHz to 770MHz and to relax distortion characteristics of following circuit blocks such as an RF variable-gain amplifier and a mixer, tunable techniques for LNAs are required. A novel output matching configuration for tunable LNAs is proposed, and an input matching technique is also described. A tunable LNA using the proposed tunable techniques is fabricated using 90nm CMOS technology. Measured results show the proposed techniques are suitable for the LNAs for the ISDB-T.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128920785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357161
Chun-Yen Tseng, Po-Chiun Huang, Li-Wen Wang
This work presents a fully integrated linear regulator design that can dynamically assign the SRAM cell voltage to increase the read/write margin. To minimize the timing overhead between read/write mode switches, this design adopts two separate feedback loops for bias and load regulations. Individual optimization for each loop makes fast reference tracking and load regulation possible. To verify this concept, a prototype LDO is realized with a 1.8-V 0.18μm CMOS. The output voltage can be freely set between 0.9 and 1.7-V. The measured transition speed is 48ns/0.3V. The maximum current efficiency is 94.7% under a 20mA current loading.
这项工作提出了一个完全集成的线性调节器设计，可以动态分配SRAM单元电压以增加读/写余量。为了最大限度地减少读/写模式切换之间的时间开销，该设计采用两个单独的反馈回路来调节偏置和负载。每个回路的单独优化使快速参考跟踪和负载调节成为可能。为了验证这一概念，采用1.8 v 0.18μm CMOS实现了LDO原型。输出电压可在0.9 ~ 1.7 v之间自由设定。测量到的转变速度为48ns/0.3V。在20mA电流负载下，最大电流效率为94.7%。
{"title":"An integrated linear regulator with fast output voltage transition for SRAM yield improvement","authors":"Chun-Yen Tseng, Po-Chiun Huang, Li-Wen Wang","doi":"10.1109/ASSCC.2009.5357161","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357161","url":null,"abstract":"This work presents a fully integrated linear regulator design that can dynamically assign the SRAM cell voltage to increase the read/write margin. To minimize the timing overhead between read/write mode switches, this design adopts two separate feedback loops for bias and load regulations. Individual optimization for each loop makes fast reference tracking and load regulation possible. To verify this concept, a prototype LDO is realized with a 1.8-V 0.18μm CMOS. The output voltage can be freely set between 0.9 and 1.7-V. The measured transition speed is 48ns/0.3V. The maximum current efficiency is 94.7% under a 20mA current loading.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128190710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357168
Kuan-Chao Liao, Po-Sheng Huang, W. Chiu, Tsung-Hsien Lin
A multi-band FSK transmitter (Tx) is presented in this paper. The Tx is designed to operate at the ISM frequency bands at 433/868/915 MHz, 2.4 GHz, and MICS band at 402~405 MHz, and supports a data rate well over 1 Mbps. The Tx adopts an analog modulator which allows a deviation frequency ranging from 714 kHz to 3.2 MHz. In addition, this work proposes an inductor-less wideband mixer and a voltage-controlled oscillator to save the chip area. Fabricated in a 0.18-μm CMOS process, the proposed Tx consumes 8.9 mA to 12 mA from a 1.8-V supply voltage at different frequency bands. The measured FSK errors range from 13.9 % to 15.4 %, which are adequate for most low-cost wireless applications. The proposed multi-band Tx occupies an area of 1.6 mm × 1.9 mm.
{"title":"A 400-MHz/900-MHz/2.4-GHz multi-band FSK transmitter in 0.18-μm CMOS","authors":"Kuan-Chao Liao, Po-Sheng Huang, W. Chiu, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2009.5357168","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357168","url":null,"abstract":"A multi-band FSK transmitter (Tx) is presented in this paper. The Tx is designed to operate at the ISM frequency bands at 433/868/915 MHz, 2.4 GHz, and MICS band at 402~405 MHz, and supports a data rate well over 1 Mbps. The Tx adopts an analog modulator which allows a deviation frequency ranging from 714 kHz to 3.2 MHz. In addition, this work proposes an inductor-less wideband mixer and a voltage-controlled oscillator to save the chip area. Fabricated in a 0.18-μm CMOS process, the proposed Tx consumes 8.9 mA to 12 mA from a 1.8-V supply voltage at different frequency bands. The measured FSK errors range from 13.9 % to 15.4 %, which are adequate for most low-cost wireless applications. The proposed multi-band Tx occupies an area of 1.6 mm × 1.9 mm.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"751 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126946637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357169
Chul Kim, S. Nooshabadi
This paper introduces an ultra-wideband (UWB) system and its integrated circuit design for biotelemetry in-vivo wireless endoscope application that enables real-time diagnosis with high resolution images. The implemented UWB transmitter (Tx)/receiver (Rx) pair is a non-coherent differential transmit-reference (DTR) architecture. All-digital pulse generator (PG) Tx, and merged radio frequency (RF) Rx frond end including the low noise amplifier (LNA), mixer and low-pass filter (LPF) have been implemented along with the analog baseband using a 0.18um digital CMOS process. The PG operates at 200Mbps at an ultra low 27pJ/bit transmit energy.
{"title":"A DTR UWB transmitter/receiver pair for wireless endoscope","authors":"Chul Kim, S. Nooshabadi","doi":"10.1109/ASSCC.2009.5357169","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357169","url":null,"abstract":"This paper introduces an ultra-wideband (UWB) system and its integrated circuit design for biotelemetry in-vivo wireless endoscope application that enables real-time diagnosis with high resolution images. The implemented UWB transmitter (Tx)/receiver (Rx) pair is a non-coherent differential transmit-reference (DTR) architecture. All-digital pulse generator (PG) Tx, and merged radio frequency (RF) Rx frond end including the low noise amplifier (LNA), mixer and low-pass filter (LPF) have been implemented along with the analog baseband using a 0.18um digital CMOS process. The PG operates at 200Mbps at an ultra low 27pJ/bit transmit energy.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121890252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/ASSCC.2009.5357242
H. Tong
Today, as global environmental regulations are being tightened, both IC and package technologies are also becoming far more complicated. More Moore and more than Moore, which manifest themselves in system-on-chip (SoC) and system-in-a-package (SiP), respectively, are being used more in combination to meet the ever-more-stringent cost and time-to-market requirements of consumer products with more functions built in them. In this presentation, I will review the challenges and opportunities to IC packaging as a direct outcome of the above trends to ensure SoC and SiP based IC packages meet the needs of the present generation without compromising the ability of future generations.
今天，随着全球环境法规的收紧，IC和封装技术也变得更加复杂。更多的摩尔(More Moore)和更多的摩尔(More than Moore)分别体现在片上系统(SoC)和系统级封装(SiP)上，它们正被更多地结合使用，以满足内置更多功能的消费产品对成本和上市时间日益严格的要求。在本次演讲中，我将回顾IC封装的挑战和机遇，作为上述趋势的直接结果，以确保基于SoC和SiP的IC封装在不影响后代能力的情况下满足当前一代的需求。
{"title":"Green future: IC packaging opportunities abound","authors":"H. Tong","doi":"10.1109/ASSCC.2009.5357242","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357242","url":null,"abstract":"Today, as global environmental regulations are being tightened, both IC and package technologies are also becoming far more complicated. More Moore and more than Moore, which manifest themselves in system-on-chip (SoC) and system-in-a-package (SiP), respectively, are being used more in combination to meet the ever-more-stringent cost and time-to-market requirements of consumer products with more functions built in them. In this presentation, I will review the challenges and opportunities to IC packaging as a direct outcome of the above trends to ensure SoC and SiP based IC packages meet the needs of the present generation without compromising the ability of future generations.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129752223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-11-01DOI: 10.1109/ASSCC.2009.5357219
M. Sinangil, N. Verma, A. Chandrakasan
8T bit-cells hold great promise for overcoming device variability in deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8T test array fabricated in 45nm CMOS achieves functionality from 1.1V to below 0.5V. Test chip operates at 450MHz at 1.1V and 5.8MHz at 0.5V while consuming 12.9mW and 46μW respectively.
{"title":"A 45nm 0.5V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier","authors":"M. Sinangil, N. Verma, A. Chandrakasan","doi":"10.1109/ASSCC.2009.5357219","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357219","url":null,"abstract":"8T bit-cells hold great promise for overcoming device variability in deeply scaled SRAMs and enabling aggressive voltage scaling for ultra-low-power. This paper presents an array architecture and circuits with minimal area overhead to allow column-interleaving while eliminating the half-select problem. This enables sense-amplifier sharing and soft-error immunity. A reference selection loop is designed and implemented in the column circuitry. By choosing one of the two reference voltages for each sense-amplifier in a pseudo-differential scheme, selection loop effectively reduces input offset. 8T test array fabricated in 45nm CMOS achieves functionality from 1.1V to below 0.5V. Test chip operates at 450MHz at 1.1V and 5.8MHz at 0.5V while consuming 12.9mW and 46μW respectively.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130850384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/asscc.2009.5357181
Yi-Da Wu, Po-Chiun Huang
This work presents a quantization error minimization technique for a fractional-N frequency synthesizer. By using a direct digital synthesis phase accumulator as the fractional divider and a DAC as pulse conversion, the quantization error can be much smaller than the one by conventional Σ-Δ modulated multi-modulus divider. With small quantization error, dedicated compensation mechanism is no longer necessary for wide loop bandwidth applications. To demonstrate this concept, a prototype chip is realized with the 0.18μm CMOS. The synthesizer consumes 31mA under a single 1.8V supply. With 1MHz closed-loop bandwidth, the in-band noise is −94dBc/Hz and the 3MHz offset noise is −118dBc/Hz for the 1.8GHz output. The output exhibits 27dB phase noise reduction. The settling time is 2μs under a 35MHz frequency step.
{"title":"A quantization error minimization using DDS-DAC for wideband fractional-N frequency synthesizer","authors":"Yi-Da Wu, Po-Chiun Huang","doi":"10.1109/asscc.2009.5357181","DOIUrl":"https://doi.org/10.1109/asscc.2009.5357181","url":null,"abstract":"This work presents a quantization error minimization technique for a fractional-N frequency synthesizer. By using a direct digital synthesis phase accumulator as the fractional divider and a DAC as pulse conversion, the quantization error can be much smaller than the one by conventional Σ-Δ modulated multi-modulus divider. With small quantization error, dedicated compensation mechanism is no longer necessary for wide loop bandwidth applications. To demonstrate this concept, a prototype chip is realized with the 0.18μm CMOS. The synthesizer consumes 31mA under a single 1.8V supply. With 1MHz closed-loop bandwidth, the in-band noise is −94dBc/Hz and the 3MHz offset noise is −118dBc/Hz for the 1.8GHz output. The output exhibits 27dB phase noise reduction. The settling time is 2μs under a 35MHz frequency step.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126153401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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