Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357184
Shoichi Hara, K. Okada, A. Matsuzawa
This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed oscillator has a core VCO and a tuning-range extension circuit, which consists of an injection-locked frequency divider (ILFD), and flip flop dividers. The 2-stage differential ILFD can generate quadrature outputs, and it realizes 2, 3, 4, and 6 of divide ratio with very wide output frequency range. The proposed circuit is implemented by using a 90nm CMOS process, and the chip area is 250μm × 200 μm. The measured results achieves 9.3 MHz-to-5.7 GHz (199%) of continuous frequency tuning range with −210 dBc/Hz of FoMT.
{"title":"A 9.3MHz to 5.7GHz tunable LC-based VCO using a divide-by-N injection-locked frequency divider","authors":"Shoichi Hara, K. Okada, A. Matsuzawa","doi":"10.1109/ASSCC.2009.5357184","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357184","url":null,"abstract":"This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed oscillator has a core VCO and a tuning-range extension circuit, which consists of an injection-locked frequency divider (ILFD), and flip flop dividers. The 2-stage differential ILFD can generate quadrature outputs, and it realizes 2, 3, 4, and 6 of divide ratio with very wide output frequency range. The proposed circuit is implemented by using a 90nm CMOS process, and the chip area is 250μm × 200 μm. The measured results achieves 9.3 MHz-to-5.7 GHz (199%) of continuous frequency tuning range with −210 dBc/Hz of FoMT.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124595632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357199
Yanfei Chen, Sanroku Tsukamoto, T. Kuroda
A 9b 100MS/s successive approximation register (SAR) ADC has been implemented in 65nm CMOS, with an active area of 0.012mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1dB (8.53 ENOB) and consumes 1.46mW from a 1.2V supply, resulting in an FOM of 39fJ/conversion-step.
{"title":"A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS","authors":"Yanfei Chen, Sanroku Tsukamoto, T. Kuroda","doi":"10.1109/ASSCC.2009.5357199","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357199","url":null,"abstract":"A 9b 100MS/s successive approximation register (SAR) ADC has been implemented in 65nm CMOS, with an active area of 0.012mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1dB (8.53 ENOB) and consumes 1.46mW from a 1.2V supply, resulting in an FOM of 39fJ/conversion-step.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124595719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357257
D. Ikebuchi, N. Seki, Y. Kojima, M. Kamata, L. Zhao, H. Amano, T. Shirai, S. Koyama, T. Hashida, Y. Umahashi, H. Masuda, K. Usami, S. Takeda, H. Nakamura, M. Namiki, M. Kondo
Geyser-1, a prototype MIPS R3000 CPU with fine grain runtime PG for major computational components in the execution stage is available. Function units such as CLU, shifter, multiplier and divider are power-gated and controlled at runtime such that only the function unit to be used is powered-on to minimize the leakage power. The evaluation results on the real chip reveals that the fine grain runtime PG mechanism works without electric problems. It reduces the leakage power 7% at 25 °C and 24% at 80°C. The evaluation results using benchmark programs show that the power consumption can be reduced from 3% at 25 °C and 30% at 80°C.
{"title":"Geyser-1: A MIPS R3000 CPU core with fine grain runtime power gating","authors":"D. Ikebuchi, N. Seki, Y. Kojima, M. Kamata, L. Zhao, H. Amano, T. Shirai, S. Koyama, T. Hashida, Y. Umahashi, H. Masuda, K. Usami, S. Takeda, H. Nakamura, M. Namiki, M. Kondo","doi":"10.1109/ASSCC.2009.5357257","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357257","url":null,"abstract":"Geyser-1, a prototype MIPS R3000 CPU with fine grain runtime PG for major computational components in the execution stage is available. Function units such as CLU, shifter, multiplier and divider are power-gated and controlled at runtime such that only the function unit to be used is powered-on to minimize the leakage power. The evaluation results on the real chip reveals that the fine grain runtime PG mechanism works without electric problems. It reduces the leakage power 7% at 25 °C and 24% at 80°C. The evaluation results using benchmark programs show that the power consumption can be reduced from 3% at 25 °C and 30% at 80°C.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126444773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357170
T. Teo, P. K. Gopalakrishnan, Y. S. Hwan, X. Qian, K. Haridas, C. Pang, M. Je
A sensor node was designed and implemented in 0.18 μm CMOS process. The sensor node consists of a sensor interface circuit, an analog-to-digital converter (ADC), a digital signal processor (DSP) unit and a radio-frequency (RF) transmitter unit. The sensor node was designed for use in a wireless health monitoring system. Minimal off-chip components are allowed in this implementation for improved user experience, which are antenna, crystal resonator and supply decoupling capacitors. Low-power low-voltage design techniques such as sub-threshold design were employed intensively to minimize the power consumption of the sensor node IC and maximize the battery life. The sensor consumes only about 700 µW at 0.7 V supply and it enables continuous-and real-time electrocardiogram (ECG) monitoring for more than 200 hours without changing the battery when a typical button-cell battery is used.
{"title":"A 700-μW single-chip IC for wireless continuous-time health monitoring in 0.18-μm CMOS","authors":"T. Teo, P. K. Gopalakrishnan, Y. S. Hwan, X. Qian, K. Haridas, C. Pang, M. Je","doi":"10.1109/ASSCC.2009.5357170","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357170","url":null,"abstract":"A sensor node was designed and implemented in 0.18 μm CMOS process. The sensor node consists of a sensor interface circuit, an analog-to-digital converter (ADC), a digital signal processor (DSP) unit and a radio-frequency (RF) transmitter unit. The sensor node was designed for use in a wireless health monitoring system. Minimal off-chip components are allowed in this implementation for improved user experience, which are antenna, crystal resonator and supply decoupling capacitors. Low-power low-voltage design techniques such as sub-threshold design were employed intensively to minimize the power consumption of the sensor node IC and maximize the battery life. The sensor consumes only about 700 µW at 0.7 V supply and it enables continuous-and real-time electrocardiogram (ECG) monitoring for more than 200 hours without changing the battery when a typical button-cell battery is used.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"167 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132503080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357244
Ho-Young Song, Hankyu Chi, Heesoo Song, D. Jeong
A 1.3-MHz to 330-MHz video clock synthesizer consisting of a fine-resolution fractional frequency divider and a divider-merged delta-sigma modulator (DSM) is presented. The proposed architecture provides a wide frequency range of output clock, and good jitter performance with reduced design complexity. Moreover, the divider-merged DSM guarantees the cycle-accurate frequency synthesis. The proposed fractional divider can divide the clock frequency with 4-bit fractional resolution using the proposed phase-switching technique. Fabricated in a 0.13-μm CMOS technology, the synthesizer has maximum peak-to-peak period jitter of 120 ps.
{"title":"A 1.3–330-MHz direct clock synthesizer for display interface using fractional multimodulus frequency divider","authors":"Ho-Young Song, Hankyu Chi, Heesoo Song, D. Jeong","doi":"10.1109/ASSCC.2009.5357244","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357244","url":null,"abstract":"A 1.3-MHz to 330-MHz video clock synthesizer consisting of a fine-resolution fractional frequency divider and a divider-merged delta-sigma modulator (DSM) is presented. The proposed architecture provides a wide frequency range of output clock, and good jitter performance with reduced design complexity. Moreover, the divider-merged DSM guarantees the cycle-accurate frequency synthesis. The proposed fractional divider can divide the clock frequency with 4-bit fractional resolution using the proposed phase-switching technique. Fabricated in a 0.13-μm CMOS technology, the synthesizer has maximum peak-to-peak period jitter of 120 ps.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116416041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357157
Wei-Ming Lin, K. Teng, Shen-Iuan Liu
A delay-locked loop (DLL) with digital background calibration is presented. The static phase error of a DLL may exist owing to the current mismatch in the charge pump (CP). A digital background calibration using the time amplifier is presented. This DLL is fabricated in a CMOS 0.18μm technology. The measured input frequency range of this DLL is from 400MHz to 525MHz. The measured static phase error without and with calibration is 113.8ps and 27.8ps, respectively, at 525MHz. The measured peak-to-peak jitter without and with calibration is 15.56ps and 15.11ps, respectively. The power consumption is 25.2mW at 500MHz and the area is 0.85mm2.
{"title":"A delay-locked loop with digital background calibration","authors":"Wei-Ming Lin, K. Teng, Shen-Iuan Liu","doi":"10.1109/ASSCC.2009.5357157","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357157","url":null,"abstract":"A delay-locked loop (DLL) with digital background calibration is presented. The static phase error of a DLL may exist owing to the current mismatch in the charge pump (CP). A digital background calibration using the time amplifier is presented. This DLL is fabricated in a CMOS 0.18μm technology. The measured input frequency range of this DLL is from 400MHz to 525MHz. The measured static phase error without and with calibration is 113.8ps and 27.8ps, respectively, at 525MHz. The measured peak-to-peak jitter without and with calibration is 15.56ps and 15.11ps, respectively. The power consumption is 25.2mW at 500MHz and the area is 0.85mm2.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125454669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357200
Wen-Yi Pang, Chao-Shiun Wang, You-Kuang Chang, N. Chou, Chorng-Kuang Wang
This paper presents a successive approximation register analog-to-digital converter (SAR ADC) design for bio-medical applications. Splitting comparator and energy saving capacitor array are proposed to achieve low power consumption. The average switching energy of the capacitor array can be reduced by 69% compared to a conventional switching method. The measured signal-to-noise-and-distortion ratios of the ADC is 58.4 dB at 500KS/s sampling rate with an ultra-low power consumption of 42-μW from a 1-V supply voltage. The ADC is fabricated in a 0.18-μm CMOS technology.
{"title":"A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications","authors":"Wen-Yi Pang, Chao-Shiun Wang, You-Kuang Chang, N. Chou, Chorng-Kuang Wang","doi":"10.1109/ASSCC.2009.5357200","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357200","url":null,"abstract":"This paper presents a successive approximation register analog-to-digital converter (SAR ADC) design for bio-medical applications. Splitting comparator and energy saving capacitor array are proposed to achieve low power consumption. The average switching energy of the capacitor array can be reduced by 69% compared to a conventional switching method. The measured signal-to-noise-and-distortion ratios of the ADC is 58.4 dB at 500KS/s sampling rate with an ultra-low power consumption of 42-μW from a 1-V supply voltage. The ADC is fabricated in a 0.18-μm CMOS technology.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122240091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357256
Wei-Chang Liu, Chih-Hsien Lin, S. Jou, Hungwen Lu, Chau-chin Su, Kai-Wei Hong, Kuo-Hsing Cheng, Shyue-Wen Yang, M. Sheu
In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13μm CMOS technology. The core area of this chip is 990μm∗1600μm and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.
{"title":"A micro-network on chip with 10-Gb/s transmission link","authors":"Wei-Chang Liu, Chih-Hsien Lin, S. Jou, Hungwen Lu, Chau-chin Su, Kai-Wei Hong, Kuo-Hsing Cheng, Shyue-Wen Yang, M. Sheu","doi":"10.1109/ASSCC.2009.5357256","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357256","url":null,"abstract":"In this paper, a micro-network on chip (MNoC) with 10-Gb/s transmission link is proposed. A prototype system with two 5-port packet-based on-chip micro-switches and a 10-Gb/s data transceiver with an all digital data recovery circuit and a self-calibration clock generator are designed. This chip is implemented in 0.13μm CMOS technology. The core area of this chip is 990μm∗1600μm and the power consumption is 155mW (60mW for micro-switches and 95mW for 10-Gb/s data transceiver) at 1.2V supply voltage with 10-Gb/s transmission data rate.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122326399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357222
C. Chien, C. Hung, Chia-Wei Chen
This paper presents a fully balanced structure of a CMOS operational transconductance amplifier (OTA) with high linearity for frequency up to 50MHz. The proposed circuit is based on a conventional pseudo-differential structure with a third-order harmonic distortion (HD3) feedforward technique to cancel out the output 3rd harmonic component. The OTA was fabricated in the TSMC CMOS 0.18μm technology. The measurement results show the HD3 of −62dB with 0.4-Vpp 50MHz input signal and the power consumption of 0.47mW at a 1.2-V voltage supply.
{"title":"A pseudo-differential OTA with linearity improving by HD3 feedforward","authors":"C. Chien, C. Hung, Chia-Wei Chen","doi":"10.1109/ASSCC.2009.5357222","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357222","url":null,"abstract":"This paper presents a fully balanced structure of a CMOS operational transconductance amplifier (OTA) with high linearity for frequency up to 50MHz. The proposed circuit is based on a conventional pseudo-differential structure with a third-order harmonic distortion (HD3) feedforward technique to cancel out the output 3rd harmonic component. The OTA was fabricated in the TSMC CMOS 0.18μm technology. The measurement results show the HD3 of −62dB with 0.4-Vpp 50MHz input signal and the power consumption of 0.47mW at a 1.2-V voltage supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128427566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357153
Guo-Wei Wu, Wei-Zen Chen, Shih-Hao Huang
An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 μm CMOS technology, the chip size is 0.62 mm × 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.
{"title":"An 8 Gbps fast-locked automatic gain control for PAM receiver","authors":"Guo-Wei Wu, Wei-Zen Chen, Shih-Hao Huang","doi":"10.1109/ASSCC.2009.5357153","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357153","url":null,"abstract":"An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 μm CMOS technology, the chip size is 0.62 mm × 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127770253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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