Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357225
Dong Han, Yuanjin Zheng
An ultra-low power mixed-signal Gaussian frequency shift keying (GFSK) demodulator for wireless body area networks (WBAN) is introduced. A novel multi-threshold instant phase zero-crossing detector (MIPZCD) which is composed of a 2-stage poly-phase filter (PPF), an instant phase calculator and an adaptive multi-threshold quantizer is proposed to improve the demodulator phase accuracy and data rate. The measured results show that the demodulator achieves the data rate up to 2Mbps and the input frequency range from 1.6MHz to 2.5MHz. The measured signal-to-noise ratio (SNR) for 0.1% bit error rate (BER) with the GFSK signal of 1Mbps data rate, 2MHz center frequency, and 160kHz frequency deviation is 15.8dB. The demodulator has been implemented in 0.18-μm CMOS process with only 0.23mm2 active area and 410μA drain current from a 1.8V power supply.
{"title":"A GFSK demodulator based on instant phase computation and adaptive multi-threshold quantization","authors":"Dong Han, Yuanjin Zheng","doi":"10.1109/ASSCC.2009.5357225","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357225","url":null,"abstract":"An ultra-low power mixed-signal Gaussian frequency shift keying (GFSK) demodulator for wireless body area networks (WBAN) is introduced. A novel multi-threshold instant phase zero-crossing detector (MIPZCD) which is composed of a 2-stage poly-phase filter (PPF), an instant phase calculator and an adaptive multi-threshold quantizer is proposed to improve the demodulator phase accuracy and data rate. The measured results show that the demodulator achieves the data rate up to 2Mbps and the input frequency range from 1.6MHz to 2.5MHz. The measured signal-to-noise ratio (SNR) for 0.1% bit error rate (BER) with the GFSK signal of 1Mbps data rate, 2MHz center frequency, and 160kHz frequency deviation is 15.8dB. The demodulator has been implemented in 0.18-μm CMOS process with only 0.23mm2 active area and 410μA drain current from a 1.8V power supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124050135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 1.0 TOPS image stream processor, which deals with image processing tasks for multimedia content analysis, is implemented with 2.2mm2 area in 90nm CMOS technology. Two sub processors, linear processor and order processor, are integrated to achieve tera-scale performance. In the proposed SoC architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. Based on the memory architecture, the maximum input data rate of the proposed image stream processor reaches 62.5 Gpixel/s, which meets the requirements for real-time HDTV image processing.
{"title":"Tera-scale performance image stream processor with SoC architecture for multimedia content analysis","authors":"Tse-Wei Chen, Chi-Sun Tang, Sung-Fang Tsai, Chen-Han Tsai, Shao-Yi Chien, Liang-Gee Chen","doi":"10.1109/ASSCC.2009.5357149","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357149","url":null,"abstract":"A 1.0 TOPS image stream processor, which deals with image processing tasks for multimedia content analysis, is implemented with 2.2mm2 area in 90nm CMOS technology. Two sub processors, linear processor and order processor, are integrated to achieve tera-scale performance. In the proposed SoC architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. Based on the memory architecture, the maximum input data rate of the proposed image stream processor reaches 62.5 Gpixel/s, which meets the requirements for real-time HDTV image processing.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"2015 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132059742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357198
Y. Asada, K. Yoshihara, Tatsuya Urano, M. Miyahara, A. Matsuzawa
A 6 bit, 7 mW, 700 MS /s subranging ADC fabricated in 90 nm CMOS technology with SNDR of 34 dB for Nyquist input frequency is presented. The subranging architecture using CDACs, gate-weighted interpolation scheme, and digitally offset calibrating double-tail latched comparators has demonstrated an ultra low FoM of 250 fJ/conv. steps. and attractiveness for embedded IP for low power SoCs.
{"title":"A 6bit, 7mW, 250fJ, 700MS/s subranging ADC","authors":"Y. Asada, K. Yoshihara, Tatsuya Urano, M. Miyahara, A. Matsuzawa","doi":"10.1109/ASSCC.2009.5357198","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357198","url":null,"abstract":"A 6 bit, 7 mW, 700 MS /s subranging ADC fabricated in 90 nm CMOS technology with SNDR of 34 dB for Nyquist input frequency is presented. The subranging architecture using CDACs, gate-weighted interpolation scheme, and digitally offset calibrating double-tail latched comparators has demonstrated an ultra low FoM of 250 fJ/conv. steps. and attractiveness for embedded IP for low power SoCs.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130733697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357223
Byung‐Do Yang, Young-Kyu Shin, Jee-Sue Lee, Yong-Kyu Lee, K. Ryu
In this paper, an accurate current reference using temperature and process compensation current mirror (TPC-CM) is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current. The temperature coefficient and magnitude of the reference current are influenced by the process variation. To calibrate the process variation, the proposed TPC-CM uses two binary weighted current mirrors which control the temperature coefficient and magnitude of the reference current. After the PTAT and CTAT currents are measured, the switch codes of the TPC-CM are fixed in order that the magnitude of reference current is independent to temperature. And, the codes are stored in the non-volatile memory. In the simulation, the effect of the process variation is reduced to 0.52% from 19.7% after the calibration using a TPC-CM in chip-by-chip. A current reference chip is fabricated with a 3.3V 0.35um CMOS process. The measured calibrated reference current has 0.42% variation.
{"title":"An accurate current reference using temperature and process compensation current mirror","authors":"Byung‐Do Yang, Young-Kyu Shin, Jee-Sue Lee, Yong-Kyu Lee, K. Ryu","doi":"10.1109/ASSCC.2009.5357223","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357223","url":null,"abstract":"In this paper, an accurate current reference using temperature and process compensation current mirror (TPC-CM) is proposed. The temperature independent reference current is generated by summing a proportional to absolute temperature (PTAT) current and a complementary to absolute temperature (CTAT) current. The temperature coefficient and magnitude of the reference current are influenced by the process variation. To calibrate the process variation, the proposed TPC-CM uses two binary weighted current mirrors which control the temperature coefficient and magnitude of the reference current. After the PTAT and CTAT currents are measured, the switch codes of the TPC-CM are fixed in order that the magnitude of reference current is independent to temperature. And, the codes are stored in the non-volatile memory. In the simulation, the effect of the process variation is reduced to 0.52% from 19.7% after the calibration using a TPC-CM in chip-by-chip. A current reference chip is fabricated with a 3.3V 0.35um CMOS process. The measured calibrated reference current has 0.42% variation.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114073472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357145
Yuta Okano, T. Shibata
A high-frame-rate dense motion vector field generation processor employing an efficient data manipulation scheme has been developed. The computation result of detecting a motion vector (MV) at each pixel location is reused in the adjacent location. As a result, the size of a best-match searching circuitry for MV detection has been reduced to 1/10 of that without data reuse. This allows us to implement two MV calculation units on a chip without area penalty, enabling dual MV generation at every clock cycle except for the initial period of over head processing. As a result, the frame rate has been increased by 23% as compared to the previous architecture [1], while the total number of transistors has been reduced by 41%. A prototype chip was designed and fabricated in a 0.18-μm 5-metal CMOS technology. It was experimentally demonstrated that the chip can generate motion vectors from all pixel sites of 256×256-size motion images at a frame rate of 1060 frames/sec with a clock frequency of 100 MHz.
{"title":"A high-frame-rate dense motion vector field generation processor with simplified best-match searching circuitries","authors":"Yuta Okano, T. Shibata","doi":"10.1109/ASSCC.2009.5357145","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357145","url":null,"abstract":"A high-frame-rate dense motion vector field generation processor employing an efficient data manipulation scheme has been developed. The computation result of detecting a motion vector (MV) at each pixel location is reused in the adjacent location. As a result, the size of a best-match searching circuitry for MV detection has been reduced to 1/10 of that without data reuse. This allows us to implement two MV calculation units on a chip without area penalty, enabling dual MV generation at every clock cycle except for the initial period of over head processing. As a result, the frame rate has been increased by 23% as compared to the previous architecture [1], while the total number of transistors has been reduced by 41%. A prototype chip was designed and fabricated in a 0.18-μm 5-metal CMOS technology. It was experimentally demonstrated that the chip can generate motion vectors from all pixel sites of 256×256-size motion images at a frame rate of 1060 frames/sec with a clock frequency of 100 MHz.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124988616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reports a successive-approximation analog-to-digital converter (ADC) with low input capacitance. The 10-bit prototype is fabricated in a 0.13-µm CMOS process. Compared to conventional successive approximation ADCs, the proposed ADC reduces the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in an FOM of 95 fJ/Conversion-step.
{"title":"A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance","authors":"Guan-Ying Huang, Chun-Cheng Liu, Ying-Zu Lin, Soon-Jyh Chang","doi":"10.1109/ASSCC.2009.5357202","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357202","url":null,"abstract":"This paper reports a successive-approximation analog-to-digital converter (ADC) with low input capacitance. The 10-bit prototype is fabricated in a 0.13-µm CMOS process. Compared to conventional successive approximation ADCs, the proposed ADC reduces the input capacitance to 1.2 pF for 10-bit resolution. At 12 MS/s and 1.2-V supply, this ADC consumes 0.32 mW and achieves an SNDR of 50.89 dB, resulting in an FOM of 95 fJ/Conversion-step.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"14 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123649404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357172
Tien-Yu Lo, Chuan-Cheng Hsiao, K. Hsueh, Hung-Sung Li
A 5-th order bandpass filter is implemented in this paper. The filter can perform SAW filter function required in the tuner. In this design, leap-frog synthesis is used and the Active-RC topology is implemented. To save power consumption, the amplifier with a smaller unity gain-bandwidth is designed, and a new quality-factor calibration strategy is presented to compensate the non-ideal effect of the filter. In addition, the accurate center frequency is obtained by adopting a modified frequency tuning scheme. The filter was fabricated in 65nm CMOS process, and consumes 23.5mW under 1-V supply.
{"title":"A 1-V 60MHz bandpass filter with quality-factor calibration in 65nm CMOS","authors":"Tien-Yu Lo, Chuan-Cheng Hsiao, K. Hsueh, Hung-Sung Li","doi":"10.1109/ASSCC.2009.5357172","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357172","url":null,"abstract":"A 5-th order bandpass filter is implemented in this paper. The filter can perform SAW filter function required in the tuner. In this design, leap-frog synthesis is used and the Active-RC topology is implemented. To save power consumption, the amplifier with a smaller unity gain-bandwidth is designed, and a new quality-factor calibration strategy is presented to compensate the non-ideal effect of the filter. In addition, the accurate center frequency is obtained by adopting a modified frequency tuning scheme. The filter was fabricated in 65nm CMOS process, and consumes 23.5mW under 1-V supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129914096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357196
Wei-Ming Lin, C. Lin, Shen-Iuan Liu
A second-order sigma-delta modulator has been implemented in 3μm low-temperature poly-silicon thin-film transistor (LTPS-TFT) technology. Since the LTPS-TFT operational amplifier has a low open-loop gain, a large offset voltage, and the poor linearity, the proposed comparator-based switched-capacitor integrator with correlated double sampling is adopted in the modulator. The whole modulator consumes 63.3mW from an 11.2V supply and occupies 26mm2 area. In a signal bandwidth of 1.56kHz for the touch panel application, the measured input dynamic range is 69dB and the measured peak signal-to-noise plus distortion ratio is 65.63dB with the duty-cycle control technique.
{"title":"A CBSC second-order sigma-delta modulator in 3μm LTPS-TFT technology","authors":"Wei-Ming Lin, C. Lin, Shen-Iuan Liu","doi":"10.1109/ASSCC.2009.5357196","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357196","url":null,"abstract":"A second-order sigma-delta modulator has been implemented in 3μm low-temperature poly-silicon thin-film transistor (LTPS-TFT) technology. Since the LTPS-TFT operational amplifier has a low open-loop gain, a large offset voltage, and the poor linearity, the proposed comparator-based switched-capacitor integrator with correlated double sampling is adopted in the modulator. The whole modulator consumes 63.3mW from an 11.2V supply and occupies 26mm2 area. In a signal bandwidth of 1.56kHz for the touch panel application, the measured input dynamic range is 69dB and the measured peak signal-to-noise plus distortion ratio is 65.63dB with the duty-cycle control technique.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121602856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357224
Hsin-Hong Hou, Chung-Wei Lin, Wentao Chen
This paper describes a robust PWM class D amplifier with high linearity and good immunity to process variations. By using the proposed adaptive triangular wave generator (ATG), 0.0042% THD+N and 99.2dB dynamic range is achieved in this design. The standard deviation of THD+N ratio over 22 samples can be smaller by 4 times compared to the results without the adaptive triangular wave generator. This chip integrates power MOS stages and 2 channel design. The supply voltage is from 3V to 5.5V and the die area is 2.45mm × 2.9mm.
{"title":"A robust continuous time loop filter PWM class D amplifier with high linearity and good immunity to process variations","authors":"Hsin-Hong Hou, Chung-Wei Lin, Wentao Chen","doi":"10.1109/ASSCC.2009.5357224","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357224","url":null,"abstract":"This paper describes a robust PWM class D amplifier with high linearity and good immunity to process variations. By using the proposed adaptive triangular wave generator (ATG), 0.0042% THD+N and 99.2dB dynamic range is achieved in this design. The standard deviation of THD+N ratio over 22 samples can be smaller by 4 times compared to the results without the adaptive triangular wave generator. This chip integrates power MOS stages and 2 channel design. The supply voltage is from 3V to 5.5V and the die area is 2.45mm × 2.9mm.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122017817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357171
Shengxi Diao, Yuanjin Zheng, Yuan Gao, X. Yuan, C. Heng
This paper presents a dual-channel timed array transmitter for impulse radio ultra wide band wireless communication system. The transmitter can generate UWB pulses in two separate transmitter paths with tunable path delay difference of 0~250ps to achieve beamforming capability. Through injection locking with 800MHz input reference, the generated UWB pulse centers at 4GHz and covers 3~5GHz band with 10-dB side-lobe rejection. Fabricated in 0.18μm CMOS technology, the transmitter consumes 37mA at 10Mbps under 1.8V supply.
{"title":"3–5GHz IR-UWB timed array transmitter in 0.18μm CMOS","authors":"Shengxi Diao, Yuanjin Zheng, Yuan Gao, X. Yuan, C. Heng","doi":"10.1109/ASSCC.2009.5357171","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357171","url":null,"abstract":"This paper presents a dual-channel timed array transmitter for impulse radio ultra wide band wireless communication system. The transmitter can generate UWB pulses in two separate transmitter paths with tunable path delay difference of 0~250ps to achieve beamforming capability. Through injection locking with 800MHz input reference, the generated UWB pulse centers at 4GHz and covers 3~5GHz band with 10-dB side-lobe rejection. Fabricated in 0.18μm CMOS technology, the transmitter consumes 37mA at 10Mbps under 1.8V supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123773658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：