Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357195
Y. Tsutsumi, M. Nishio, S. Obayashi, H. Shoki, T. Ikehashi, H. Yamazaki, E. Ogawa, Tomohiro Saito, T. Ohguro, T. Morooka
It is difficult to realize the built-in antenna for wideband systems, because a frequency bandwidth of the low profile antenna is narrow. A frequency tunable antenna is a technique for wideband characteristics. In this paper a low profile double resonance frequency tunable antenna using MEMS variable capacitors is presented. It has high efficiency over a wide frequency band. Through both resonant portions from 465 to 665 MHz, the efficiency of more than −4 dB and the VSWR of less than 3 are observed in the measurement using the variable capacitor of 0.4–0.9 pF.
{"title":"Low profile double resonance frequency tunable antenna using RF MEMS variable capacitor for digital terrestrial broadcasting reception","authors":"Y. Tsutsumi, M. Nishio, S. Obayashi, H. Shoki, T. Ikehashi, H. Yamazaki, E. Ogawa, Tomohiro Saito, T. Ohguro, T. Morooka","doi":"10.1109/ASSCC.2009.5357195","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357195","url":null,"abstract":"It is difficult to realize the built-in antenna for wideband systems, because a frequency bandwidth of the low profile antenna is narrow. A frequency tunable antenna is a technique for wideband characteristics. In this paper a low profile double resonance frequency tunable antenna using MEMS variable capacitors is presented. It has high efficiency over a wide frequency band. Through both resonant portions from 465 to 665 MHz, the efficiency of more than −4 dB and the VSWR of less than 3 are observed in the measurement using the variable capacitor of 0.4–0.9 pF.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117238446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357152
Zhang Feng, Yang Yi, Yang Zongren, P. Chiang, Hu Weiwu
This paper describes a 65nm 16-bit parallel transceiver IP macro, whose bandwidth is 4.8GByte/s with 5pf load including the HBM 2000v ESD protection. Equalizers and CDR modules, CRC checkers and 8b/10b encoders are not added in the design for reducing the latency and the whole latency is 7ns without cables. Since the transceiver has many robust features including a PVT independent PLL with calibrations, the low skew differential clock tree, a stable current mode driver with common mode feedback. The transceiver can tolerance 20% power supply variations and work properly at different process corners and the extreme temperatures. The transceiver can be applied for the interface of sub-100nm high performance processors which require low latency and high stability. The transceiver shows a BER less than 10-15 at 3Gb/s/pin.
{"title":"A low latency transceiver macro with robust design technique for processor interface","authors":"Zhang Feng, Yang Yi, Yang Zongren, P. Chiang, Hu Weiwu","doi":"10.1109/ASSCC.2009.5357152","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357152","url":null,"abstract":"This paper describes a 65nm 16-bit parallel transceiver IP macro, whose bandwidth is 4.8GByte/s with 5pf load including the HBM 2000v ESD protection. Equalizers and CDR modules, CRC checkers and 8b/10b encoders are not added in the design for reducing the latency and the whole latency is 7ns without cables. Since the transceiver has many robust features including a PVT independent PLL with calibrations, the low skew differential clock tree, a stable current mode driver with common mode feedback. The transceiver can tolerance 20% power supply variations and work properly at different process corners and the extreme temperatures. The transceiver can be applied for the interface of sub-100nm high performance processors which require low latency and high stability. The transceiver shows a BER less than 10-15 at 3Gb/s/pin.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130587223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357193
Wei Chen, Wenyi Che, Zhongyu Bi, Jing Wang, N. Yan, Xi Tan, Junyu Wang, Hao Min, Jie Tan
This paper proposes a low power, low voltage Truly Random Number Generator (TRNG) for EPC Gen2 RFID tag. According to the special requirements of Gen2 tag, design considerations and tradeoffs among chip area, power consumption and randomicity are presented. The proposed TRNG is composed of an analog random seed generator which uses the oscillator sampling mechanism, and Linear Feedback Shift Registers (LFSR) for post digital processing. Realized in SMIC 0.18 µm standard CMOS process, the TRNG generates 16-bit random series at a speed of 40 kb/s, and their randomicity performance is verified by the FIPS 140−2 standard for security. Power consumption of the TRNG is only 1.04 µW with a minimum supply voltage of 0.8 V, and its total chip area is 0.05 mm2.
{"title":"A 1.04 µW Truly Random Number Generator for Gen2 RFID tag","authors":"Wei Chen, Wenyi Che, Zhongyu Bi, Jing Wang, N. Yan, Xi Tan, Junyu Wang, Hao Min, Jie Tan","doi":"10.1109/ASSCC.2009.5357193","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357193","url":null,"abstract":"This paper proposes a low power, low voltage Truly Random Number Generator (TRNG) for EPC Gen2 RFID tag. According to the special requirements of Gen2 tag, design considerations and tradeoffs among chip area, power consumption and randomicity are presented. The proposed TRNG is composed of an analog random seed generator which uses the oscillator sampling mechanism, and Linear Feedback Shift Registers (LFSR) for post digital processing. Realized in SMIC 0.18 µm standard CMOS process, the TRNG generates 16-bit random series at a speed of 40 kb/s, and their randomicity performance is verified by the FIPS 140−2 standard for security. Power consumption of the TRNG is only 1.04 µW with a minimum supply voltage of 0.8 V, and its total chip area is 0.05 mm2.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127739251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357247
I. Chen, Rong-Jyi Yang, Shen-Iuan Liu
This paper presents an all-digital implemented clock and data recovery circuit. To alleviate the instability contributed by the large latency of digital loop filter, the architecture of two integral paths is proposed in this work. The loop latency from the digital loop filter can be removing by introducing a high speed pre-accumulator cascaded by a low speed accumulator. It increases the phase margin and also improves the loop stability. A smaller proportional gain for the digital loop filter can be chosen without sacrificing the stability. Hence the jitter performance can be improved. The experimental chip occupies a chip area of 0.432mm2 in standard 0.18∧m CMOS technology. It consumes 23.4mW from a 1.8V supply and achieves a peak-to-peak jitter of 0.064 unit interval while operating at the bit rate of 1.25Gb/s.
{"title":"Loop latency reduction technique for all-digital clock and data recovery circuits","authors":"I. Chen, Rong-Jyi Yang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2009.5357247","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357247","url":null,"abstract":"This paper presents an all-digital implemented clock and data recovery circuit. To alleviate the instability contributed by the large latency of digital loop filter, the architecture of two integral paths is proposed in this work. The loop latency from the digital loop filter can be removing by introducing a high speed pre-accumulator cascaded by a low speed accumulator. It increases the phase margin and also improves the loop stability. A smaller proportional gain for the digital loop filter can be chosen without sacrificing the stability. Hence the jitter performance can be improved. The experimental chip occupies a chip area of 0.432mm2 in standard 0.18∧m CMOS technology. It consumes 23.4mW from a 1.8V supply and achieves a peak-to-peak jitter of 0.064 unit interval while operating at the bit rate of 1.25Gb/s.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"140 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129222169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357191
Sehyung Jeon, Y. Nam, Seonghwan Cho
In this paper, a recording and stimulation method that does not require electrodes exposed to the neurons is introduced, Unlike conventional neural stimulation ICs based on micro-electrodes, the proposed method exploits eddy current induced by time-varying magnetic field of a micro-inductor. The recording circuit employs an electrolyte-insulator-metal capacitor which removes the need for the exposed metal electrode, thereby making the post-process step easier. The proposed technique also solves the problem of recording blind-time and charge-imbalance seen in the conventional MEA-based system. The proof-of-concept IC has been fabricated in 0.18um 1-poly, 4-metal standard CMOS process.
{"title":"A neural recording and stimulation technique using passivated electrodes and micro-inductors","authors":"Sehyung Jeon, Y. Nam, Seonghwan Cho","doi":"10.1109/ASSCC.2009.5357191","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357191","url":null,"abstract":"In this paper, a recording and stimulation method that does not require electrodes exposed to the neurons is introduced, Unlike conventional neural stimulation ICs based on micro-electrodes, the proposed method exploits eddy current induced by time-varying magnetic field of a micro-inductor. The recording circuit employs an electrolyte-insulator-metal capacitor which removes the need for the exposed metal electrode, thereby making the post-process step easier. The proposed technique also solves the problem of recording blind-time and charge-imbalance seen in the conventional MEA-based system. The proof-of-concept IC has been fabricated in 0.18um 1-poly, 4-metal standard CMOS process.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117263134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357261
S. Hampel, O. Schmitz, M. Tiebout, I. Rolfes
This article presents the design of a fully integrated inductorless LNA for wireless applications including WLAN, Bluetooth and UWB. The circuit was fabricated in 65nm CMOS technology and operates at a supply voltage of 1.2 V. The two-stage design is comprised of a current reuse shunt feedback input stage followed by a differential pair, incorporating an active inductor load to compensate the gain roll-off. The circuit exhibits a peak gain of 16.5 dB, while the 3-dB bandwidth as well as the input and output matching of better than −10 dB range from 1–10.5 GHz. The noise figure is kept below 5 dB within this frequency range, offering a minimum noise figure of 3.9 dB. The linearity in terms of P1dB, out and oIP3 offers nearly constant behavior with −5 dBm and 3 dBm respectively. The active area takes up only 0.021 mm2.
{"title":"Inductorless 1–10.5 GHz wideband LNA for multistandard applications","authors":"S. Hampel, O. Schmitz, M. Tiebout, I. Rolfes","doi":"10.1109/ASSCC.2009.5357261","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357261","url":null,"abstract":"This article presents the design of a fully integrated inductorless LNA for wireless applications including WLAN, Bluetooth and UWB. The circuit was fabricated in 65nm CMOS technology and operates at a supply voltage of 1.2 V. The two-stage design is comprised of a current reuse shunt feedback input stage followed by a differential pair, incorporating an active inductor load to compensate the gain roll-off. The circuit exhibits a peak gain of 16.5 dB, while the 3-dB bandwidth as well as the input and output matching of better than −10 dB range from 1–10.5 GHz. The noise figure is kept below 5 dB within this frequency range, offering a minimum noise figure of 3.9 dB. The linearity in terms of P1dB, out and oIP3 offers nearly constant behavior with −5 dBm and 3 dBm respectively. The active area takes up only 0.021 mm2.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"516 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116218870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357194
T. Nakura, M. Ikeda, K. Asada
This paper presents a random number generation circuit utilizing ring oscillator's wake-up time uncertainty. A ring oscillator goes into metastability state before starting to oscillate when its control voltage is increased from zero. The metastability causes the uncertainty of the wake-up time of the ring oscillator resulting in large jitter, which can be used for random number generation. We compared simple inverter and schmitt trigger type rings, number of stages of the rings, slow and fast control voltage change for the rings. The measurement results show that the slow control voltage change in a inverter type ring oscillator is effective for random number generation.
{"title":"Ring oscillator based random number generator utilizing wake-up time uncertainty","authors":"T. Nakura, M. Ikeda, K. Asada","doi":"10.1109/ASSCC.2009.5357194","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357194","url":null,"abstract":"This paper presents a random number generation circuit utilizing ring oscillator's wake-up time uncertainty. A ring oscillator goes into metastability state before starting to oscillate when its control voltage is increased from zero. The metastability causes the uncertainty of the wake-up time of the ring oscillator resulting in large jitter, which can be used for random number generation. We compared simple inverter and schmitt trigger type rings, number of stages of the rings, slow and fast control voltage change for the rings. The measurement results show that the slow control voltage change in a inverter type ring oscillator is effective for random number generation.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125843435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357173
Xin-Yu Shih, Cheng-Zhou Zhan, A. Wu
For the applications of next-generation channel-adaptive communication systems, a real-time programmable LDPC decoder architecture is proposed with three design techniques: divided-group comparison (DGC), adaptive wordlength assignment (AWA), and efficient early termination scheme (EETS). By utilizing programmable principle, the hardware architecture can support arbitrary Quasi-Cyclic LDPC parity check matrices, including various locations of 1's, information bits, codeword lengths, and code rates. The prototyping LDPC decoder chip using 0.13um CMOS technology, which supports up to 23 code rates with a maximum block size of 1536 bits, only occupies 4.94 mm2 die area, operates at 125 MHz, and dissipates 58 mW power.
{"title":"A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices","authors":"Xin-Yu Shih, Cheng-Zhou Zhan, A. Wu","doi":"10.1109/ASSCC.2009.5357173","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357173","url":null,"abstract":"For the applications of next-generation channel-adaptive communication systems, a real-time programmable LDPC decoder architecture is proposed with three design techniques: divided-group comparison (DGC), adaptive wordlength assignment (AWA), and efficient early termination scheme (EETS). By utilizing programmable principle, the hardware architecture can support arbitrary Quasi-Cyclic LDPC parity check matrices, including various locations of 1's, information bits, codeword lengths, and code rates. The prototyping LDPC decoder chip using 0.13um CMOS technology, which supports up to 23 code rates with a maximum block size of 1536 bits, only occupies 4.94 mm2 die area, operates at 125 MHz, and dissipates 58 mW power.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124245665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 25-GHz CMOS phased array receiver front-end with full-range beam steering is presented. The entire beam steering range is divided into five subsectors, where in each subsector the receive beam is steered by vector distribution and weighted vector combination of the received signals from array antennas. Such architecture has lower circuit complexity and less power consumption because no complicated full-range variable phase shifters and multiphase voltage-controlled oscillators, challenging in CMOS technology, are required. The implemented 0 13 μm CMOS phased array MMIC consumes lower than 30 mW and takes only a small area of 1.43 mm2. The measured array factors at various incident angles are demonstrated. It has 10–12 dB measured power gain and 9–10.5 dB noise figure in 24.5–26 GHz.
{"title":"A 25 GHz CMOS phased array receiver front-end based on subsector beam steering technique","authors":"Ting-Yueh Chin, Sheng-Fuh Chang, Chia-Chan Chang, Jen-Chieh Wu","doi":"10.1109/ASSCC.2009.5357263","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357263","url":null,"abstract":"A 25-GHz CMOS phased array receiver front-end with full-range beam steering is presented. The entire beam steering range is divided into five subsectors, where in each subsector the receive beam is steered by vector distribution and weighted vector combination of the received signals from array antennas. Such architecture has lower circuit complexity and less power consumption because no complicated full-range variable phase shifters and multiphase voltage-controlled oscillators, challenging in CMOS technology, are required. The implemented 0 13 μm CMOS phased array MMIC consumes lower than 30 mW and takes only a small area of 1.43 mm2. The measured array factors at various incident angles are demonstrated. It has 10–12 dB measured power gain and 9–10.5 dB noise figure in 24.5–26 GHz.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130314300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357165
Sai-Weng Sin, Hegong Wei, U. Chio, Yan Zhu, U. Seng-Pan, R. Martins, F. Maloberti
An on-chip capacitor mismatches measurement technique is proposed. The use of a beta-multiplier-biased ring oscillator improves the measurement sensitivity by over 6 times with respect to the state-of-the art. Experimental results using a 90 nm CMOS and thick-oxide transistors are presented. The method enables the measurement of capacitors with mismatches being as small as σ =0.04% only, and the minimum measurable capacitance can be as small 4.3fF. The results also demonstrated that better matching can be achieved with low-density capacitors.
{"title":"On-chip small capacitor mismatches measurement technique using beta-multiplier-biased ring oscillator","authors":"Sai-Weng Sin, Hegong Wei, U. Chio, Yan Zhu, U. Seng-Pan, R. Martins, F. Maloberti","doi":"10.1109/ASSCC.2009.5357165","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357165","url":null,"abstract":"An on-chip capacitor mismatches measurement technique is proposed. The use of a beta-multiplier-biased ring oscillator improves the measurement sensitivity by over 6 times with respect to the state-of-the art. Experimental results using a 90 nm CMOS and thick-oxide transistors are presented. The method enables the measurement of capacitors with mismatches being as small as σ =0.04% only, and the minimum measurable capacitance can be as small 4.3fF. The results also demonstrated that better matching can be achieved with low-density capacitors.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132430147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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