Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357167
F. Lin, J. Brinkhoff, K. Kang, D. Pham, X. Yuan
Building on an efficient active and passive device modeling strategy, a 60 GHz OOK transceiver system including on-chip antenna in 90nm CMOS is designed. The key features of the circuits are small power consumption and size. With the modulator connected to an innovative artificial magnetic conductor (AMC) on-chip antenna, free space transmission at 2Gb/s is demonstrated. Also, an on-chip psuedo-link demonstrates 1Gb/s transmission, using only 26 pJ/bit for the modulator and 6 pJ/bit for the demodulator. The receiver consists of on-chip antenna, LNA with 20dB gain & 5.7dB noise figure, detector and limiting amplifier. Recovery of a 1.5Gb/s NRZ signal is demonstrated.
{"title":"A low power 60GHz OOK transceiver system in 90nm CMOS with innovative on-chip AMC antenna","authors":"F. Lin, J. Brinkhoff, K. Kang, D. Pham, X. Yuan","doi":"10.1109/ASSCC.2009.5357167","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357167","url":null,"abstract":"Building on an efficient active and passive device modeling strategy, a 60 GHz OOK transceiver system including on-chip antenna in 90nm CMOS is designed. The key features of the circuits are small power consumption and size. With the modulator connected to an innovative artificial magnetic conductor (AMC) on-chip antenna, free space transmission at 2Gb/s is demonstrated. Also, an on-chip psuedo-link demonstrates 1Gb/s transmission, using only 26 pJ/bit for the modulator and 6 pJ/bit for the demodulator. The receiver consists of on-chip antenna, LNA with 20dB gain & 5.7dB noise figure, detector and limiting amplifier. Recovery of a 1.5Gb/s NRZ signal is demonstrated.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131010469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357262
R. Tseng, Hao Li, D. Kwon, A. Poon, Y. Chiu
A four-antenna vector modulator (VM) beamforming receiver in 90-nm CMOS operating between 2.4 and 4.9 GHz is presented. The VM is based on a phase-oversampling technique that allows the synthesis of inherently linear, high-resolution complex gains without complex variable gain amplifiers. It achieves 360° phase shift programmability with 8-bit digital control, a measured < 4.2° phase error at a back-off of 4 dB from the maximum gain setting, and a complex gain constellation with a mean error vector magnitude of < 2%. The monolithic beamformer also demonstrates an interference cancellation of > 24 dB for interferers impinging from different directions.
{"title":"An inherently linear phase-oversampling vector modulator in 90-nm CMOS","authors":"R. Tseng, Hao Li, D. Kwon, A. Poon, Y. Chiu","doi":"10.1109/ASSCC.2009.5357262","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357262","url":null,"abstract":"A four-antenna vector modulator (VM) beamforming receiver in 90-nm CMOS operating between 2.4 and 4.9 GHz is presented. The VM is based on a phase-oversampling technique that allows the synthesis of inherently linear, high-resolution complex gains without complex variable gain amplifiers. It achieves 360° phase shift programmability with 8-bit digital control, a measured < 4.2° phase error at a back-off of 4 dB from the maximum gain setting, and a complex gain constellation with a mean error vector magnitude of < 2%. The monolithic beamformer also demonstrates an interference cancellation of > 24 dB for interferers impinging from different directions.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126472549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357216
Deok-Soo Kim, Heesoo Song, Taeho Kim, Suhwan Kim, D. Jeong
A 1.35GHz all-digital phase-locked loop (ADPLL) with an adaptively controlled loop filter and a 1/3rd-resolution fractional divider is presented. The adaptive loop gain controller (ALGC) effectively reduces the nonlinear characteristics of the bang-bang phase-frequency detector (BBPFD). The fractional divider partially compensates for the input phase error which is caused by the fractional-N frequency synthesis operation. A prototype ADPLL using a BBPFD with a dead zone free retimer, an ALGC, and a fractional divider is fabricated in 0.13μm CMOS. The core occupies 0.19mm2 and consumes 13.7mW from a 1.2V supply. The measured RMS jitter was 4.17ps at a 1.35GHz clock output.
{"title":"A 1.35GHz all-digital fractional-N PLL with adaptive loop gain controller and fractional divider","authors":"Deok-Soo Kim, Heesoo Song, Taeho Kim, Suhwan Kim, D. Jeong","doi":"10.1109/ASSCC.2009.5357216","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357216","url":null,"abstract":"A 1.35GHz all-digital phase-locked loop (ADPLL) with an adaptively controlled loop filter and a 1/3rd-resolution fractional divider is presented. The adaptive loop gain controller (ALGC) effectively reduces the nonlinear characteristics of the bang-bang phase-frequency detector (BBPFD). The fractional divider partially compensates for the input phase error which is caused by the fractional-N frequency synthesis operation. A prototype ADPLL using a BBPFD with a dead zone free retimer, an ALGC, and a fractional divider is fabricated in 0.13μm CMOS. The core occupies 0.19mm2 and consumes 13.7mW from a 1.2V supply. The measured RMS jitter was 4.17ps at a 1.35GHz clock output.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"66 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120933712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357186
Man-Chia Chen, J. Yu, Chen-Yi Lee
This work addresses an all digitally-controlled oscillator (DCO) design with three newly proposed hysteresis delay cells (HDC). According to circuit topologies, the three HDCs are defined as on-off, cascaded, and nested HDCs that provide different propagation delay. These HDCs comprise architecture, a power-of-two delay stage DCO (P2DCO), that every delay stage provides half delay than the previous one in a descending order, resulting in low power and low cost features. A self-calibration method is accompanied to maintain the monotonicity of the P2DCO under PVT variations. The P2DCO is verified in a 90nm CMOS technology. The LSB control word provides a 2.04ps delay resolution. The post-layout simulations show that the dynamic power is 75.9μW and 5.2μW in the 239.2MHz and 3.89MHz, respectively. The area of the P2DCO is 60×20μm2.
{"title":"A sub-100μW area-efficient digitally-controlled oscillator based on hysteresis delay cell topologies","authors":"Man-Chia Chen, J. Yu, Chen-Yi Lee","doi":"10.1109/ASSCC.2009.5357186","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357186","url":null,"abstract":"This work addresses an all digitally-controlled oscillator (DCO) design with three newly proposed hysteresis delay cells (HDC). According to circuit topologies, the three HDCs are defined as on-off, cascaded, and nested HDCs that provide different propagation delay. These HDCs comprise architecture, a power-of-two delay stage DCO (P2DCO), that every delay stage provides half delay than the previous one in a descending order, resulting in low power and low cost features. A self-calibration method is accompanied to maintain the monotonicity of the P2DCO under PVT variations. The P2DCO is verified in a 90nm CMOS technology. The LSB control word provides a 2.04ps delay resolution. The post-layout simulations show that the dynamic power is 75.9μW and 5.2μW in the 239.2MHz and 3.89MHz, respectively. The area of the P2DCO is 60×20μm2.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123776826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357190
Long Yan, Jerald Yoo, Binhee Kim, H. Yoo
A 0.5μVrms, 12μW wirelessly powered patch type fabric sensor is presented for wearable body sensor network to continuously monitor personal bioelectric signals. Thick film electrodes are screen printed on the fabric with various metal components and their impedances of ≈100kΩ are characterized. A 2-stage nested chopped analog readout front end (AFE) is optimized for the fabric sensor with reduced electrode referred noise performance of 0.5μVrms. A 10b folded SAR ADC reduces capacitive DAC (CDAC) size and relaxes the power budget of ADC driver by 94%. The proposed fabric sensor operates with system resolution of 9b and CMRR>106dB. The chip fabricated with 0.18μm CMOS technology, the fabric sensor stacked by screen printed inductor (diameter=3cm and # turns=4) can measure the ECG and EMG signals with wirelessly transmitted power through inductive coupling.
{"title":"A 0.5µVrms 12µW patch type fabric sensor for wearable body sensor network","authors":"Long Yan, Jerald Yoo, Binhee Kim, H. Yoo","doi":"10.1109/ASSCC.2009.5357190","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357190","url":null,"abstract":"A 0.5μVrms, 12μW wirelessly powered patch type fabric sensor is presented for wearable body sensor network to continuously monitor personal bioelectric signals. Thick film electrodes are screen printed on the fabric with various metal components and their impedances of ≈100kΩ are characterized. A 2-stage nested chopped analog readout front end (AFE) is optimized for the fabric sensor with reduced electrode referred noise performance of 0.5μVrms. A 10b folded SAR ADC reduces capacitive DAC (CDAC) size and relaxes the power budget of ADC driver by 94%. The proposed fabric sensor operates with system resolution of 9b and CMRR>106dB. The chip fabricated with 0.18μm CMOS technology, the fabric sensor stacked by screen printed inductor (diameter=3cm and # turns=4) can measure the ECG and EMG signals with wirelessly transmitted power through inductive coupling.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125284192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357183
X. Yu, Yuanfeng Sun, W. Rhee, Sangsoo Ko, Wooseung Choo, Byeong-ha Park, Zhihua Wang
A 3.6GHz fractional-N PLL utilizing high-order digital modulation and weighted 13-tap finite impulse response (FIR) filtering for low spur and enhanced noise reduction is implemented in 65nm CMOS. The prototype PLL exhibits nearly −100dBc/Hz in-band noise contribution and −126.8dBc/Hz phase noise at a 3MHz offset from a 1.8GHz carrier. With 5th-order single-loop ΔΣ modulation, the fractional spur levels of −65.6dBc and −58.5dBc are achieved within the bandwidth and near the bandwidth, respectively.
{"title":"A 65nm CMOS 3.6GHz fractional-N PLL with 5th-order ΔΣ modulation and weighted FIR filtering","authors":"X. Yu, Yuanfeng Sun, W. Rhee, Sangsoo Ko, Wooseung Choo, Byeong-ha Park, Zhihua Wang","doi":"10.1109/ASSCC.2009.5357183","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357183","url":null,"abstract":"A 3.6GHz fractional-N PLL utilizing high-order digital modulation and weighted 13-tap finite impulse response (FIR) filtering for low spur and enhanced noise reduction is implemented in 65nm CMOS. The prototype PLL exhibits nearly −100dBc/Hz in-band noise contribution and −126.8dBc/Hz phase noise at a 3MHz offset from a 1.8GHz carrier. With 5th-order single-loop ΔΣ modulation, the fractional spur levels of −65.6dBc and −58.5dBc are achieved within the bandwidth and near the bandwidth, respectively.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131288007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A single driving module with field color sequential (FCS) LCD technology needs to dynamically switch output voltage between 40 V for 12 series G- and B- color LEDs and 26 V for 12 series R-color LEDs at related time cluster. Thus, an energy-recycling (ER) technology is proposed to accelerate voltage settling and save compressed energy when the driving voltage is pressed from 40 V to 26 V. Only one recycling capacitor and one Schottky diode are added into the power structure of synchronous boost converter for composing the proposed ER technology. A proposed energy-recycling mode (ERM) controller is plugged into a boundary current mode (BCM) controller to control energy delivering and recycling. The proposed ER technology was fabricated by TSMC 0.25 μm 2.5/5 V BCD process. Experimental results demonstrate fast and efficient tracking performance of driving voltage is achieved.
{"title":"An energy-recycling (ER) technique for reducing power consumption of field color sequential (FCS) RGB LEDs backlight module","authors":"Ming-Hsin Huang, Yueh-Chang Tsai, Shih-Wei Wang, Dian-Rung Wu, Ke-Horng Chen, Chien-Yu Chen","doi":"10.1109/ASSCC.2009.5357162","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357162","url":null,"abstract":"A single driving module with field color sequential (FCS) LCD technology needs to dynamically switch output voltage between 40 V for 12 series G- and B- color LEDs and 26 V for 12 series R-color LEDs at related time cluster. Thus, an energy-recycling (ER) technology is proposed to accelerate voltage settling and save compressed energy when the driving voltage is pressed from 40 V to 26 V. Only one recycling capacitor and one Schottky diode are added into the power structure of synchronous boost converter for composing the proposed ER technology. A proposed energy-recycling mode (ERM) controller is plugged into a boundary current mode (BCM) controller to control energy delivering and recycling. The proposed ER technology was fabricated by TSMC 0.25 μm 2.5/5 V BCD process. Experimental results demonstrate fast and efficient tracking performance of driving voltage is achieved.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127669346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357250
Seulki Lee, Jerald Yoo, Kiseok Song, H. Yoo
A 1.3pJ/b inductive coupling transceiver is proposed for Cm-range multimedia data transmission in mobile device applications. Its Transmission Time Control (TTC) scheme and Adaptive Gain Control (AGC) scheme reduce the energy consumption below to 1.3pJ/b. Inductor with self-resonance frequency above 200MHz achieves the data rate over 50Mbps. The receiver sensitivity can be enhanced to increase the communication distance up to 7cm by relative magnitude comparison between two nodes of the receiver inductor. The transceiver consumes only 65μW in total with 1V supply.
{"title":"A 1.3pJ/b inductive coupling transceiver with adaptive gain control for Cm-range 50Mbps data communication","authors":"Seulki Lee, Jerald Yoo, Kiseok Song, H. Yoo","doi":"10.1109/ASSCC.2009.5357250","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357250","url":null,"abstract":"A 1.3pJ/b inductive coupling transceiver is proposed for Cm-range multimedia data transmission in mobile device applications. Its Transmission Time Control (TTC) scheme and Adaptive Gain Control (AGC) scheme reduce the energy consumption below to 1.3pJ/b. Inductor with self-resonance frequency above 200MHz achieves the data rate over 50Mbps. The receiver sensitivity can be enhanced to increase the communication distance up to 7cm by relative magnitude comparison between two nodes of the receiver inductor. The transceiver consumes only 65μW in total with 1V supply.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123402576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357152
Zhang Feng, Yang Yi, Yang Zongren, P. Chiang, Hu Weiwu
This paper describes a 65nm 16-bit parallel transceiver IP macro, whose bandwidth is 4.8GByte/s with 5pf load including the HBM 2000v ESD protection. Equalizers and CDR modules, CRC checkers and 8b/10b encoders are not added in the design for reducing the latency and the whole latency is 7ns without cables. Since the transceiver has many robust features including a PVT independent PLL with calibrations, the low skew differential clock tree, a stable current mode driver with common mode feedback. The transceiver can tolerance 20% power supply variations and work properly at different process corners and the extreme temperatures. The transceiver can be applied for the interface of sub-100nm high performance processors which require low latency and high stability. The transceiver shows a BER less than 10-15 at 3Gb/s/pin.
{"title":"A low latency transceiver macro with robust design technique for processor interface","authors":"Zhang Feng, Yang Yi, Yang Zongren, P. Chiang, Hu Weiwu","doi":"10.1109/ASSCC.2009.5357152","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357152","url":null,"abstract":"This paper describes a 65nm 16-bit parallel transceiver IP macro, whose bandwidth is 4.8GByte/s with 5pf load including the HBM 2000v ESD protection. Equalizers and CDR modules, CRC checkers and 8b/10b encoders are not added in the design for reducing the latency and the whole latency is 7ns without cables. Since the transceiver has many robust features including a PVT independent PLL with calibrations, the low skew differential clock tree, a stable current mode driver with common mode feedback. The transceiver can tolerance 20% power supply variations and work properly at different process corners and the extreme temperatures. The transceiver can be applied for the interface of sub-100nm high performance processors which require low latency and high stability. The transceiver shows a BER less than 10-15 at 3Gb/s/pin.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130587223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-22DOI: 10.1109/ASSCC.2009.5357255
V. Karkare, S. Gibson, D. Markovic
Spike sorting is an important processing step in various neuroscientific and clinical studies. An on-chip spike-sorting DSP must provide data-rate reduction while maintaining a power density much less than 800 μW/mm2. Most existing designs either provide only spike detection for multi-channel processing, or they provide detection and feature extraction only for a single channel. We demonstrate a chip for detection, alignment, and feature extraction simultaneously for 64 channels. Spike-sorting algorithms identified from a complexity-performance analysis are implemented on ASIC using a Matlab/Simulink-based architecture design framework. The chip has a modular architecture, which allows it to be configured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated to reduce power consumption when the chip operates for less than 64 channels. The chip is implemented in a 90-nm CMOS process and has a power dissipation of 130 μW (power density of 30 μW/mm2) when processing all 64 channels. A data-rate reduction of 91.25% (11.71 Mbps to 1.02 Mbps) is achieved.
{"title":"A 130-μW, 64-channel spike-sorting DSP chip","authors":"V. Karkare, S. Gibson, D. Markovic","doi":"10.1109/ASSCC.2009.5357255","DOIUrl":"https://doi.org/10.1109/ASSCC.2009.5357255","url":null,"abstract":"Spike sorting is an important processing step in various neuroscientific and clinical studies. An on-chip spike-sorting DSP must provide data-rate reduction while maintaining a power density much less than 800 μW/mm2. Most existing designs either provide only spike detection for multi-channel processing, or they provide detection and feature extraction only for a single channel. We demonstrate a chip for detection, alignment, and feature extraction simultaneously for 64 channels. Spike-sorting algorithms identified from a complexity-performance analysis are implemented on ASIC using a Matlab/Simulink-based architecture design framework. The chip has a modular architecture, which allows it to be configured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated to reduce power consumption when the chip operates for less than 64 channels. The chip is implemented in a 90-nm CMOS process and has a power dissipation of 130 μW (power density of 30 μW/mm2) when processing all 64 channels. A data-rate reduction of 91.25% (11.71 Mbps to 1.02 Mbps) is achieved.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133612472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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