Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834888
Sung-Yao Wang, Hung-Hsien Wu, Chia-Ling Wei
An integrated boost converter with maximum power point tracking for solar photovoltaic (PV) energy harvesting has been proposed. The maximum power point tracking (MPPT) function is realized with analog circuits, instead of using a microprocessor. In the proposed chip, the output power of the PV modules is controlled by modulating the on-time of the boost converter. The chip was designed and fabricated by using TSMC 0.18 μm 1P6M mixed-signal CMOS process. The total chip area is 1.08×1.25 mm2, which is much smaller than that with a microprocessor. The measured maximum tracking efficiency is 90%.
{"title":"An integrated boost converter with maximum power point tracking for solar photovoltaic energy harvesting","authors":"Sung-Yao Wang, Hung-Hsien Wu, Chia-Ling Wei","doi":"10.1109/VLSI-DAT.2014.6834888","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834888","url":null,"abstract":"An integrated boost converter with maximum power point tracking for solar photovoltaic (PV) energy harvesting has been proposed. The maximum power point tracking (MPPT) function is realized with analog circuits, instead of using a microprocessor. In the proposed chip, the output power of the PV modules is controlled by modulating the on-time of the boost converter. The chip was designed and fabricated by using TSMC 0.18 μm 1P6M mixed-signal CMOS process. The total chip area is 1.08×1.25 mm2, which is much smaller than that with a microprocessor. The measured maximum tracking efficiency is 90%.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"264 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114326864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834919
Kuo-Chiang Hung, Tim Chen
The main purpose of this paper is to present the method to reduce the electromagnetic interference (EMI) noise of universal serial bus (USB) hub product. Traditionally, there are a large number of methods used to reduce the EMI noise. Some methods severely increase the cost of product; some methods only improve power integrity (PI) of USB power distribution network (PDN) to a limited extent. In this paper, the present method can reduce EMI noise effectively by PI improvement using few decoupling capacitors (de-caps). More specifically, de-caps placement and value selection are the key parameters that are used to control the PDN behaviors. The results show that the present method is easy to implement and it reduces the EMI noise effectively.
{"title":"Power integrity optimization on USB power distribution network for EMI reduction","authors":"Kuo-Chiang Hung, Tim Chen","doi":"10.1109/VLSI-DAT.2014.6834919","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834919","url":null,"abstract":"The main purpose of this paper is to present the method to reduce the electromagnetic interference (EMI) noise of universal serial bus (USB) hub product. Traditionally, there are a large number of methods used to reduce the EMI noise. Some methods severely increase the cost of product; some methods only improve power integrity (PI) of USB power distribution network (PDN) to a limited extent. In this paper, the present method can reduce EMI noise effectively by PI improvement using few decoupling capacitors (de-caps). More specifically, de-caps placement and value selection are the key parameters that are used to control the PDN behaviors. The results show that the present method is easy to implement and it reduces the EMI noise effectively.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114956297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834912
Chen-Yi Lee, Kelvin Yi-Tse Lai, S. Hsu
Smart sensors are currently demanded in various kinds of applications to pave a way for better life. To reach this goal, it is necessary to provide energy-efficient solutions with analysis capability. Though state-of-the-art SoC's can meet μW-level processing requirements, front-end sensors remain a bottleneck to be solved. In this paper, a few sensors based on event-driven techniques to improve energy-efficiency and accuracy will be first addressed. Then an ECG-SoC for mobile health-care applications will be described and illustrated.
{"title":"Event-driven read-out circuits for energy-efficient sensor-SoC's","authors":"Chen-Yi Lee, Kelvin Yi-Tse Lai, S. Hsu","doi":"10.1109/VLSI-DAT.2014.6834912","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834912","url":null,"abstract":"Smart sensors are currently demanded in various kinds of applications to pave a way for better life. To reach this goal, it is necessary to provide energy-efficient solutions with analysis capability. Though state-of-the-art SoC's can meet μW-level processing requirements, front-end sensors remain a bottleneck to be solved. In this paper, a few sensors based on event-driven techniques to improve energy-efficiency and accuracy will be first addressed. Then an ECG-SoC for mobile health-care applications will be described and illustrated.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130779519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834876
Yung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, C. Chiu
This paper provides a step-by-step guideline for the assessment of an automotive safety microprocessor with ISO 26262 hardware requirements. ISO 26262 part 5 - Product development at the hardware level - specifies the safety activities during the phase of the automotive hardware development. In this phase, hardware safety design is derived (from the results of ISO 26262 part 3 and 4), implemented, integrated, and tested. To prove the compliance with ISO 26262 hardware development process, quantitative evaluations on the hardware are indispensable. These quantitative evaluations are known as hardware architecture metrics and probabilistic hardware metrics. The assessment results qualify a design with an automotive safety integrity level (ASIL) which ranges from ASIL-A (lowest) to ASIL-D (highest). In this paper, we implemented an exemplary safety microprocessor to demonstrate the ISO 26262 hardware assessment process. The derivation procedures of the ASIL level from the hardware architecture metrics and probabilistic hardware metrics are fully discussed. Based on the evaluation results, we also provide design suggestions for the ISO 26262 safety hardware design.
{"title":"Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements","authors":"Yung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, C. Chiu","doi":"10.1109/VLSI-DAT.2014.6834876","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834876","url":null,"abstract":"This paper provides a step-by-step guideline for the assessment of an automotive safety microprocessor with ISO 26262 hardware requirements. ISO 26262 part 5 - Product development at the hardware level - specifies the safety activities during the phase of the automotive hardware development. In this phase, hardware safety design is derived (from the results of ISO 26262 part 3 and 4), implemented, integrated, and tested. To prove the compliance with ISO 26262 hardware development process, quantitative evaluations on the hardware are indispensable. These quantitative evaluations are known as hardware architecture metrics and probabilistic hardware metrics. The assessment results qualify a design with an automotive safety integrity level (ASIL) which ranges from ASIL-A (lowest) to ASIL-D (highest). In this paper, we implemented an exemplary safety microprocessor to demonstrate the ISO 26262 hardware assessment process. The derivation procedures of the ASIL level from the hardware architecture metrics and probabilistic hardware metrics are fully discussed. Based on the evaluation results, we also provide design suggestions for the ISO 26262 safety hardware design.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130449318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834910
Kun-Chih Chen, Huai-Ting Li, A. Wu
The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues. Because of the die-stacking architecture, the thermal problem becomes more severe than in 2D NoC. To simultaneously consider the thermal safety and system performance, proactive thermal management (PDTM) has been proved as an efficient way to control the system temperature against overheat. Based on the information of predictive temperature, the PDTM can early control the system temperature. To predict the future temperature, adopting the Thermal Resistance and Capacitance (Thermal RC) model is a popular way to derive the thermal prediction scheme. However, the Thermal RC value is sensitive to temperature changes, which affect the accuracy of the future temperature estimation. Therefore, the current proactive thermal-aware NoC system still suffers from large performance impact because of imprecise future temperature estimation. In this paper, we propose an LMS-based adaptive thermal prediction (LMS-ATP) model, which can adaptively adjust the involved Thermal RC values for future temperature estimation. The experimental results show that the proposed LMS-ATP model can improve the precision of future temperature estimation by 72.96%. In addition, the system throughput can be enhanced by around 0.77% to 47.96%.
{"title":"LMS-based adaptive temperature prediction scheme for proactive thermal-aware three-dimensional Network-on-Chip systems","authors":"Kun-Chih Chen, Huai-Ting Li, A. Wu","doi":"10.1109/VLSI-DAT.2014.6834910","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834910","url":null,"abstract":"The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues. Because of the die-stacking architecture, the thermal problem becomes more severe than in 2D NoC. To simultaneously consider the thermal safety and system performance, proactive thermal management (PDTM) has been proved as an efficient way to control the system temperature against overheat. Based on the information of predictive temperature, the PDTM can early control the system temperature. To predict the future temperature, adopting the Thermal Resistance and Capacitance (Thermal RC) model is a popular way to derive the thermal prediction scheme. However, the Thermal RC value is sensitive to temperature changes, which affect the accuracy of the future temperature estimation. Therefore, the current proactive thermal-aware NoC system still suffers from large performance impact because of imprecise future temperature estimation. In this paper, we propose an LMS-based adaptive thermal prediction (LMS-ATP) model, which can adaptively adjust the involved Thermal RC values for future temperature estimation. The experimental results show that the proposed LMS-ATP model can improve the precision of future temperature estimation by 72.96%. In addition, the system throughput can be enhanced by around 0.77% to 47.96%.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133329252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834931
C. Prasad
This work reviews transistors of advanced CMOS process nodes from a reliability perspective and covers some of the important challenges and solutions. Physical mechanisms for various modes are investigated for 65nm to 22nm nodes with focus on disruptive changes such as HK/MG and Tri-gate/FinFET. The importance of modeling non-idealities and variation is also emphasized, and projections are made for scaling to sub-20nm with comparisons to existing research.
{"title":"Advanced CMOS reliability challenges","authors":"C. Prasad","doi":"10.1109/VLSI-DAT.2014.6834931","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834931","url":null,"abstract":"This work reviews transistors of advanced CMOS process nodes from a reliability perspective and covers some of the important challenges and solutions. Physical mechanisms for various modes are investigated for 65nm to 22nm nodes with focus on disruptive changes such as HK/MG and Tri-gate/FinFET. The importance of modeling non-idealities and variation is also emphasized, and projections are made for scaling to sub-20nm with comparisons to existing research.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121692217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834895
Chih-Chan Tu, Tsung-Hsien Lin
This paper presents a low-noise low-power Instrumentation Amplifier (IA) for ECG applications. Chopped capacitively-coupled IA (CCIA) is built to precisely define the gain and avoid flicker noise. The circuit for electrode offset (EOS) cancellation is implemented in feed-forward (FF) manner with an area-efficient SC integrator. The FF architecture uses less capacitor ratio to define the low HPF corner than the feedback architecture. Implemented in a 0.18-μm process, the circuit draws 4.2 μA from a 1.8 V supply, and occupies 0.63mm2. The total integrated noise from 0.5 to 100Hz is 7.37 μVrms.
{"title":"Analog front-end amplifier for ECG applications with feed-forward EOS cancellation","authors":"Chih-Chan Tu, Tsung-Hsien Lin","doi":"10.1109/VLSI-DAT.2014.6834895","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834895","url":null,"abstract":"This paper presents a low-noise low-power Instrumentation Amplifier (IA) for ECG applications. Chopped capacitively-coupled IA (CCIA) is built to precisely define the gain and avoid flicker noise. The circuit for electrode offset (EOS) cancellation is implemented in feed-forward (FF) manner with an area-efficient SC integrator. The FF architecture uses less capacitor ratio to define the low HPF corner than the feedback architecture. Implemented in a 0.18-μm process, the circuit draws 4.2 μA from a 1.8 V supply, and occupies 0.63mm2. The total integrated noise from 0.5 to 100Hz is 7.37 μVrms.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122812665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834871
S. Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean Shih-Ying Liu, Po-Cheng Pan, Hung-Ming Chen
This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the “SPICE accuracy” device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.
{"title":"An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming","authors":"S. Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean Shih-Ying Liu, Po-Cheng Pan, Hung-Ming Chen","doi":"10.1109/VLSI-DAT.2014.6834871","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834871","url":null,"abstract":"This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the “SPICE accuracy” device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126375557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834936
Zebo Peng
More and more embedded systems are used in safety-critical areas such as automotive electronics and medical applications. These safety-critical applications impose stringent requirements on reliability, performance, low-power and testability of the underlying VLSI circuits. With silicon technology scaling, however, VLSI circuits operate very often at high temperature, which has negative impact on reliability, performance, power-efficiency and testability. This paper discusses several thermal impacts on VLSI circuits and their related challenges. It presents also a few emerging techniques that take temperature into account in the design and test processes.
{"title":"Thermal challenges to building reliable embedded systems","authors":"Zebo Peng","doi":"10.1109/VLSI-DAT.2014.6834936","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834936","url":null,"abstract":"More and more embedded systems are used in safety-critical areas such as automotive electronics and medical applications. These safety-critical applications impose stringent requirements on reliability, performance, low-power and testability of the underlying VLSI circuits. With silicon technology scaling, however, VLSI circuits operate very often at high temperature, which has negative impact on reliability, performance, power-efficiency and testability. This paper discusses several thermal impacts on VLSI circuits and their related challenges. It presents also a few emerging techniques that take temperature into account in the design and test processes.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834859
Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li
Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method to consume much more runtime and memory space. In this paper, we propose a skillful method to effectively Diminish Antenna effect in Layer Assignment Stage (DALAS). Unlike previous work that needs to search for separator locations and thus requires exploring much more solution space, DALAS does not need to search for separator locations and can deal with local and global antenna effects while trying to keep total via count and total overflow minimal. Experiment results show that DALAS is the first work to expel all antenna violations with similar via count to that produced by previous works [3][5] for the benchmarks in ISPD'08 Global Routing Contest.
{"title":"Skillfully diminishing antenna effect in layer assignment stage","authors":"Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li","doi":"10.1109/VLSI-DAT.2014.6834859","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834859","url":null,"abstract":"Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method to consume much more runtime and memory space. In this paper, we propose a skillful method to effectively Diminish Antenna effect in Layer Assignment Stage (DALAS). Unlike previous work that needs to search for separator locations and thus requires exploring much more solution space, DALAS does not need to search for separator locations and can deal with local and global antenna effects while trying to keep total via count and total overflow minimal. Experiment results show that DALAS is the first work to expel all antenna violations with similar via count to that produced by previous works [3][5] for the benchmarks in ISPD'08 Global Routing Contest.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125906288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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