Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834888
Sung-Yao Wang, Hung-Hsien Wu, Chia-Ling Wei
An integrated boost converter with maximum power point tracking for solar photovoltaic (PV) energy harvesting has been proposed. The maximum power point tracking (MPPT) function is realized with analog circuits, instead of using a microprocessor. In the proposed chip, the output power of the PV modules is controlled by modulating the on-time of the boost converter. The chip was designed and fabricated by using TSMC 0.18 μm 1P6M mixed-signal CMOS process. The total chip area is 1.08×1.25 mm2, which is much smaller than that with a microprocessor. The measured maximum tracking efficiency is 90%.
{"title":"An integrated boost converter with maximum power point tracking for solar photovoltaic energy harvesting","authors":"Sung-Yao Wang, Hung-Hsien Wu, Chia-Ling Wei","doi":"10.1109/VLSI-DAT.2014.6834888","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834888","url":null,"abstract":"An integrated boost converter with maximum power point tracking for solar photovoltaic (PV) energy harvesting has been proposed. The maximum power point tracking (MPPT) function is realized with analog circuits, instead of using a microprocessor. In the proposed chip, the output power of the PV modules is controlled by modulating the on-time of the boost converter. The chip was designed and fabricated by using TSMC 0.18 μm 1P6M mixed-signal CMOS process. The total chip area is 1.08×1.25 mm2, which is much smaller than that with a microprocessor. The measured maximum tracking efficiency is 90%.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"264 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114326864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834919
Kuo-Chiang Hung, Tim Chen
The main purpose of this paper is to present the method to reduce the electromagnetic interference (EMI) noise of universal serial bus (USB) hub product. Traditionally, there are a large number of methods used to reduce the EMI noise. Some methods severely increase the cost of product; some methods only improve power integrity (PI) of USB power distribution network (PDN) to a limited extent. In this paper, the present method can reduce EMI noise effectively by PI improvement using few decoupling capacitors (de-caps). More specifically, de-caps placement and value selection are the key parameters that are used to control the PDN behaviors. The results show that the present method is easy to implement and it reduces the EMI noise effectively.
{"title":"Power integrity optimization on USB power distribution network for EMI reduction","authors":"Kuo-Chiang Hung, Tim Chen","doi":"10.1109/VLSI-DAT.2014.6834919","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834919","url":null,"abstract":"The main purpose of this paper is to present the method to reduce the electromagnetic interference (EMI) noise of universal serial bus (USB) hub product. Traditionally, there are a large number of methods used to reduce the EMI noise. Some methods severely increase the cost of product; some methods only improve power integrity (PI) of USB power distribution network (PDN) to a limited extent. In this paper, the present method can reduce EMI noise effectively by PI improvement using few decoupling capacitors (de-caps). More specifically, de-caps placement and value selection are the key parameters that are used to control the PDN behaviors. The results show that the present method is easy to implement and it reduces the EMI noise effectively.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114956297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834912
Chen-Yi Lee, Kelvin Yi-Tse Lai, S. Hsu
Smart sensors are currently demanded in various kinds of applications to pave a way for better life. To reach this goal, it is necessary to provide energy-efficient solutions with analysis capability. Though state-of-the-art SoC's can meet μW-level processing requirements, front-end sensors remain a bottleneck to be solved. In this paper, a few sensors based on event-driven techniques to improve energy-efficiency and accuracy will be first addressed. Then an ECG-SoC for mobile health-care applications will be described and illustrated.
{"title":"Event-driven read-out circuits for energy-efficient sensor-SoC's","authors":"Chen-Yi Lee, Kelvin Yi-Tse Lai, S. Hsu","doi":"10.1109/VLSI-DAT.2014.6834912","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834912","url":null,"abstract":"Smart sensors are currently demanded in various kinds of applications to pave a way for better life. To reach this goal, it is necessary to provide energy-efficient solutions with analysis capability. Though state-of-the-art SoC's can meet μW-level processing requirements, front-end sensors remain a bottleneck to be solved. In this paper, a few sensors based on event-driven techniques to improve energy-efficiency and accuracy will be first addressed. Then an ECG-SoC for mobile health-care applications will be described and illustrated.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130779519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834876
Yung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, C. Chiu
This paper provides a step-by-step guideline for the assessment of an automotive safety microprocessor with ISO 26262 hardware requirements. ISO 26262 part 5 - Product development at the hardware level - specifies the safety activities during the phase of the automotive hardware development. In this phase, hardware safety design is derived (from the results of ISO 26262 part 3 and 4), implemented, integrated, and tested. To prove the compliance with ISO 26262 hardware development process, quantitative evaluations on the hardware are indispensable. These quantitative evaluations are known as hardware architecture metrics and probabilistic hardware metrics. The assessment results qualify a design with an automotive safety integrity level (ASIL) which ranges from ASIL-A (lowest) to ASIL-D (highest). In this paper, we implemented an exemplary safety microprocessor to demonstrate the ISO 26262 hardware assessment process. The derivation procedures of the ASIL level from the hardware architecture metrics and probabilistic hardware metrics are fully discussed. Based on the evaluation results, we also provide design suggestions for the ISO 26262 safety hardware design.
{"title":"Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements","authors":"Yung-Chang Chang, Li-Ren Huang, Hsing-Chuang Liu, Chih-Jen Yang, C. Chiu","doi":"10.1109/VLSI-DAT.2014.6834876","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834876","url":null,"abstract":"This paper provides a step-by-step guideline for the assessment of an automotive safety microprocessor with ISO 26262 hardware requirements. ISO 26262 part 5 - Product development at the hardware level - specifies the safety activities during the phase of the automotive hardware development. In this phase, hardware safety design is derived (from the results of ISO 26262 part 3 and 4), implemented, integrated, and tested. To prove the compliance with ISO 26262 hardware development process, quantitative evaluations on the hardware are indispensable. These quantitative evaluations are known as hardware architecture metrics and probabilistic hardware metrics. The assessment results qualify a design with an automotive safety integrity level (ASIL) which ranges from ASIL-A (lowest) to ASIL-D (highest). In this paper, we implemented an exemplary safety microprocessor to demonstrate the ISO 26262 hardware assessment process. The derivation procedures of the ASIL level from the hardware architecture metrics and probabilistic hardware metrics are fully discussed. Based on the evaluation results, we also provide design suggestions for the ISO 26262 safety hardware design.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130449318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834910
Kun-Chih Chen, Huai-Ting Li, A. Wu
The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues. Because of the die-stacking architecture, the thermal problem becomes more severe than in 2D NoC. To simultaneously consider the thermal safety and system performance, proactive thermal management (PDTM) has been proved as an efficient way to control the system temperature against overheat. Based on the information of predictive temperature, the PDTM can early control the system temperature. To predict the future temperature, adopting the Thermal Resistance and Capacitance (Thermal RC) model is a popular way to derive the thermal prediction scheme. However, the Thermal RC value is sensitive to temperature changes, which affect the accuracy of the future temperature estimation. Therefore, the current proactive thermal-aware NoC system still suffers from large performance impact because of imprecise future temperature estimation. In this paper, we propose an LMS-based adaptive thermal prediction (LMS-ATP) model, which can adaptively adjust the involved Thermal RC values for future temperature estimation. The experimental results show that the proposed LMS-ATP model can improve the precision of future temperature estimation by 72.96%. In addition, the system throughput can be enhanced by around 0.77% to 47.96%.
{"title":"LMS-based adaptive temperature prediction scheme for proactive thermal-aware three-dimensional Network-on-Chip systems","authors":"Kun-Chih Chen, Huai-Ting Li, A. Wu","doi":"10.1109/VLSI-DAT.2014.6834910","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834910","url":null,"abstract":"The three-dimensional Network-on-Chip (3D NoC) has been proposed to solve the complex on-chip communication issues. Because of the die-stacking architecture, the thermal problem becomes more severe than in 2D NoC. To simultaneously consider the thermal safety and system performance, proactive thermal management (PDTM) has been proved as an efficient way to control the system temperature against overheat. Based on the information of predictive temperature, the PDTM can early control the system temperature. To predict the future temperature, adopting the Thermal Resistance and Capacitance (Thermal RC) model is a popular way to derive the thermal prediction scheme. However, the Thermal RC value is sensitive to temperature changes, which affect the accuracy of the future temperature estimation. Therefore, the current proactive thermal-aware NoC system still suffers from large performance impact because of imprecise future temperature estimation. In this paper, we propose an LMS-based adaptive thermal prediction (LMS-ATP) model, which can adaptively adjust the involved Thermal RC values for future temperature estimation. The experimental results show that the proposed LMS-ATP model can improve the precision of future temperature estimation by 72.96%. In addition, the system throughput can be enhanced by around 0.77% to 47.96%.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133329252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834902
Ching-Che Chung, Chi-Yu Hou
In this paper, an all-digital delay-locked loop (ADDLL) for 3D-IC die-to-die clock synchronization with through silicon vias (TSVs) is presented. The proposed ADDLL can tolerate delay variations in TSVs and synchronize the clock signals in multiple layers of a given 3D-IC. Firstly, after system is reset, the proposed ADDLL uses two high resolution delay lines which composed of digital controlled varactors (DCVs) to compensate for the delay variations in TSVs. Subsequently, the proposed ADDLL can further compensate for the clock skew of clock signals in multiple layers of a 3D-IC. After ADDLL is locked, the clock skew or phase error is eliminated, and data transfer between dies can be performed synchronously. The proposed design can operate from 300MHz to 1GHz. The proposed ADDLL is implemented in a standard performance 90nm CMOS process, and the area of the ADDLL per die is 0.045mm2. The power consumption of the proposed ADDLL is 3.27mW at 1GHz, and the maximum phase error of clock signals in multiple layers of a given 3D-IC is 21.9ps.
{"title":"All-digital delay-locked loop for 3D-IC die-to-die clock synchronization","authors":"Ching-Che Chung, Chi-Yu Hou","doi":"10.1109/VLSI-DAT.2014.6834902","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834902","url":null,"abstract":"In this paper, an all-digital delay-locked loop (ADDLL) for 3D-IC die-to-die clock synchronization with through silicon vias (TSVs) is presented. The proposed ADDLL can tolerate delay variations in TSVs and synchronize the clock signals in multiple layers of a given 3D-IC. Firstly, after system is reset, the proposed ADDLL uses two high resolution delay lines which composed of digital controlled varactors (DCVs) to compensate for the delay variations in TSVs. Subsequently, the proposed ADDLL can further compensate for the clock skew of clock signals in multiple layers of a 3D-IC. After ADDLL is locked, the clock skew or phase error is eliminated, and data transfer between dies can be performed synchronously. The proposed design can operate from 300MHz to 1GHz. The proposed ADDLL is implemented in a standard performance 90nm CMOS process, and the area of the ADDLL per die is 0.045mm2. The power consumption of the proposed ADDLL is 3.27mW at 1GHz, and the maximum phase error of clock signals in multiple layers of a given 3D-IC is 21.9ps.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132540402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a low-complexity video stitching algorithm and its system prototype are proposed. With the novel design, users can obtain a high-resolution, high quality and seamless 360-degree panoramic video immediately by stitching the images with overlapped regions. Most of the present works are focused on image stitching instead of video stitching. In the proposed design, we develop some novel methods to solve the problems encountered in video stitching. First, we provide a new blending method to remove the color difference in video stitching. Moreover, we avoid the moving objects in the overlapped area by using the dynamic seam adjustment scheme. Finally, we remove the drift problem and obtain a better visual quality while displaying the 360 degree panoramic video scenes. The implementation results show that the entire system achieves 4-channel D1 30fps real-time video stitching on an Intel i7 3930K CPU 2.3GHz machine with 8GB DDR3 memory and Linux Ubuntu 12.10 operation system.
{"title":"A 360-degree panoramic video system design","authors":"Kai-Chen Huang, Po-Yu Chien, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo","doi":"10.1109/VLSI-DAT.2014.6834863","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834863","url":null,"abstract":"In this paper, a low-complexity video stitching algorithm and its system prototype are proposed. With the novel design, users can obtain a high-resolution, high quality and seamless 360-degree panoramic video immediately by stitching the images with overlapped regions. Most of the present works are focused on image stitching instead of video stitching. In the proposed design, we develop some novel methods to solve the problems encountered in video stitching. First, we provide a new blending method to remove the color difference in video stitching. Moreover, we avoid the moving objects in the overlapped area by using the dynamic seam adjustment scheme. Finally, we remove the drift problem and obtain a better visual quality while displaying the 360 degree panoramic video scenes. The implementation results show that the entire system achieves 4-channel D1 30fps real-time video stitching on an Intel i7 3930K CPU 2.3GHz machine with 8GB DDR3 memory and Linux Ubuntu 12.10 operation system.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133579847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834895
Chih-Chan Tu, Tsung-Hsien Lin
This paper presents a low-noise low-power Instrumentation Amplifier (IA) for ECG applications. Chopped capacitively-coupled IA (CCIA) is built to precisely define the gain and avoid flicker noise. The circuit for electrode offset (EOS) cancellation is implemented in feed-forward (FF) manner with an area-efficient SC integrator. The FF architecture uses less capacitor ratio to define the low HPF corner than the feedback architecture. Implemented in a 0.18-μm process, the circuit draws 4.2 μA from a 1.8 V supply, and occupies 0.63mm2. The total integrated noise from 0.5 to 100Hz is 7.37 μVrms.
{"title":"Analog front-end amplifier for ECG applications with feed-forward EOS cancellation","authors":"Chih-Chan Tu, Tsung-Hsien Lin","doi":"10.1109/VLSI-DAT.2014.6834895","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834895","url":null,"abstract":"This paper presents a low-noise low-power Instrumentation Amplifier (IA) for ECG applications. Chopped capacitively-coupled IA (CCIA) is built to precisely define the gain and avoid flicker noise. The circuit for electrode offset (EOS) cancellation is implemented in feed-forward (FF) manner with an area-efficient SC integrator. The FF architecture uses less capacitor ratio to define the low HPF corner than the feedback architecture. Implemented in a 0.18-μm process, the circuit draws 4.2 μA from a 1.8 V supply, and occupies 0.63mm2. The total integrated noise from 0.5 to 100Hz is 7.37 μVrms.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122812665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-TSA.2014.6839634
Seok-Hee Lee
Summary form only given. DRAM and NAND technologies have been successfully developed so far thanks to advanced patterning and device technologies, meeting high density, high performance and low cost requirements. However, imminent scaling limit in DRAM and NAND requires breakthrough technologies to meet market needs. DRAM technology in 1xnm and beyond faces severe challenges, such as difficulties in obtaining sufficient storage capacitance and sensing margin. To alleviate the problems, new materials for cell capacitor should be exploited and systematic aids such as error correction should be considered. Besides these scaling issues, DRAM has been suffering from performance issue, and it requires enhanced peripheral transistor performance with low power and high speed by using new process technologies such as HKMG. A 3D integration with TSV provides a new solution for high density, high speed, low power, and wider bandwidth without traditional device geometric scaling. However, 3D has its own challenges such as high manufacturing cost and reliability that need to be overcome before it could be widely used. 3D NAND flash memory technologies have been studied as a strong contender due to their potential for replacing conventional 2D floating gate cell. Recently, there has been remarkable progresses towards mass production even though their inherent issues of poor data retention and process complexity. Several challenges such as process, material, and cell architecture will be discussed. New non-volatile memories such as ReRAM, PRAM and STT-MRAM have undergone explosive study in the past decade. ReRAM and PRAM are now leading candidates to replace conventional NAND or NOR flash memories and to pioneer the field of Storage Class Memories, while STT-MRAM is regarded as the only a non-volatile memory that can have the performance of DRAM due to its high-speed read/write and excellent cycling endurance. Device characteristics of new non-volatile memories, key technology of device integration and materials will be discussed.
{"title":"Scaling trends and challenges of advanced memory technology","authors":"Seok-Hee Lee","doi":"10.1109/VLSI-TSA.2014.6839634","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839634","url":null,"abstract":"Summary form only given. DRAM and NAND technologies have been successfully developed so far thanks to advanced patterning and device technologies, meeting high density, high performance and low cost requirements. However, imminent scaling limit in DRAM and NAND requires breakthrough technologies to meet market needs. DRAM technology in 1xnm and beyond faces severe challenges, such as difficulties in obtaining sufficient storage capacitance and sensing margin. To alleviate the problems, new materials for cell capacitor should be exploited and systematic aids such as error correction should be considered. Besides these scaling issues, DRAM has been suffering from performance issue, and it requires enhanced peripheral transistor performance with low power and high speed by using new process technologies such as HKMG. A 3D integration with TSV provides a new solution for high density, high speed, low power, and wider bandwidth without traditional device geometric scaling. However, 3D has its own challenges such as high manufacturing cost and reliability that need to be overcome before it could be widely used. 3D NAND flash memory technologies have been studied as a strong contender due to their potential for replacing conventional 2D floating gate cell. Recently, there has been remarkable progresses towards mass production even though their inherent issues of poor data retention and process complexity. Several challenges such as process, material, and cell architecture will be discussed. New non-volatile memories such as ReRAM, PRAM and STT-MRAM have undergone explosive study in the past decade. ReRAM and PRAM are now leading candidates to replace conventional NAND or NOR flash memories and to pioneer the field of Storage Class Memories, while STT-MRAM is regarded as the only a non-volatile memory that can have the performance of DRAM due to its high-speed read/write and excellent cycling endurance. Device characteristics of new non-volatile memories, key technology of device integration and materials will be discussed.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121531983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834931
C. Prasad
This work reviews transistors of advanced CMOS process nodes from a reliability perspective and covers some of the important challenges and solutions. Physical mechanisms for various modes are investigated for 65nm to 22nm nodes with focus on disruptive changes such as HK/MG and Tri-gate/FinFET. The importance of modeling non-idealities and variation is also emphasized, and projections are made for scaling to sub-20nm with comparisons to existing research.
{"title":"Advanced CMOS reliability challenges","authors":"C. Prasad","doi":"10.1109/VLSI-DAT.2014.6834931","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834931","url":null,"abstract":"This work reviews transistors of advanced CMOS process nodes from a reliability perspective and covers some of the important challenges and solutions. Physical mechanisms for various modes are investigated for 65nm to 22nm nodes with focus on disruptive changes such as HK/MG and Tri-gate/FinFET. The importance of modeling non-idealities and variation is also emphasized, and projections are made for scaling to sub-20nm with comparisons to existing research.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121692217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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