Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834934
Islam A. K. M. Mahfuzul, H. Onodera
Aggressive technology scaling and strong demand for lowering supply voltage impose a serious challenge in achieving robust and energy-efficient circuit operation. This paper first overviews circuit techniques for variability resilience including on-chip circuits for performance and variability monitoring. We then focus on on-chip delay cells for transistor performance estimation and homogeneous and inhomogeneous ring oscillators for Die-to-Die (D2D) and Within-Die (WID) variability extraction. We also explain topology-reconfigurable on-chip monitors for in-situ variability characterization which can be used for D2D and WID variability modeling. The monitor can also be used for monitoring temporal variability such as Random Telegraph Noise (RTN). Compensation of performance variability can be done by a localized body biasing with on-chip monitors. A proof-of-concept circuit fabricated in a 65 nm process will be demonstrated such that a test chip fabricated at the slow process corner can achieve a target performance under the typical process condition by the compensation.
{"title":"Characterization and compensation of performance variability using on-chip monitors","authors":"Islam A. K. M. Mahfuzul, H. Onodera","doi":"10.1109/VLSI-DAT.2014.6834934","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834934","url":null,"abstract":"Aggressive technology scaling and strong demand for lowering supply voltage impose a serious challenge in achieving robust and energy-efficient circuit operation. This paper first overviews circuit techniques for variability resilience including on-chip circuits for performance and variability monitoring. We then focus on on-chip delay cells for transistor performance estimation and homogeneous and inhomogeneous ring oscillators for Die-to-Die (D2D) and Within-Die (WID) variability extraction. We also explain topology-reconfigurable on-chip monitors for in-situ variability characterization which can be used for D2D and WID variability modeling. The monitor can also be used for monitoring temporal variability such as Random Telegraph Noise (RTN). Compensation of performance variability can be done by a localized body biasing with on-chip monitors. A proof-of-concept circuit fabricated in a 65 nm process will be demonstrated such that a test chip fabricated at the slow process corner can achieve a target performance under the typical process condition by the compensation.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133831565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834864
Jian Wang, Huawei Li, Xiaowei Li
This paper presents a novel abstraction-guided simulation approach for multiple target states which uses posterior probabilities of the states from the abstract model, instead of abstract distances used by former abstraction-guided approaches, as the guidance of simulation. The posterior probabilities carry more precise information of the abstract model, being able to offer more effective guidance as well as allow the simulation to deal with multiple target states at a time. Experimental results show that the simulation using posterior probabilities as guidance is much more efficient than that using the abstract distances, and the multiple target states simulation framework reduces the simulation cycles effectively.
{"title":"A novel abstraction-guided simulation approach using posterior probabilities for verification","authors":"Jian Wang, Huawei Li, Xiaowei Li","doi":"10.1109/VLSI-DAT.2014.6834864","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834864","url":null,"abstract":"This paper presents a novel abstraction-guided simulation approach for multiple target states which uses posterior probabilities of the states from the abstract model, instead of abstract distances used by former abstraction-guided approaches, as the guidance of simulation. The posterior probabilities carry more precise information of the abstract model, being able to offer more effective guidance as well as allow the simulation to deal with multiple target states at a time. Experimental results show that the simulation using posterior probabilities as guidance is much more efficient than that using the abstract distances, and the multiple target states simulation framework reduces the simulation cycles effectively.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116591216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834885
N. Farnoosh, A. Polimeridis, T. Klemas, L. Daniel
A finite element and combined field integral equation domain decomposition approach is presented for electromagnetic scattering from multiple domains. The main computational bottleneck is the construction of the dense coupling impedance matrix blocks capturing the interactions between different domains. In order to accelerate such coupling computation, A. Hochman et al. in [1] proposed the combination of the randomized singular value decomposition (rSVD) and of the discrete empirical interpolation method (DEIM). The computation of the incident fields due to equivalent currents on each domain is reduced to just a few observation points that can be located optimally and automatically by the DEIM algorithm. Furthermore, the compressed form of the coupling blocks generated by that approach significantly reduces the memory requirement and computational cost associated with the iterative solution of the global system matrix. In this paper, we focus on developing an implementation of such approach for a domain decomposition solver that combines finite element method (FEM) with boundary element method (BEM). Results on a simplified magnetic resonance imaging (MRI) scattering on human body are finally presented to validate our code implementation.
{"title":"Accelerated domain decomposition FEM-BEM solver for magnetic resonance imaging (MRI) via discrete empirical interpolation method","authors":"N. Farnoosh, A. Polimeridis, T. Klemas, L. Daniel","doi":"10.1109/VLSI-DAT.2014.6834885","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834885","url":null,"abstract":"A finite element and combined field integral equation domain decomposition approach is presented for electromagnetic scattering from multiple domains. The main computational bottleneck is the construction of the dense coupling impedance matrix blocks capturing the interactions between different domains. In order to accelerate such coupling computation, A. Hochman et al. in [1] proposed the combination of the randomized singular value decomposition (rSVD) and of the discrete empirical interpolation method (DEIM). The computation of the incident fields due to equivalent currents on each domain is reduced to just a few observation points that can be located optimally and automatically by the DEIM algorithm. Furthermore, the compressed form of the coupling blocks generated by that approach significantly reduces the memory requirement and computational cost associated with the iterative solution of the global system matrix. In this paper, we focus on developing an implementation of such approach for a domain decomposition solver that combines finite element method (FEM) with boundary element method (BEM). Results on a simplified magnetic resonance imaging (MRI) scattering on human body are finally presented to validate our code implementation.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"37 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125733147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834865
Wei-Cheng Lien, Kuen-Jong Lee, K. Chakrabarty, Tong-Yu Hsieh
Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%~67.87% test application time with only slight increase on area overhead.
{"title":"Output selection for test response compaction based on multiple counters","authors":"Wei-Cheng Lien, Kuen-Jong Lee, K. Chakrabarty, Tong-Yu Hsieh","doi":"10.1109/VLSI-DAT.2014.6834865","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834865","url":null,"abstract":"Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%~67.87% test application time with only slight increase on area overhead.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123554486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834892
Chih-Hao Lin, C. Hsieh, Che-Chun Lin, Ren-Jr Chen
This paper presents a dual-mode CMOS image sensor (CIS) for optical wireless communication. The proposed CIS system implements two operation modes as image mode and communication mode. In image mode, raw image data is output with integrate-and-readout operation like conventional imager. In communication mode, the modulated light signal from transmitter is extracted with proposed real-time photocurrent sensing and summation operation. The dual-mode function is realized by a compact pixel structure with four transistors (4T). A prototype chip with 64×64 pixel array and 3.3V operation has been designed and fabricated in 0.18um CMOS technology. The pixel pitch is 10×10 um2 with 54.9% fill factor, and the chip size is 1.4mm×1.4mm. The measurement results demonstrate a transimpedance gain of 109dBΩ, a -3dB bandwidth of 1MHz, and raw image data output, in communication mode and image mode, respectively.
{"title":"A dual-mode CMOS image sensor for optical wireless communication","authors":"Chih-Hao Lin, C. Hsieh, Che-Chun Lin, Ren-Jr Chen","doi":"10.1109/VLSI-DAT.2014.6834892","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834892","url":null,"abstract":"This paper presents a dual-mode CMOS image sensor (CIS) for optical wireless communication. The proposed CIS system implements two operation modes as image mode and communication mode. In image mode, raw image data is output with integrate-and-readout operation like conventional imager. In communication mode, the modulated light signal from transmitter is extracted with proposed real-time photocurrent sensing and summation operation. The dual-mode function is realized by a compact pixel structure with four transistors (4T). A prototype chip with 64×64 pixel array and 3.3V operation has been designed and fabricated in 0.18um CMOS technology. The pixel pitch is 10×10 um2 with 54.9% fill factor, and the chip size is 1.4mm×1.4mm. The measurement results demonstrate a transimpedance gain of 109dBΩ, a -3dB bandwidth of 1MHz, and raw image data output, in communication mode and image mode, respectively.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127122924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834883
Hsin-Yu Ting, Chih-Tsun Huang
This paper presents Elliptic Curve Cryptographic (ECC) engines for very constrained devices in ubiquitous security such as passive RFID tags. The proposed scheduling of atomic operations optimizes the EC scalar multiplication at a higher level of finite field arithmetic with improved resource arrangement. Our architecture of arithmetic unit (AU) and circular-shift-based register file (RF) realizes the scheduling effectively. Using 65nm process technology, the ECC engine can produce one scalar multiplication in 250ms with 10.5K gates. The area overhead is 1.23× to 1.54× smaller than other designs; the power of 4.68μW and energy of 1.17μJ is also the lowest. The comparison shows that our ECC engines outperform others in terms of cycles, area, power and energy.
{"title":"Design of low-cost elliptic curve cryptographic engines for ubiquitous security","authors":"Hsin-Yu Ting, Chih-Tsun Huang","doi":"10.1109/VLSI-DAT.2014.6834883","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834883","url":null,"abstract":"This paper presents Elliptic Curve Cryptographic (ECC) engines for very constrained devices in ubiquitous security such as passive RFID tags. The proposed scheduling of atomic operations optimizes the EC scalar multiplication at a higher level of finite field arithmetic with improved resource arrangement. Our architecture of arithmetic unit (AU) and circular-shift-based register file (RF) realizes the scheduling effectively. Using 65nm process technology, the ECC engine can produce one scalar multiplication in 250ms with 10.5K gates. The area overhead is 1.23× to 1.54× smaller than other designs; the power of 4.68μW and energy of 1.17μJ is also the lowest. The comparison shows that our ECC engines outperform others in terms of cycles, area, power and energy.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127468855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834894
Taisuke Hayashi, N. Miura, K. Yoshikawa, M. Nagata
This paper presents a low-power and compact passive supply-resonance (SR) suppression filter. By using an on-chip waveform monitor, a power-delivery network (PDN) impedance including package, and board PDNs is in-situ analyzed to identify the SR frequency fSR. A notch filter which consists of coupled bonding-wire coils and an on-chip MOS capacitor bank is auto-tuned for the SR suppression. This passive filtering approach reduces the power loss to 1/5~1/10 and the static power to effectively zero as compared to an active SR suppression circuit [1]. The coupled bonding-wire coil enhances its self-inductance and hence shrinks the on-chip capacitor size for the layout-area saving. A 0.18μm CMOS test chip demonstrates SR suppression by >43% with only <;7% of power loss and <;0.034mm layout area penalty.
{"title":"A passive supply-resonance suppression filter utilizing inductance-enhanced coupled bonding-wire coils","authors":"Taisuke Hayashi, N. Miura, K. Yoshikawa, M. Nagata","doi":"10.1109/VLSI-DAT.2014.6834894","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834894","url":null,"abstract":"This paper presents a low-power and compact passive supply-resonance (SR) suppression filter. By using an on-chip waveform monitor, a power-delivery network (PDN) impedance including package, and board PDNs is in-situ analyzed to identify the SR frequency fSR. A notch filter which consists of coupled bonding-wire coils and an on-chip MOS capacitor bank is auto-tuned for the SR suppression. This passive filtering approach reduces the power loss to 1/5~1/10 and the static power to effectively zero as compared to an active SR suppression circuit [1]. The coupled bonding-wire coil enhances its self-inductance and hence shrinks the on-chip capacitor size for the layout-area saving. A 0.18μm CMOS test chip demonstrates SR suppression by >43% with only <;7% of power loss and <;0.034mm layout area penalty.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122585958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834923
Hung-Yi Yang
As design becomes more and more complicated, functional verification is getting challenging than ever. The challenges come in twofold: verification is taking longer to finish and difficult to catch all functional errors. Surveys[1] shown that functional error has been the number one reason for re-spin. How well verification is done becomes a very important issue. Re-spin not only can cost a lot due to advancing of manufacturing process but also delays the time to market which could be even more costly than re-spin itself. In order to tackle these two challenges, industry has come up with a solution called Universal Verification Methodology (UVM)[2] in recent years. But even with UVM which standardized the way for designing testbench, a simulation environment has to be well designed to take advantage of UVM and provide management of running large amount of simulations/regression in an efficient way.
{"title":"Highly automated and efficient simulation environment with UVM","authors":"Hung-Yi Yang","doi":"10.1109/VLSI-DAT.2014.6834923","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834923","url":null,"abstract":"As design becomes more and more complicated, functional verification is getting challenging than ever. The challenges come in twofold: verification is taking longer to finish and difficult to catch all functional errors. Surveys[1] shown that functional error has been the number one reason for re-spin. How well verification is done becomes a very important issue. Re-spin not only can cost a lot due to advancing of manufacturing process but also delays the time to market which could be even more costly than re-spin itself. In order to tackle these two challenges, industry has come up with a solution called Universal Verification Methodology (UVM)[2] in recent years. But even with UVM which standardized the way for designing testbench, a simulation environment has to be well designed to take advantage of UVM and provide management of running large amount of simulations/regression in an efficient way.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124286723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834861
Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang
As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, minimizing the number of TSVs becomes an important design issue. Therefore, in this paper, we propose a parallel layer-aware partitioning algorithm, featuring both divergence stage and convergence stage, for TSV minimization in 3D structures. In the divergence stage, we employ OpenMP for the parallelization of 2-way min-cut partitioning and get the initial solution, and then refine it in the convergence stage. Experimental results show that the proposed two-staged algorithm can reduce the number of TSVs by up to 39% as compared to several existing methods.
{"title":"Two-staged parallel layer-aware partitioning for 3D designs","authors":"Yi-Hang Chen, Yi-Ting Chen, Juinn-Dar Huang","doi":"10.1109/VLSI-DAT.2014.6834861","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834861","url":null,"abstract":"As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, minimizing the number of TSVs becomes an important design issue. Therefore, in this paper, we propose a parallel layer-aware partitioning algorithm, featuring both divergence stage and convergence stage, for TSV minimization in 3D structures. In the divergence stage, we employ OpenMP for the parallelization of 2-way min-cut partitioning and get the initial solution, and then refine it in the convergence stage. Experimental results show that the proposed two-staged algorithm can reduce the number of TSVs by up to 39% as compared to several existing methods.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"20 7-8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123584329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834869
Yung-Chih Chen, Kung-Ming Ji
Logic implication that finds necessary assignments for a given set of value assignments in a Boolean circuit has a wide set of applications in the computer-aided design field, such as logic optimization, design verification, and test pattern generation. Due to the high computational complexity, earlier methods either cannot or do not find all necessary assignments, limiting their qualities in the applications. With the dramatic advance of Boolean satisfiability (SAT) solving techniques, applying the efficient SAT solving techniques to logic implication seems promising. Thus, the paper presents a SAT-based method for complete logic implication. Given a set of value assignments, it first simulates a large number of random patterns and collects a set of candidate necessary assignments based on the simulation results. Then, instead of validating each candidate one by one, it iteratively calls a SAT solver to identify the invalid candidates and remove them. At each SAT solving iteration, at least one invalid candidate can be removed. Finally, only the valid candidates are left and they are exactly all the necessary assignments. Furthermore, we extend the method to compute all mandatory assignments for a stuck-at fault test and apply the extended method to enhance a logic optimization algorithm whose quality largely depends on the completeness of the mandatory assignment computation. The experimental results show that the enhanced method achieves an average of 1.3× improvement in circuit size reduction with acceptable CPU time overhead.
{"title":"SAT-based complete logic implication with application to logic optimization","authors":"Yung-Chih Chen, Kung-Ming Ji","doi":"10.1109/VLSI-DAT.2014.6834869","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834869","url":null,"abstract":"Logic implication that finds necessary assignments for a given set of value assignments in a Boolean circuit has a wide set of applications in the computer-aided design field, such as logic optimization, design verification, and test pattern generation. Due to the high computational complexity, earlier methods either cannot or do not find all necessary assignments, limiting their qualities in the applications. With the dramatic advance of Boolean satisfiability (SAT) solving techniques, applying the efficient SAT solving techniques to logic implication seems promising. Thus, the paper presents a SAT-based method for complete logic implication. Given a set of value assignments, it first simulates a large number of random patterns and collects a set of candidate necessary assignments based on the simulation results. Then, instead of validating each candidate one by one, it iteratively calls a SAT solver to identify the invalid candidates and remove them. At each SAT solving iteration, at least one invalid candidate can be removed. Finally, only the valid candidates are left and they are exactly all the necessary assignments. Furthermore, we extend the method to compute all mandatory assignments for a stuck-at fault test and apply the extended method to enhance a logic optimization algorithm whose quality largely depends on the completeness of the mandatory assignment computation. The experimental results show that the enhanced method achieves an average of 1.3× improvement in circuit size reduction with acceptable CPU time overhead.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"432 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122872615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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