Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834936
Zebo Peng
More and more embedded systems are used in safety-critical areas such as automotive electronics and medical applications. These safety-critical applications impose stringent requirements on reliability, performance, low-power and testability of the underlying VLSI circuits. With silicon technology scaling, however, VLSI circuits operate very often at high temperature, which has negative impact on reliability, performance, power-efficiency and testability. This paper discusses several thermal impacts on VLSI circuits and their related challenges. It presents also a few emerging techniques that take temperature into account in the design and test processes.
{"title":"Thermal challenges to building reliable embedded systems","authors":"Zebo Peng","doi":"10.1109/VLSI-DAT.2014.6834936","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834936","url":null,"abstract":"More and more embedded systems are used in safety-critical areas such as automotive electronics and medical applications. These safety-critical applications impose stringent requirements on reliability, performance, low-power and testability of the underlying VLSI circuits. With silicon technology scaling, however, VLSI circuits operate very often at high temperature, which has negative impact on reliability, performance, power-efficiency and testability. This paper discusses several thermal impacts on VLSI circuits and their related challenges. It presents also a few emerging techniques that take temperature into account in the design and test processes.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125837637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834871
S. Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean Shih-Ying Liu, Po-Cheng Pan, Hung-Ming Chen
This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the “SPICE accuracy” device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.
{"title":"An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming","authors":"S. Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean Shih-Ying Liu, Po-Cheng Pan, Hung-Ming Chen","doi":"10.1109/VLSI-DAT.2014.6834871","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834871","url":null,"abstract":"This paper presents an efficient synthesis framework for Low Dropout Regulator (LDOs) automatic design to facilitate varieties of power management ICs applications. A four-stage synthesizer is proposed to deal with topology selection, transistor sizing, and layout generation automatically. The proposed approach correctly describes device behaviors in moderate and strong inversion regions for current optimization. Without trivial trial and error procedure, the “SPICE accuracy” device size mapping is provided, and the resulting layout is compact and regular while meeting analog design constraints. Using the proposed synthesis tool for LDO automatic design, a prototype chip has been successfully fabricated in 65nm CMOS process. The experimental results validate our methodology in industrial cases with high performance and meet all the target specifications.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126375557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834859
Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li
Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method to consume much more runtime and memory space. In this paper, we propose a skillful method to effectively Diminish Antenna effect in Layer Assignment Stage (DALAS). Unlike previous work that needs to search for separator locations and thus requires exploring much more solution space, DALAS does not need to search for separator locations and can deal with local and global antenna effects while trying to keep total via count and total overflow minimal. Experiment results show that DALAS is the first work to expel all antenna violations with similar via count to that produced by previous works [3][5] for the benchmarks in ISPD'08 Global Routing Contest.
{"title":"Skillfully diminishing antenna effect in layer assignment stage","authors":"Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li","doi":"10.1109/VLSI-DAT.2014.6834859","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834859","url":null,"abstract":"Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based method to consume much more runtime and memory space. In this paper, we propose a skillful method to effectively Diminish Antenna effect in Layer Assignment Stage (DALAS). Unlike previous work that needs to search for separator locations and thus requires exploring much more solution space, DALAS does not need to search for separator locations and can deal with local and global antenna effects while trying to keep total via count and total overflow minimal. Experiment results show that DALAS is the first work to expel all antenna violations with similar via count to that produced by previous works [3][5] for the benchmarks in ISPD'08 Global Routing Contest.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125906288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834881
Jia-An Jheng, W. Chang, Tai-Cheng Lee
A 3X-oversampling hybrid clock and data recovery (CDR) circuit with programmable bandwidth has been fabricated in a 55-nm CMOS technology. The jitter tolerance analysis and the design of the proposed architecture are presented. The proposed hybrid CDR consists of a conventional phase-tracking CDR and a oversampling CDR for jitter tolerance improvement. Based on the input jitter magnitude and jitter tolerance specification requirements, different bandwidths will be selected. The measured results of jitter tolerance are 1.2 UI @ 10 MHz, 5.5 UI @ 1 MHz, and 35 UI @ 100 kHz, respectively. The total area of this design is 0.98 mm2, and the power consumption is 46.2 mW at 5-Gb/s input data rate from a 1.1V supply voltage.
{"title":"A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth","authors":"Jia-An Jheng, W. Chang, Tai-Cheng Lee","doi":"10.1109/VLSI-DAT.2014.6834881","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834881","url":null,"abstract":"A 3X-oversampling hybrid clock and data recovery (CDR) circuit with programmable bandwidth has been fabricated in a 55-nm CMOS technology. The jitter tolerance analysis and the design of the proposed architecture are presented. The proposed hybrid CDR consists of a conventional phase-tracking CDR and a oversampling CDR for jitter tolerance improvement. Based on the input jitter magnitude and jitter tolerance specification requirements, different bandwidths will be selected. The measured results of jitter tolerance are 1.2 UI @ 10 MHz, 5.5 UI @ 1 MHz, and 35 UI @ 100 kHz, respectively. The total area of this design is 0.98 mm2, and the power consumption is 46.2 mW at 5-Gb/s input data rate from a 1.1V supply voltage.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123002633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834887
Jing Lin, J. Shiau, Chien-Hung Tsai
In this paper, a novel state ACP (adaptive current position) is presented, which allows Buck converter to achieve fast load transient response. The PWM (pulse width modulation) and PFM (pulse frequency modulation) modes increase light-load efficiency and maintain good regulation over a wide load range. When the load rapidly changes from light to heavy, ACP can enhance the transient response, to minimize the settling time and suppresses under/overshoot voltage. Unlike other system, the proposed controller can operate without current-sensor. ACP can force the inductor current to catch up with load current quickly. Switch on high-side power MOS a period of time then change to PWM state. By using the information from pseudo current roof, the exact on-time and off-time at different Vin can be calculated. Also, we can speculate the time to execute ACP without current-sensor. Simulation and experimental results demonstrate the superior dynamic response over that of a conventional digital Buck converter.
本文提出了一种新的自适应电流位置状态ACP (adaptive current position)，使Buck变换器能够实现快速的负载瞬态响应。PWM(脉冲宽度调制)和PFM(脉冲频率调制)模式增加了轻负载效率，并在宽负载范围内保持良好的调节。当负载从轻到重快速变化时，ACP可以增强暂态响应，最大限度地减少稳定时间，抑制欠/过调电压。与其他系统不同的是，该控制器可以在没有电流传感器的情况下运行。ACP可以迫使电感电流快速赶上负载电流。开关高侧功率MOS一段时间，然后切换到PWM状态。利用伪电流顶的信息，可以计算出不同电压点的准确通断时间。此外，我们还可以推测在没有电流传感器的情况下执行ACP的时间。仿真和实验结果表明，该方法的动态响应优于传统数字Buck变换器。
{"title":"A fast transient and under/overshoot suppression DC-DC Buck converter with ACP control","authors":"Jing Lin, J. Shiau, Chien-Hung Tsai","doi":"10.1109/VLSI-DAT.2014.6834887","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834887","url":null,"abstract":"In this paper, a novel state ACP (adaptive current position) is presented, which allows Buck converter to achieve fast load transient response. The PWM (pulse width modulation) and PFM (pulse frequency modulation) modes increase light-load efficiency and maintain good regulation over a wide load range. When the load rapidly changes from light to heavy, ACP can enhance the transient response, to minimize the settling time and suppresses under/overshoot voltage. Unlike other system, the proposed controller can operate without current-sensor. ACP can force the inductor current to catch up with load current quickly. Switch on high-side power MOS a period of time then change to PWM state. By using the information from pseudo current roof, the exact on-time and off-time at different Vin can be calculated. Also, we can speculate the time to execute ACP without current-sensor. Simulation and experimental results demonstrate the superior dynamic response over that of a conventional digital Buck converter.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115487504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834868
J. Cho, Kiyoung Choi
This paper presents an efficient implementation of key-value store using Bloom filters on FPGA. Bloom filters are used to reduce the number of unnecessary accesses to the hash tables, thereby improving the performance. Additionally, for better hash table utilization, we use a modified cuckoo hashing algorithm for the implementation. They are implemented in FPGA to further improve the performance. Experimental results show significant performance improvement over existing approaches.
{"title":"An FPGA implementation of high-throughput key-value store using Bloom filter","authors":"J. Cho, Kiyoung Choi","doi":"10.1109/VLSI-DAT.2014.6834868","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834868","url":null,"abstract":"This paper presents an efficient implementation of key-value store using Bloom filters on FPGA. Bloom filters are used to reduce the number of unnecessary accesses to the hash tables, thereby improving the performance. Additionally, for better hash table utilization, we use a modified cuckoo hashing algorithm for the implementation. They are implemented in FPGA to further improve the performance. Experimental results show significant performance improvement over existing approaches.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114430033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834862
Mostafa Said, M. El-Sayed, Farhad Mehdipour, N. Miyakawa
One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due to the high induced thermal stresses during fabrication. The area overhead besides the fabrication process itself inversely affects the overall yield and fabrication cost, so the increase in area will reduce the yield and increase the fabrication cost. In this paper, the effect of KOZ overhead on the overall area, yield, and fabrication cost is investigated. Also various parameters that might change KOZ overhead are examined. We show that the share of area overhead caused by KOZ is considerably higher compared to that of TSVs. Further, the impact of KOZ is considered for obtaining more accurate estimation on W2W overall yield and fabrication cost of a 3D-IC.
{"title":"Keep-Out-Zone analysis for three-dimensional ICs","authors":"Mostafa Said, M. El-Sayed, Farhad Mehdipour, N. Miyakawa","doi":"10.1109/VLSI-DAT.2014.6834862","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834862","url":null,"abstract":"One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due to the high induced thermal stresses during fabrication. The area overhead besides the fabrication process itself inversely affects the overall yield and fabrication cost, so the increase in area will reduce the yield and increase the fabrication cost. In this paper, the effect of KOZ overhead on the overall area, yield, and fabrication cost is investigated. Also various parameters that might change KOZ overhead are examined. We show that the share of area overhead caused by KOZ is considerably higher compared to that of TSVs. Further, the impact of KOZ is considered for obtaining more accurate estimation on W2W overall yield and fabrication cost of a 3D-IC.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127087644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834913
Yen-kuang Chen
Summary form only given. Many people predict Internet of Things will become the next big wave of IT industry. Some people predicts there are a trillions of dollars businesses in the IoT era, as IoT will significant improve our lives. However, are energy efficiency VLSI designs critical to the success of IoT? Or, they are just nice-to-have. In this talk, we plan to discuss the following topics: What are the key computing and communication technology barriers in the IoT era? What kind of VLSI designs in the most important part in IoT?
{"title":"Energy efficiency in the Internet of Things — Critical or nice-to-have?","authors":"Yen-kuang Chen","doi":"10.1109/VLSI-DAT.2014.6834913","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834913","url":null,"abstract":"Summary form only given. Many people predict Internet of Things will become the next big wave of IT industry. Some people predicts there are a trillions of dollars businesses in the IoT era, as IoT will significant improve our lives. However, are energy efficiency VLSI designs critical to the success of IoT? Or, they are just nice-to-have. In this talk, we plan to discuss the following topics: What are the key computing and communication technology barriers in the IoT era? What kind of VLSI designs in the most important part in IoT?","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"10 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123697548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834866
Tong-Yu Hsieh, Kuan-Hsien Li, Yi-Han Peng
With the advance of semiconductor manufacturing technology, low yield issue of a circuit/system has received much attention. Error-tolerance is an innovative concept that can significantly improve yield of integrated circuits (IC's) by identifying defective yet acceptable chips. In this paper we first employ an Inverse Discrete Wavelet Transform (IDWT) circuit to illustrate the potential of yield improvement in a JPEG2000 decoder via error-tolerance. We then carefully analyze error distribution induced by faults in the IDWT design. The analysis results reveal that the identification of acceptable chips will be challenging and needs to be carefully addressed. We also conduct an architectural error-tolerability analysis on the target design and show that one can easily identify the internal locations where errors are unacceptable, and can therefore re-design only the circuitry associated with these locations so as to reduce the significance of errors as well as design costs. In addition we also discuss possible image post-processing methods to further increase the acceptability of the designs.
{"title":"On efficient error-tolerability evaluation and maximization for image processing applications","authors":"Tong-Yu Hsieh, Kuan-Hsien Li, Yi-Han Peng","doi":"10.1109/VLSI-DAT.2014.6834866","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834866","url":null,"abstract":"With the advance of semiconductor manufacturing technology, low yield issue of a circuit/system has received much attention. Error-tolerance is an innovative concept that can significantly improve yield of integrated circuits (IC's) by identifying defective yet acceptable chips. In this paper we first employ an Inverse Discrete Wavelet Transform (IDWT) circuit to illustrate the potential of yield improvement in a JPEG2000 decoder via error-tolerance. We then carefully analyze error distribution induced by faults in the IDWT design. The analysis results reveal that the identification of acceptable chips will be challenging and needs to be carefully addressed. We also conduct an architectural error-tolerability analysis on the target design and show that one can easily identify the internal locations where errors are unacceptable, and can therefore re-design only the circuitry associated with these locations so as to reduce the significance of errors as well as design costs. In addition we also discuss possible image post-processing methods to further increase the acceptability of the designs.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131724130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834875
Yipin Wu, Zhigang Hao, Jin-Seop Han, Joy Tsai
Switching activity in digital circuits produce current peaks which result in voltage fluctuation on the power network, and the accompanying digital power noise may cause WIFI desense. To address this issue, this paper proposes a novel simulation method for application to WLCSP (Wafer Level Chip Scale Packaging), in which RDL (Redistribution Layer) routing is only partially occupied by power mesh. The proposed method correctly models the coupling effect from on-die power mesh's current, via mutual inductance, into the WIFI RX path. The proposed method is applied to a wireless combo chip to confirm that simulation correlates well with silicon measurement. As a result, we are able to demonstrate that on-die power mesh optimization can lead to significant reduction in WIFI de-sense.
{"title":"A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging","authors":"Yipin Wu, Zhigang Hao, Jin-Seop Han, Joy Tsai","doi":"10.1109/VLSI-DAT.2014.6834875","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834875","url":null,"abstract":"Switching activity in digital circuits produce current peaks which result in voltage fluctuation on the power network, and the accompanying digital power noise may cause WIFI desense. To address this issue, this paper proposes a novel simulation method for application to WLCSP (Wafer Level Chip Scale Packaging), in which RDL (Redistribution Layer) routing is only partially occupied by power mesh. The proposed method correctly models the coupling effect from on-die power mesh's current, via mutual inductance, into the WIFI RX path. The proposed method is applied to a wireless combo chip to confirm that simulation correlates well with silicon measurement. As a result, we are able to demonstrate that on-die power mesh optimization can lead to significant reduction in WIFI de-sense.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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