Pub Date : 2014-04-28DOI: 10.1109/VLSI-TSA.2014.6839634
Seok-Hee Lee
Summary form only given. DRAM and NAND technologies have been successfully developed so far thanks to advanced patterning and device technologies, meeting high density, high performance and low cost requirements. However, imminent scaling limit in DRAM and NAND requires breakthrough technologies to meet market needs. DRAM technology in 1xnm and beyond faces severe challenges, such as difficulties in obtaining sufficient storage capacitance and sensing margin. To alleviate the problems, new materials for cell capacitor should be exploited and systematic aids such as error correction should be considered. Besides these scaling issues, DRAM has been suffering from performance issue, and it requires enhanced peripheral transistor performance with low power and high speed by using new process technologies such as HKMG. A 3D integration with TSV provides a new solution for high density, high speed, low power, and wider bandwidth without traditional device geometric scaling. However, 3D has its own challenges such as high manufacturing cost and reliability that need to be overcome before it could be widely used. 3D NAND flash memory technologies have been studied as a strong contender due to their potential for replacing conventional 2D floating gate cell. Recently, there has been remarkable progresses towards mass production even though their inherent issues of poor data retention and process complexity. Several challenges such as process, material, and cell architecture will be discussed. New non-volatile memories such as ReRAM, PRAM and STT-MRAM have undergone explosive study in the past decade. ReRAM and PRAM are now leading candidates to replace conventional NAND or NOR flash memories and to pioneer the field of Storage Class Memories, while STT-MRAM is regarded as the only a non-volatile memory that can have the performance of DRAM due to its high-speed read/write and excellent cycling endurance. Device characteristics of new non-volatile memories, key technology of device integration and materials will be discussed.
{"title":"Scaling trends and challenges of advanced memory technology","authors":"Seok-Hee Lee","doi":"10.1109/VLSI-TSA.2014.6839634","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2014.6839634","url":null,"abstract":"Summary form only given. DRAM and NAND technologies have been successfully developed so far thanks to advanced patterning and device technologies, meeting high density, high performance and low cost requirements. However, imminent scaling limit in DRAM and NAND requires breakthrough technologies to meet market needs. DRAM technology in 1xnm and beyond faces severe challenges, such as difficulties in obtaining sufficient storage capacitance and sensing margin. To alleviate the problems, new materials for cell capacitor should be exploited and systematic aids such as error correction should be considered. Besides these scaling issues, DRAM has been suffering from performance issue, and it requires enhanced peripheral transistor performance with low power and high speed by using new process technologies such as HKMG. A 3D integration with TSV provides a new solution for high density, high speed, low power, and wider bandwidth without traditional device geometric scaling. However, 3D has its own challenges such as high manufacturing cost and reliability that need to be overcome before it could be widely used. 3D NAND flash memory technologies have been studied as a strong contender due to their potential for replacing conventional 2D floating gate cell. Recently, there has been remarkable progresses towards mass production even though their inherent issues of poor data retention and process complexity. Several challenges such as process, material, and cell architecture will be discussed. New non-volatile memories such as ReRAM, PRAM and STT-MRAM have undergone explosive study in the past decade. ReRAM and PRAM are now leading candidates to replace conventional NAND or NOR flash memories and to pioneer the field of Storage Class Memories, while STT-MRAM is regarded as the only a non-volatile memory that can have the performance of DRAM due to its high-speed read/write and excellent cycling endurance. Device characteristics of new non-volatile memories, key technology of device integration and materials will be discussed.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121531983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a low-complexity video stitching algorithm and its system prototype are proposed. With the novel design, users can obtain a high-resolution, high quality and seamless 360-degree panoramic video immediately by stitching the images with overlapped regions. Most of the present works are focused on image stitching instead of video stitching. In the proposed design, we develop some novel methods to solve the problems encountered in video stitching. First, we provide a new blending method to remove the color difference in video stitching. Moreover, we avoid the moving objects in the overlapped area by using the dynamic seam adjustment scheme. Finally, we remove the drift problem and obtain a better visual quality while displaying the 360 degree panoramic video scenes. The implementation results show that the entire system achieves 4-channel D1 30fps real-time video stitching on an Intel i7 3930K CPU 2.3GHz machine with 8GB DDR3 memory and Linux Ubuntu 12.10 operation system.
{"title":"A 360-degree panoramic video system design","authors":"Kai-Chen Huang, Po-Yu Chien, Cheng-An Chien, Hsiu-Cheng Chang, Jiun-In Guo","doi":"10.1109/VLSI-DAT.2014.6834863","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834863","url":null,"abstract":"In this paper, a low-complexity video stitching algorithm and its system prototype are proposed. With the novel design, users can obtain a high-resolution, high quality and seamless 360-degree panoramic video immediately by stitching the images with overlapped regions. Most of the present works are focused on image stitching instead of video stitching. In the proposed design, we develop some novel methods to solve the problems encountered in video stitching. First, we provide a new blending method to remove the color difference in video stitching. Moreover, we avoid the moving objects in the overlapped area by using the dynamic seam adjustment scheme. Finally, we remove the drift problem and obtain a better visual quality while displaying the 360 degree panoramic video scenes. The implementation results show that the entire system achieves 4-channel D1 30fps real-time video stitching on an Intel i7 3930K CPU 2.3GHz machine with 8GB DDR3 memory and Linux Ubuntu 12.10 operation system.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133579847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834902
Ching-Che Chung, Chi-Yu Hou
In this paper, an all-digital delay-locked loop (ADDLL) for 3D-IC die-to-die clock synchronization with through silicon vias (TSVs) is presented. The proposed ADDLL can tolerate delay variations in TSVs and synchronize the clock signals in multiple layers of a given 3D-IC. Firstly, after system is reset, the proposed ADDLL uses two high resolution delay lines which composed of digital controlled varactors (DCVs) to compensate for the delay variations in TSVs. Subsequently, the proposed ADDLL can further compensate for the clock skew of clock signals in multiple layers of a 3D-IC. After ADDLL is locked, the clock skew or phase error is eliminated, and data transfer between dies can be performed synchronously. The proposed design can operate from 300MHz to 1GHz. The proposed ADDLL is implemented in a standard performance 90nm CMOS process, and the area of the ADDLL per die is 0.045mm2. The power consumption of the proposed ADDLL is 3.27mW at 1GHz, and the maximum phase error of clock signals in multiple layers of a given 3D-IC is 21.9ps.
{"title":"All-digital delay-locked loop for 3D-IC die-to-die clock synchronization","authors":"Ching-Che Chung, Chi-Yu Hou","doi":"10.1109/VLSI-DAT.2014.6834902","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834902","url":null,"abstract":"In this paper, an all-digital delay-locked loop (ADDLL) for 3D-IC die-to-die clock synchronization with through silicon vias (TSVs) is presented. The proposed ADDLL can tolerate delay variations in TSVs and synchronize the clock signals in multiple layers of a given 3D-IC. Firstly, after system is reset, the proposed ADDLL uses two high resolution delay lines which composed of digital controlled varactors (DCVs) to compensate for the delay variations in TSVs. Subsequently, the proposed ADDLL can further compensate for the clock skew of clock signals in multiple layers of a 3D-IC. After ADDLL is locked, the clock skew or phase error is eliminated, and data transfer between dies can be performed synchronously. The proposed design can operate from 300MHz to 1GHz. The proposed ADDLL is implemented in a standard performance 90nm CMOS process, and the area of the ADDLL per die is 0.045mm2. The power consumption of the proposed ADDLL is 3.27mW at 1GHz, and the maximum phase error of clock signals in multiple layers of a given 3D-IC is 21.9ps.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132540402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834881
Jia-An Jheng, W. Chang, Tai-Cheng Lee
A 3X-oversampling hybrid clock and data recovery (CDR) circuit with programmable bandwidth has been fabricated in a 55-nm CMOS technology. The jitter tolerance analysis and the design of the proposed architecture are presented. The proposed hybrid CDR consists of a conventional phase-tracking CDR and a oversampling CDR for jitter tolerance improvement. Based on the input jitter magnitude and jitter tolerance specification requirements, different bandwidths will be selected. The measured results of jitter tolerance are 1.2 UI @ 10 MHz, 5.5 UI @ 1 MHz, and 35 UI @ 100 kHz, respectively. The total area of this design is 0.98 mm2, and the power consumption is 46.2 mW at 5-Gb/s input data rate from a 1.1V supply voltage.
{"title":"A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth","authors":"Jia-An Jheng, W. Chang, Tai-Cheng Lee","doi":"10.1109/VLSI-DAT.2014.6834881","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834881","url":null,"abstract":"A 3X-oversampling hybrid clock and data recovery (CDR) circuit with programmable bandwidth has been fabricated in a 55-nm CMOS technology. The jitter tolerance analysis and the design of the proposed architecture are presented. The proposed hybrid CDR consists of a conventional phase-tracking CDR and a oversampling CDR for jitter tolerance improvement. Based on the input jitter magnitude and jitter tolerance specification requirements, different bandwidths will be selected. The measured results of jitter tolerance are 1.2 UI @ 10 MHz, 5.5 UI @ 1 MHz, and 35 UI @ 100 kHz, respectively. The total area of this design is 0.98 mm2, and the power consumption is 46.2 mW at 5-Gb/s input data rate from a 1.1V supply voltage.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123002633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834887
Jing Lin, J. Shiau, Chien-Hung Tsai
In this paper, a novel state ACP (adaptive current position) is presented, which allows Buck converter to achieve fast load transient response. The PWM (pulse width modulation) and PFM (pulse frequency modulation) modes increase light-load efficiency and maintain good regulation over a wide load range. When the load rapidly changes from light to heavy, ACP can enhance the transient response, to minimize the settling time and suppresses under/overshoot voltage. Unlike other system, the proposed controller can operate without current-sensor. ACP can force the inductor current to catch up with load current quickly. Switch on high-side power MOS a period of time then change to PWM state. By using the information from pseudo current roof, the exact on-time and off-time at different Vin can be calculated. Also, we can speculate the time to execute ACP without current-sensor. Simulation and experimental results demonstrate the superior dynamic response over that of a conventional digital Buck converter.
本文提出了一种新的自适应电流位置状态ACP (adaptive current position)，使Buck变换器能够实现快速的负载瞬态响应。PWM(脉冲宽度调制)和PFM(脉冲频率调制)模式增加了轻负载效率，并在宽负载范围内保持良好的调节。当负载从轻到重快速变化时，ACP可以增强暂态响应，最大限度地减少稳定时间，抑制欠/过调电压。与其他系统不同的是，该控制器可以在没有电流传感器的情况下运行。ACP可以迫使电感电流快速赶上负载电流。开关高侧功率MOS一段时间，然后切换到PWM状态。利用伪电流顶的信息，可以计算出不同电压点的准确通断时间。此外，我们还可以推测在没有电流传感器的情况下执行ACP的时间。仿真和实验结果表明，该方法的动态响应优于传统数字Buck变换器。
{"title":"A fast transient and under/overshoot suppression DC-DC Buck converter with ACP control","authors":"Jing Lin, J. Shiau, Chien-Hung Tsai","doi":"10.1109/VLSI-DAT.2014.6834887","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834887","url":null,"abstract":"In this paper, a novel state ACP (adaptive current position) is presented, which allows Buck converter to achieve fast load transient response. The PWM (pulse width modulation) and PFM (pulse frequency modulation) modes increase light-load efficiency and maintain good regulation over a wide load range. When the load rapidly changes from light to heavy, ACP can enhance the transient response, to minimize the settling time and suppresses under/overshoot voltage. Unlike other system, the proposed controller can operate without current-sensor. ACP can force the inductor current to catch up with load current quickly. Switch on high-side power MOS a period of time then change to PWM state. By using the information from pseudo current roof, the exact on-time and off-time at different Vin can be calculated. Also, we can speculate the time to execute ACP without current-sensor. Simulation and experimental results demonstrate the superior dynamic response over that of a conventional digital Buck converter.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115487504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834868
J. Cho, Kiyoung Choi
This paper presents an efficient implementation of key-value store using Bloom filters on FPGA. Bloom filters are used to reduce the number of unnecessary accesses to the hash tables, thereby improving the performance. Additionally, for better hash table utilization, we use a modified cuckoo hashing algorithm for the implementation. They are implemented in FPGA to further improve the performance. Experimental results show significant performance improvement over existing approaches.
{"title":"An FPGA implementation of high-throughput key-value store using Bloom filter","authors":"J. Cho, Kiyoung Choi","doi":"10.1109/VLSI-DAT.2014.6834868","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834868","url":null,"abstract":"This paper presents an efficient implementation of key-value store using Bloom filters on FPGA. Bloom filters are used to reduce the number of unnecessary accesses to the hash tables, thereby improving the performance. Additionally, for better hash table utilization, we use a modified cuckoo hashing algorithm for the implementation. They are implemented in FPGA to further improve the performance. Experimental results show significant performance improvement over existing approaches.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114430033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834862
Mostafa Said, M. El-Sayed, Farhad Mehdipour, N. Miyakawa
One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due to the high induced thermal stresses during fabrication. The area overhead besides the fabrication process itself inversely affects the overall yield and fabrication cost, so the increase in area will reduce the yield and increase the fabrication cost. In this paper, the effect of KOZ overhead on the overall area, yield, and fabrication cost is investigated. Also various parameters that might change KOZ overhead are examined. We show that the share of area overhead caused by KOZ is considerably higher compared to that of TSVs. Further, the impact of KOZ is considered for obtaining more accurate estimation on W2W overall yield and fabrication cost of a 3D-IC.
{"title":"Keep-Out-Zone analysis for three-dimensional ICs","authors":"Mostafa Said, M. El-Sayed, Farhad Mehdipour, N. Miyakawa","doi":"10.1109/VLSI-DAT.2014.6834862","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834862","url":null,"abstract":"One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due to the high induced thermal stresses during fabrication. The area overhead besides the fabrication process itself inversely affects the overall yield and fabrication cost, so the increase in area will reduce the yield and increase the fabrication cost. In this paper, the effect of KOZ overhead on the overall area, yield, and fabrication cost is investigated. Also various parameters that might change KOZ overhead are examined. We show that the share of area overhead caused by KOZ is considerably higher compared to that of TSVs. Further, the impact of KOZ is considered for obtaining more accurate estimation on W2W overall yield and fabrication cost of a 3D-IC.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127087644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834913
Yen-kuang Chen
Summary form only given. Many people predict Internet of Things will become the next big wave of IT industry. Some people predicts there are a trillions of dollars businesses in the IoT era, as IoT will significant improve our lives. However, are energy efficiency VLSI designs critical to the success of IoT? Or, they are just nice-to-have. In this talk, we plan to discuss the following topics: What are the key computing and communication technology barriers in the IoT era? What kind of VLSI designs in the most important part in IoT?
{"title":"Energy efficiency in the Internet of Things — Critical or nice-to-have?","authors":"Yen-kuang Chen","doi":"10.1109/VLSI-DAT.2014.6834913","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834913","url":null,"abstract":"Summary form only given. Many people predict Internet of Things will become the next big wave of IT industry. Some people predicts there are a trillions of dollars businesses in the IoT era, as IoT will significant improve our lives. However, are energy efficiency VLSI designs critical to the success of IoT? Or, they are just nice-to-have. In this talk, we plan to discuss the following topics: What are the key computing and communication technology barriers in the IoT era? What kind of VLSI designs in the most important part in IoT?","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"10 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123697548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834866
Tong-Yu Hsieh, Kuan-Hsien Li, Yi-Han Peng
With the advance of semiconductor manufacturing technology, low yield issue of a circuit/system has received much attention. Error-tolerance is an innovative concept that can significantly improve yield of integrated circuits (IC's) by identifying defective yet acceptable chips. In this paper we first employ an Inverse Discrete Wavelet Transform (IDWT) circuit to illustrate the potential of yield improvement in a JPEG2000 decoder via error-tolerance. We then carefully analyze error distribution induced by faults in the IDWT design. The analysis results reveal that the identification of acceptable chips will be challenging and needs to be carefully addressed. We also conduct an architectural error-tolerability analysis on the target design and show that one can easily identify the internal locations where errors are unacceptable, and can therefore re-design only the circuitry associated with these locations so as to reduce the significance of errors as well as design costs. In addition we also discuss possible image post-processing methods to further increase the acceptability of the designs.
{"title":"On efficient error-tolerability evaluation and maximization for image processing applications","authors":"Tong-Yu Hsieh, Kuan-Hsien Li, Yi-Han Peng","doi":"10.1109/VLSI-DAT.2014.6834866","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834866","url":null,"abstract":"With the advance of semiconductor manufacturing technology, low yield issue of a circuit/system has received much attention. Error-tolerance is an innovative concept that can significantly improve yield of integrated circuits (IC's) by identifying defective yet acceptable chips. In this paper we first employ an Inverse Discrete Wavelet Transform (IDWT) circuit to illustrate the potential of yield improvement in a JPEG2000 decoder via error-tolerance. We then carefully analyze error distribution induced by faults in the IDWT design. The analysis results reveal that the identification of acceptable chips will be challenging and needs to be carefully addressed. We also conduct an architectural error-tolerability analysis on the target design and show that one can easily identify the internal locations where errors are unacceptable, and can therefore re-design only the circuitry associated with these locations so as to reduce the significance of errors as well as design costs. In addition we also discuss possible image post-processing methods to further increase the acceptability of the designs.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131724130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834875
Yipin Wu, Zhigang Hao, Jin-Seop Han, Joy Tsai
Switching activity in digital circuits produce current peaks which result in voltage fluctuation on the power network, and the accompanying digital power noise may cause WIFI desense. To address this issue, this paper proposes a novel simulation method for application to WLCSP (Wafer Level Chip Scale Packaging), in which RDL (Redistribution Layer) routing is only partially occupied by power mesh. The proposed method correctly models the coupling effect from on-die power mesh's current, via mutual inductance, into the WIFI RX path. The proposed method is applied to a wireless combo chip to confirm that simulation correlates well with silicon measurement. As a result, we are able to demonstrate that on-die power mesh optimization can lead to significant reduction in WIFI de-sense.
{"title":"A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging","authors":"Yipin Wu, Zhigang Hao, Jin-Seop Han, Joy Tsai","doi":"10.1109/VLSI-DAT.2014.6834875","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834875","url":null,"abstract":"Switching activity in digital circuits produce current peaks which result in voltage fluctuation on the power network, and the accompanying digital power noise may cause WIFI desense. To address this issue, this paper proposes a novel simulation method for application to WLCSP (Wafer Level Chip Scale Packaging), in which RDL (Redistribution Layer) routing is only partially occupied by power mesh. The proposed method correctly models the coupling effect from on-die power mesh's current, via mutual inductance, into the WIFI RX path. The proposed method is applied to a wireless combo chip to confirm that simulation correlates well with silicon measurement. As a result, we are able to demonstrate that on-die power mesh optimization can lead to significant reduction in WIFI de-sense.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134221271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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