Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834922
Hau-Yung Chen, Ming Juan, Hsin-Hao Chen, Arvin Guan
The device layout structure has proven to have profound effects to its electrical characteristics for advanced technology nodes, which, if not taken into account during the design cycle, will have devastating impact to the circuit functionality. A new design methodology is presented in this paper, which can help circuit designers identify early in the design stage the performance implication due to shift of critical device instance parameters from its layout.
{"title":"Practical electrical parameter aware methodology for analog designers with emphasis on LDE aware for devices","authors":"Hau-Yung Chen, Ming Juan, Hsin-Hao Chen, Arvin Guan","doi":"10.1109/VLSI-DAT.2014.6834922","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834922","url":null,"abstract":"The device layout structure has proven to have profound effects to its electrical characteristics for advanced technology nodes, which, if not taken into account during the design cycle, will have devastating impact to the circuit functionality. A new design methodology is presented in this paper, which can help circuit designers identify early in the design stage the performance implication due to shift of critical device instance parameters from its layout.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120949560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834935
J. Henkel
Summary form only given. Dark Silicon is predicted to dominate the chip footage of upcoming many-core systems within a decade since Dennard Scaling fails mainly due to the voltage-scaling problem that results in higher power densities. It would deem upcoming technologies nodes inefficient since a majority of cores would lie fallow. International research efforts have recently started to investigate and mitigate Dark Silicon effects to ensure an effective use of available chip footage. The talk starts with an overview of state-of-the-art in Dark Silicon research and how it is driven by thermal constraints. Besides background on thermal issues and its impact on reliability, effective solutions are presented that scale especially with respect to many-core systems.
{"title":"Dark Silicon — A thermal perspective","authors":"J. Henkel","doi":"10.1109/VLSI-DAT.2014.6834935","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834935","url":null,"abstract":"Summary form only given. Dark Silicon is predicted to dominate the chip footage of upcoming many-core systems within a decade since Dennard Scaling fails mainly due to the voltage-scaling problem that results in higher power densities. It would deem upcoming technologies nodes inefficient since a majority of cores would lie fallow. International research efforts have recently started to investigate and mitigate Dark Silicon effects to ensure an effective use of available chip footage. The talk starts with an overview of state-of-the-art in Dark Silicon research and how it is driven by thermal constraints. Besides background on thermal issues and its impact on reliability, effective solutions are presented that scale especially with respect to many-core systems.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121361283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834867
Yanbing Wang, Hong Wang, Deyong Meng, Bin Zhou
The Oscillation-Based Test (OBT) method converts the circuits under test (CUTs) into self-oscillating mode by changing CUT's typology or adding feedback path(s). In traditional OBT, the frequencies and amplitudes of sinusoidal oscillation are used as fault features to build up the fault dictionary, which is capable of test but not diagnosis. This paper designs harmonic feedback path to enlarge the harmonics in oscillation, and then builds up fault dictionary to diagnose the analog faults and eliminate the deviation effects by membership functions. The simulation and PCB experiment results prove that the proposed method is both applicable and practical.
{"title":"Oscillation-based diagnosis by using harmonics analysis on analog filters","authors":"Yanbing Wang, Hong Wang, Deyong Meng, Bin Zhou","doi":"10.1109/VLSI-DAT.2014.6834867","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834867","url":null,"abstract":"The Oscillation-Based Test (OBT) method converts the circuits under test (CUTs) into self-oscillating mode by changing CUT's typology or adding feedback path(s). In traditional OBT, the frequencies and amplitudes of sinusoidal oscillation are used as fault features to build up the fault dictionary, which is capable of test but not diagnosis. This paper designs harmonic feedback path to enlarge the harmonics in oscillation, and then builds up fault dictionary to diagnose the analog faults and eliminate the deviation effects by membership functions. The simulation and PCB experiment results prove that the proposed method is both applicable and practical.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121415852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834877
Chang Hao, Huaguo Liang, Li Yang, Yiming Ouyang
One notable difference between 3D test flow and 2D test flow mainly lies in the mid-bond test, in which the stacking yield can be further enhanced through optimized bonding arrangement. In contrast to the existing sequential stacking, this paper proposes a novel rearranged stacking scheme which estimates the probability and cost of failed bonding in each stacking step and optimizes the mid-bond order to screen out the failed component as early as possible. The effect of the rearranged stacking has been extensively analyzed using the yield model and cost model of 3D-SICs considering different process parameters such as die yield, stacking size, failure rate and redundancy degree of TSVs. Experimental results demonstrate that the proposed rearranged stacking method is only a half of the sequential stacking in terms of failed area ratio (FAR).
{"title":"Optimized stacking order for 3D-stacked ICs considering the probability and cost of failed bonding","authors":"Chang Hao, Huaguo Liang, Li Yang, Yiming Ouyang","doi":"10.1109/VLSI-DAT.2014.6834877","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834877","url":null,"abstract":"One notable difference between 3D test flow and 2D test flow mainly lies in the mid-bond test, in which the stacking yield can be further enhanced through optimized bonding arrangement. In contrast to the existing sequential stacking, this paper proposes a novel rearranged stacking scheme which estimates the probability and cost of failed bonding in each stacking step and optimizes the mid-bond order to screen out the failed component as early as possible. The effect of the rearranged stacking has been extensively analyzed using the yield model and cost model of 3D-SICs considering different process parameters such as die yield, stacking size, failure rate and redundancy degree of TSVs. Experimental results demonstrate that the proposed rearranged stacking method is only a half of the sequential stacking in terms of failed area ratio (FAR).","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116404323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an efficient stereo matching algorithm for hardware implementation. A low-complexity local window size decision rule is proposed in our processing scheme. The proper window size is adopted according to the local content characteristic. The matching computation cost is almost as low as the conventional fixed window size method. An efficient hardware architecture comprises unified window size processing elements is also developed. Experimental results reveal that the proposed design can achieve better quality than the related fixed window size method with the properties of low computation cost and hardware realizable flow.
{"title":"Low complexity stereo matching algorithm using adaptive sized square window","authors":"Der-Wei Yang, Li-Chia Chu, Chun-Wei Chen, Jia-Ming Gan, Jonas Wang, Ming-Der Shieh","doi":"10.1109/VLSI-DAT.2014.6834897","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834897","url":null,"abstract":"This paper presents an efficient stereo matching algorithm for hardware implementation. A low-complexity local window size decision rule is proposed in our processing scheme. The proper window size is adopted according to the local content characteristic. The matching computation cost is almost as low as the conventional fixed window size method. An efficient hardware architecture comprises unified window size processing elements is also developed. Experimental results reveal that the proposed design can achieve better quality than the related fixed window size method with the properties of low computation cost and hardware realizable flow.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126402345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834870
Yen-Lung Chen, Guan Chu, Ying-Chi Lien, Ching-Mao Lee, C. Liu
Due to its low power, small ripple and low noise properties, low-dropout regulators (LDO) are often used in on-chip applications. However, there are few design automation works focusing on this important circuit. In this paper, an automatic optimization process is proposed to generate the optimal sizing of low dropout regulators. The devices in the LDO circuit and its error amplifier are both considered in the optimization process for reducing the overall circuit cost. The process variation effects are also considered in this work to guarantee the circuit performance after manufactured. As demonstrated in the experiments, the proposed approach successfully solves the unreachable specification in previous work and significantly improves the design yield of the generated circuits.
{"title":"Simultaneous optimization for low dropout regulator and its error amplifier with process variation","authors":"Yen-Lung Chen, Guan Chu, Ying-Chi Lien, Ching-Mao Lee, C. Liu","doi":"10.1109/VLSI-DAT.2014.6834870","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834870","url":null,"abstract":"Due to its low power, small ripple and low noise properties, low-dropout regulators (LDO) are often used in on-chip applications. However, there are few design automation works focusing on this important circuit. In this paper, an automatic optimization process is proposed to generate the optimal sizing of low dropout regulators. The devices in the LDO circuit and its error amplifier are both considered in the optimization process for reducing the overall circuit cost. The process variation effects are also considered in this work to guarantee the circuit performance after manufactured. As demonstrated in the experiments, the proposed approach successfully solves the unreachable specification in previous work and significantly improves the design yield of the generated circuits.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133221686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834882
Hung-Wen Lin, Jin-Yi Lin, Min-Tai Chuang
This paper proposes a low-area digitalized band-pass filter (BPF) for the DSRC Receiver. The resonance of active inductor and MOS varactor are utilized to generate band-pass filtering characteristics. To apply for different passband, both the inductance of the inductor and the capacitance of the varctor are designed to be adjusted via digital controls. Band selectivity is raised by cascading stages of BPF cell. In 0.18um CMOS technology, a 7bits 6-stage BPF template occupies an active area of 0.16mm2 and consumes a power of 14.8mW under 1.8V of supplies. The center frequency is ranged form 27MHz to 41MHz with an average frequency resolution of 0.11MHz and the adjacent channel suppression is -16dB@ 40±2.5MHz. The input third-order intercept point is 6dbm.
{"title":"A low-area digitalized channel selection filter for DSRC system","authors":"Hung-Wen Lin, Jin-Yi Lin, Min-Tai Chuang","doi":"10.1109/VLSI-DAT.2014.6834882","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834882","url":null,"abstract":"This paper proposes a low-area digitalized band-pass filter (BPF) for the DSRC Receiver. The resonance of active inductor and MOS varactor are utilized to generate band-pass filtering characteristics. To apply for different passband, both the inductance of the inductor and the capacitance of the varctor are designed to be adjusted via digital controls. Band selectivity is raised by cascading stages of BPF cell. In 0.18um CMOS technology, a 7bits 6-stage BPF template occupies an active area of 0.16mm2 and consumes a power of 14.8mW under 1.8V of supplies. The center frequency is ranged form 27MHz to 41MHz with an average frequency resolution of 0.11MHz and the adjacent channel suppression is -16dB@ 40±2.5MHz. The input third-order intercept point is 6dbm.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114942139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834879
Mincent Lee, S. Adham, Min-Jer Wang, C. Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen
Three-dimension ICs (3D-ICs) are the current trend due to their improvement in heterogeneous integration, performance, power consumption, silicon area, and form factors. However, the consequent new challenges are interconnects between dies, i.e., Through-Silicon-Vias (TSVs) and micro-bumps (μ-bumps). Therefore, many interconnect test, diagnosis, and repair schemes were proposed, such as double TSVs & double μ-bumps schemes. In this paper a novel DFT technique is presented based on the double resource schemes. Challenges to two-die, multi-tier, and numerous interconnects are handled by proposed testable, diag-nosable, repairable, and scalable element, structure, and flow.
{"title":"A novel DFT architecture for 3DIC test, diagnosis and repair","authors":"Mincent Lee, S. Adham, Min-Jer Wang, C. Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen","doi":"10.1109/VLSI-DAT.2014.6834879","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834879","url":null,"abstract":"Three-dimension ICs (3D-ICs) are the current trend due to their improvement in heterogeneous integration, performance, power consumption, silicon area, and form factors. However, the consequent new challenges are interconnects between dies, i.e., Through-Silicon-Vias (TSVs) and micro-bumps (μ-bumps). Therefore, many interconnect test, diagnosis, and repair schemes were proposed, such as double TSVs & double μ-bumps schemes. In this paper a novel DFT technique is presented based on the double resource schemes. Challenges to two-die, multi-tier, and numerous interconnects are handled by proposed testable, diag-nosable, repairable, and scalable element, structure, and flow.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116005154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834890
Wei Zhang, Yizhi Han, Fei Chen, Bo Zhou, Xican Chen, W. Rhee, Zhihua Wang
A 3.5-4GHz FMCW radar transceiver employing a phase-domain oversampled ranging method is implemented in 0.18μm CMOS for short-range wireless sensor network (WSN) applications. To overcome the tradeoff between bandwidth and ranging resolution in the conventional FMCW radar, a digital phase rotator and a 1-bit ΔΣ TDC are utilized to realize the oversampled phase-domain ranging, achieving both wide capture range and fine resolution. The proposed ranging method is verified in the prototype FMCW transceiver hardware and the feasibility of sub-cm ranging capability is also demonstrated based on on-board modulation measurement.
{"title":"A 3.5–4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC","authors":"Wei Zhang, Yizhi Han, Fei Chen, Bo Zhou, Xican Chen, W. Rhee, Zhihua Wang","doi":"10.1109/VLSI-DAT.2014.6834890","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834890","url":null,"abstract":"A 3.5-4GHz FMCW radar transceiver employing a phase-domain oversampled ranging method is implemented in 0.18μm CMOS for short-range wireless sensor network (WSN) applications. To overcome the tradeoff between bandwidth and ranging resolution in the conventional FMCW radar, a digital phase rotator and a 1-bit ΔΣ TDC are utilized to realize the oversampled phase-domain ranging, achieving both wide capture range and fine resolution. The proposed ranging method is verified in the prototype FMCW transceiver hardware and the feasibility of sub-cm ranging capability is also demonstrated based on on-board modulation measurement.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123621361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-04-28DOI: 10.1109/VLSI-DAT.2014.6834917
E. Spears
With the emergence of bands and combination of bands along with Carrier Aggregation (CA), the mobile handset RF front-end design has become much more complex and is revolutionizing the Front End Industry. While the industry has gone through a dis-integration strategy to reduce the front-end component cost, the industry has seen a change where the integration of the front-end components has shown both performance and size improvements. This presentation/talk will demonstrate the design aspects and the performance benefits of a complete multi-mode multi-band integrated front end solution.
{"title":"Next generation front end solutions for mobile application","authors":"E. Spears","doi":"10.1109/VLSI-DAT.2014.6834917","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2014.6834917","url":null,"abstract":"With the emergence of bands and combination of bands along with Carrier Aggregation (CA), the mobile handset RF front-end design has become much more complex and is revolutionizing the Front End Industry. While the industry has gone through a dis-integration strategy to reduce the front-end component cost, the industry has seen a change where the integration of the front-end components has shown both performance and size improvements. This presentation/talk will demonstrate the design aspects and the performance benefits of a complete multi-mode multi-band integrated front end solution.","PeriodicalId":267124,"journal":{"name":"Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121465996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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