Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920787
Michelle Lim, S. Ali, S. Jahariah, M. Islam
This work involves the modeling of three arbitrary input sources representing Hybrid Energy Harvesters (HEH) using a DC-DC Boost converter. These sources are combined in parallel and targeted at scavenging passive human power, therefore the three suitable ambient sources are motion, thermal and indoor light. Multiple sources mitigate limitations caused by single source harvesters but suffer impedance mismatches which greatly limit the total combined power that could have been harvested. A Boost Converter with suitable parameters has been designed and integrated to the HEH and PSPICE software has been used for both the modeling of arbitrary sources as well as the integration with the Boost Converter. An input source as low as 18 mV to 907 mV was able to be boosted into a 310 mV-27.9 V output when suitable parametric values were selected for the Ultra Low Power (ULP) HEH. A duty ratio of 0.5, with 10 kΩ load, 22 μH inductor as well as a switching frequency of 25 kHz was selected to be slightly above the audio range as well as being high enough to reduce passive component sizes. While VO/ VS of the boost converter is linear, PO/PIN is a function of third order polynomial. Therefore, at the HEH's lowest combined configuration of 1 K temperature difference, 0.25 g of vibration and 100 lux of indoor lighting, a combined 14 μW can be harvested. At its maximum of 10 K heat difference, 1 g vibration and 1000 lux of indoor lighting a combined 187 μW can be harvested. At its minimum, this enables possibility of battery-less applications in powering a quartz watch at 5 μW while at its maximum capacity powering a pace maker of ~50 μW as well as micro devices of ~100 μW solely from passive human activity. Once a 33 mF input capacitor is placed between the sources and converter, an output power of between 9.61 μW-78 mW can be obtained.
{"title":"Modelling of hybrid energy harvester with DC-DC boost converter using arbitary input sources for ultra-low-power micro-devices","authors":"Michelle Lim, S. Ali, S. Jahariah, M. Islam","doi":"10.1109/SMELEC.2014.6920787","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920787","url":null,"abstract":"This work involves the modeling of three arbitrary input sources representing Hybrid Energy Harvesters (HEH) using a DC-DC Boost converter. These sources are combined in parallel and targeted at scavenging passive human power, therefore the three suitable ambient sources are motion, thermal and indoor light. Multiple sources mitigate limitations caused by single source harvesters but suffer impedance mismatches which greatly limit the total combined power that could have been harvested. A Boost Converter with suitable parameters has been designed and integrated to the HEH and PSPICE software has been used for both the modeling of arbitrary sources as well as the integration with the Boost Converter. An input source as low as 18 mV to 907 mV was able to be boosted into a 310 mV-27.9 V output when suitable parametric values were selected for the Ultra Low Power (ULP) HEH. A duty ratio of 0.5, with 10 kΩ load, 22 μH inductor as well as a switching frequency of 25 kHz was selected to be slightly above the audio range as well as being high enough to reduce passive component sizes. While VO/ VS of the boost converter is linear, PO/PIN is a function of third order polynomial. Therefore, at the HEH's lowest combined configuration of 1 K temperature difference, 0.25 g of vibration and 100 lux of indoor lighting, a combined 14 μW can be harvested. At its maximum of 10 K heat difference, 1 g vibration and 1000 lux of indoor lighting a combined 187 μW can be harvested. At its minimum, this enables possibility of battery-less applications in powering a quartz watch at 5 μW while at its maximum capacity powering a pace maker of ~50 μW as well as micro devices of ~100 μW solely from passive human activity. Once a 33 mF input capacitor is placed between the sources and converter, an output power of between 9.61 μW-78 mW can be obtained.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129452060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920891
M. Zakaria, S. R. Kasjoo, A. F. Mahyidin, A. W. Al-Mufti, R. Ayub, U. Hashim
Flash memory is a device that used as a tool to store data electrically without external power supply. The charge-trap such as SONOS structure is the most widely used in flash memory technology fabrication due to the advantages of this device in term of scaling and performance characteristic. Conventional Flash memory with thickness 5nm single oxide shows good performance, but suffer leakage current and data retention. To overcome this problem, a SONOS flash memory was fabricated by using techniques that known as Engineered Tunnel Barrier to replace the conventional single oxide used in conventional flash memory. In this project, the total equivalent thickness oxide for all experiments is set at the 8nm to compare the performances. Thus, it will result in a faster write and erase speed. The analysis results will determine the most preferred structure that improved the programming characteristic.
{"title":"Fabrication of SONOS flash memory device by using engineered tunnel barrier technique","authors":"M. Zakaria, S. R. Kasjoo, A. F. Mahyidin, A. W. Al-Mufti, R. Ayub, U. Hashim","doi":"10.1109/SMELEC.2014.6920891","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920891","url":null,"abstract":"Flash memory is a device that used as a tool to store data electrically without external power supply. The charge-trap such as SONOS structure is the most widely used in flash memory technology fabrication due to the advantages of this device in term of scaling and performance characteristic. Conventional Flash memory with thickness 5nm single oxide shows good performance, but suffer leakage current and data retention. To overcome this problem, a SONOS flash memory was fabricated by using techniques that known as Engineered Tunnel Barrier to replace the conventional single oxide used in conventional flash memory. In this project, the total equivalent thickness oxide for all experiments is set at the 8nm to compare the performances. Thus, it will result in a faster write and erase speed. The analysis results will determine the most preferred structure that improved the programming characteristic.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122442741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920915
A. Shafura, I. Saurdi, N. Azhar, M. H. Mamat, M. Uzer, M. Rusop, A. Shuhaimi
Nanostructured Aluminium (Al) doped zinc oxide (ZnO) was prepared using sol-gel spin-coating method. These films were tested under different exposure of oxygen flow rates at room temperature with bias voltage applied at 5 V. The structural properties were characterized using Atomic Force Microscopy (AFM) and Field Emission Scanning Electron Microscopy (FESEM). The fesem image revealed the surface morphology of nanostructured ZnO. The diameters size of nanostructured Al-doped ZnO thin film was observed in range of 16-46 nm. These thin films were tested for oxygen-sensing characteristic by varying the gas flow rates at room temperature. The nanostructured Al-doped ZnO-based gas sensor exhibited good sensitivity at low flow rates of oxygen exposure.
{"title":"Nanostructured Al-doped ZnO-based gas sensor prepared using sol-gel spin-coating method","authors":"A. Shafura, I. Saurdi, N. Azhar, M. H. Mamat, M. Uzer, M. Rusop, A. Shuhaimi","doi":"10.1109/SMELEC.2014.6920915","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920915","url":null,"abstract":"Nanostructured Aluminium (Al) doped zinc oxide (ZnO) was prepared using sol-gel spin-coating method. These films were tested under different exposure of oxygen flow rates at room temperature with bias voltage applied at 5 V. The structural properties were characterized using Atomic Force Microscopy (AFM) and Field Emission Scanning Electron Microscopy (FESEM). The fesem image revealed the surface morphology of nanostructured ZnO. The diameters size of nanostructured Al-doped ZnO thin film was observed in range of 16-46 nm. These thin films were tested for oxygen-sensing characteristic by varying the gas flow rates at room temperature. The nanostructured Al-doped ZnO-based gas sensor exhibited good sensitivity at low flow rates of oxygen exposure.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117067741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920839
A. H. Afifah Maheran, Z. A. Noor Faizah, P. Menon, I. Ahmad, P. Apte, T. Kalaivani, F. Salehuddin
The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO2/TiSi2 PMOS device is presented; replacing the conventional SiO2 dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (VTH) and leakage current (IOFF). The simulation result shows that the optimal value of VTH and IOFF which are 0.1030075V and 3.4264075×10-12A/um respectively are well within ITRS prediction.
{"title":"Statistical process modelling for 32nm high-K/metal gate PMOS device","authors":"A. H. Afifah Maheran, Z. A. Noor Faizah, P. Menon, I. Ahmad, P. Apte, T. Kalaivani, F. Salehuddin","doi":"10.1109/SMELEC.2014.6920839","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920839","url":null,"abstract":"The evolution of MOSFET technology has been governed solely by device scaling, delivered an ever-increasing transistor density through Moore's Law. In this paper, the design, fabrication and characterization of 32nm HfO<sub>2</sub>/TiSi<sub>2</sub> PMOS device is presented; replacing the conventional SiO<sub>2</sub> dielectric and Poly-Silicon. The fabrication and simulation of PMOS transistor is performed via Virtual Wafer Fabrication (VWF) Silvaco TCAD Tools namely ATHENA and ATLAS. Taguchi L9 Orthogonal method is then applied to this experiment for optimization of threshold voltage (V<sub>TH</sub>) and leakage current (I<sub>OFF</sub>). The simulation result shows that the optimal value of V<sub>TH</sub> and I<sub>OFF</sub> which are 0.1030075V and 3.4264075×10<sup>-12</sup>A/um respectively are well within ITRS prediction.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121018044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920812
V. Retnasamy, Z. Sauli, R. Vairavan, H. Mamat
This work demonstrates the evaluation of stress distribution of the printed circuit boards (PCB) during the depanelling process and technique to manage it were investigated. The stress distribution of the PCB were evaluated using 4 types of PCB geometry, one without hole, one with single front hole, one with single centric hole and one with three through holes. The holes were placed in various positions to scrutinize the stress distribution of the PCB. The PCB boards were displaced with heights in the range of 1cm till 5cm. Ansys ver 11 was utilized to perform the simulation. Key results showed that the hole structures assisted in managing the stress distribution during the arching process of the PCB subjected to its position on the PCB.
本文研究了印制板拆板过程中应力分布的评估及控制技术。采用无孔、单前孔、单中心孔和三通孔4种PCB几何形状对PCB的应力分布进行了评价。这些孔被放置在不同的位置，以仔细检查PCB的应力分布。PCB板移位高度在1cm到5cm的范围内。利用Ansys ver 11进行仿真。关键结果表明，孔结构有助于控制其在PCB板上的位置在PCB板成拱过程中的应力分布。
{"title":"PCB depanelling stress distribution simulation analysis using designated thru holes","authors":"V. Retnasamy, Z. Sauli, R. Vairavan, H. Mamat","doi":"10.1109/SMELEC.2014.6920812","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920812","url":null,"abstract":"This work demonstrates the evaluation of stress distribution of the printed circuit boards (PCB) during the depanelling process and technique to manage it were investigated. The stress distribution of the PCB were evaluated using 4 types of PCB geometry, one without hole, one with single front hole, one with single centric hole and one with three through holes. The holes were placed in various positions to scrutinize the stress distribution of the PCB. The PCB boards were displaced with heights in the range of 1cm till 5cm. Ansys ver 11 was utilized to perform the simulation. Key results showed that the hole structures assisted in managing the stress distribution during the arching process of the PCB subjected to its position on the PCB.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"133 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133877290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920889
N. Azhar, S. S. Shariffudin, Z. Nurbaya, I. H. Affendi, A. Shafura, M. Rusop
Nanocomposite based on zinc oxide (ZnO) nanostructures and poly [2-methoxy-5(2'-ethylhexyloxy)-phenylene vinylene) (MEH-PPV) of various weight percent have been obtained using sol-gel method. The substrates were deposit at 0.1 wt% to 0.4 wt% of ZnO with pure MEH-PPV to investigate the concentration effect of MEH-PPV/ZnO nanocomposite. The structural properties were characterized using FESEM and AFM to obtain the morphology of nanocomposite. From the AFM, it was found that the roughness is more uniform. The optical properties were obtained using ultraviolet-visible spectrometer (UV-Vis). It was found that the transmittance band increased with decreased of weight percent of ZnO nanostructures. For photoluminescence (PL) spectra shows that 0.4 wt% of ZnO at visible emission is due to emission characterisitic of PPV backbone which is arise from the relaxtion of excited π-electron to the ground state. This study will provide better performance and suitable for optoelectronic device especially OLEDs application.
{"title":"Optical performance of MEH-PPV/ZnO nanocomposite at different weight percent for OLED applications","authors":"N. Azhar, S. S. Shariffudin, Z. Nurbaya, I. H. Affendi, A. Shafura, M. Rusop","doi":"10.1109/SMELEC.2014.6920889","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920889","url":null,"abstract":"Nanocomposite based on zinc oxide (ZnO) nanostructures and poly [2-methoxy-5(2'-ethylhexyloxy)-phenylene vinylene) (MEH-PPV) of various weight percent have been obtained using sol-gel method. The substrates were deposit at 0.1 wt% to 0.4 wt% of ZnO with pure MEH-PPV to investigate the concentration effect of MEH-PPV/ZnO nanocomposite. The structural properties were characterized using FESEM and AFM to obtain the morphology of nanocomposite. From the AFM, it was found that the roughness is more uniform. The optical properties were obtained using ultraviolet-visible spectrometer (UV-Vis). It was found that the transmittance band increased with decreased of weight percent of ZnO nanostructures. For photoluminescence (PL) spectra shows that 0.4 wt% of ZnO at visible emission is due to emission characterisitic of PPV backbone which is arise from the relaxtion of excited π-electron to the ground state. This study will provide better performance and suitable for optoelectronic device especially OLEDs application.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133349240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920817
M. Kumngern, U. Torteanchai
This paper presents a new voltage-mode universal filter with three-input and four-output using two differential difference current conveyors, two grounded capacitors and two resistors. The proposed filter is suitable for integrated circuit by using only grounded capacitor. Low-pass, band-pass, high-pass and band-stop voltage responses can be obtained simultaneously into one single topology and without component-matching condition requirements. The natural frequency and the quality factor can be controlled orthogonally by setting the passive components. PSPICE simulation results using 0.5 μm CMOS technology form MIETEC are included to confirm the theoretical analysis. The simulation results can be expressed that the proposed circuit agrees well with theory.
{"title":"Three-input four-output voltage-mode multifunction filter using two DDCCs","authors":"M. Kumngern, U. Torteanchai","doi":"10.1109/SMELEC.2014.6920817","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920817","url":null,"abstract":"This paper presents a new voltage-mode universal filter with three-input and four-output using two differential difference current conveyors, two grounded capacitors and two resistors. The proposed filter is suitable for integrated circuit by using only grounded capacitor. Low-pass, band-pass, high-pass and band-stop voltage responses can be obtained simultaneously into one single topology and without component-matching condition requirements. The natural frequency and the quality factor can be controlled orthogonally by setting the passive components. PSPICE simulation results using 0.5 μm CMOS technology form MIETEC are included to confirm the theoretical analysis. The simulation results can be expressed that the proposed circuit agrees well with theory.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123639032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920865
Rosalind Deena Kumari Selvam, C. Senthilpari, Lee Lini
The Low Voltage Low Power (LVLP) 8T, 11T, 13T and ZA SRAM cell is designed using the dynamic logic SRAM cell. The SRAM cells are implemented using pass transistor logic technique, which is mainly focused on read and write operation. The circuits are designed by using DSCH2 circuit editor and their layouts are generated by MICROWIND3 layout editor. The Layout Versus Simulation (LVS) design has been verified using BSIM 4 with 65nm technology and with a corresponding voltage of 0.7V respectively. The simulated SRAM layouts are verified and analyzed. The SRAM 8T gives power dissipation of 0.145 microwatts, propagation delay of 37.2 pico seconds, area of 14 × 8 micrometers and a throughput of 4.037 nano seconds.
{"title":"Low power and low voltage SRAM design for LDPC codes hardware applications","authors":"Rosalind Deena Kumari Selvam, C. Senthilpari, Lee Lini","doi":"10.1109/SMELEC.2014.6920865","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920865","url":null,"abstract":"The Low Voltage Low Power (LVLP) 8T, 11T, 13T and ZA SRAM cell is designed using the dynamic logic SRAM cell. The SRAM cells are implemented using pass transistor logic technique, which is mainly focused on read and write operation. The circuits are designed by using DSCH2 circuit editor and their layouts are generated by MICROWIND3 layout editor. The Layout Versus Simulation (LVS) design has been verified using BSIM 4 with 65nm technology and with a corresponding voltage of 0.7V respectively. The simulated SRAM layouts are verified and analyzed. The SRAM 8T gives power dissipation of 0.145 microwatts, propagation delay of 37.2 pico seconds, area of 14 × 8 micrometers and a throughput of 4.037 nano seconds.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121539824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920821
M. A. Ismail
Analytical-based and Monte Carlo-based are two methods available in TCAD for simulation of ion implantation step. This paper presents a selection of suitable implantation methods considering the speed and accuracy trade-off while fulfilling the calibrated TCAD requirements in MOSFET process and device simulations. Doping profiles from several device physicals such as channel, halo and source-drain structures are acquired to capture the impact of different implantation methods. The comparisons between measured and simulated doping profiles are presented to further investigate the trade-off as a function of energy levels and tilt angles. The best solution is proposed to obtain essentially calibrated TCAD simulation, without unnecessarily scarifying the simulation time.
{"title":"Impact of implantation methods on speed and accuracy trade-off in calibrated TCAD tool","authors":"M. A. Ismail","doi":"10.1109/SMELEC.2014.6920821","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920821","url":null,"abstract":"Analytical-based and Monte Carlo-based are two methods available in TCAD for simulation of ion implantation step. This paper presents a selection of suitable implantation methods considering the speed and accuracy trade-off while fulfilling the calibrated TCAD requirements in MOSFET process and device simulations. Doping profiles from several device physicals such as channel, halo and source-drain structures are acquired to capture the impact of different implantation methods. The comparisons between measured and simulated doping profiles are presented to further investigate the trade-off as a function of energy levels and tilt angles. The best solution is proposed to obtain essentially calibrated TCAD simulation, without unnecessarily scarifying the simulation time.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121666875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920827
M. Hosseinghadiry, R. Ismail, F. Fotovvatikhah, M. Khaledian, M. Saeidmanesh
A semi-analytical model for impact ionisation coefficient of graphene nanoribbon (GNR) is presented. The model is derived by calculating the probability of electrons reaching ionisation threshold energy Et and the distance travelled by electron gaining Et. In addition, ionisation threshold energy is semi-analytically modeled for GNR. We justify our assumptions using analytical modeling and comparison with simulation results. Gaussian simulator together with analytical modeling is used in order to calculate ionisation threshold energy and Kinetic Monte Carlo is employed to calculate ionisation coefficient and verify the analytical results. Finally, the ionization profile is presented using the proposed models and simulation is carried out. The results are compared with that of silicon.
{"title":"Modeling the velocity saturation region of graphene nanoribbon transistor","authors":"M. Hosseinghadiry, R. Ismail, F. Fotovvatikhah, M. Khaledian, M. Saeidmanesh","doi":"10.1109/SMELEC.2014.6920827","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920827","url":null,"abstract":"A semi-analytical model for impact ionisation coefficient of graphene nanoribbon (GNR) is presented. The model is derived by calculating the probability of electrons reaching ionisation threshold energy Et and the distance travelled by electron gaining Et. In addition, ionisation threshold energy is semi-analytically modeled for GNR. We justify our assumptions using analytical modeling and comparison with simulation results. Gaussian simulator together with analytical modeling is used in order to calculate ionisation threshold energy and Kinetic Monte Carlo is employed to calculate ionisation coefficient and verify the analytical results. Finally, the ionization profile is presented using the proposed models and simulation is carried out. The results are compared with that of silicon.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122828311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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