Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920911
S. P. Foo, K. Siow, A. Jalar
Solder printing faces challenges in print definition and sustainable volume transfer as the microelectronic industry migrates to smaller footprints. Nano-sized alloy particles mitigate these issues by modifying the solder formulation and rheology. We propose an electrodeposition method using reverse microemulsion (without reducing agent) as electrolyte to synthesize Sn-Ag-Cu solder alloy nanoparticle. SnCl2.2H2O, Ag2SO4 and CuSO4 are used as the precursor. N-hexane, TritonX-100 and n-hexanol are used as oil phase, surfactant and co-surfactant, respectively. Three volume ratios of aqueous to surfactant phase, Wo are carried out namely: 0.20, 0.40 and 0.60 but only the ratio of 4.5:1.0 is able to synthesize the nano-sized SAC particles. Scanning electron microscopy shows the spherical SAC particles are well dispersed and their sizes range from 15 to 90 nm. X-ray diffraction spectra show the formation of Sn, Ag3Sn and Cu6Sn5 without any oxide peaks in the synthesized nanoparticles; their absence suggests the effectiveness of the surfactants in protecting the alloy particles from oxidation. This electrodeposition method compares favourably to the microemulsion (with reducing agent) method in producing spherical and well-distributed nanosized solder particles.
{"title":"Synthesizing SnAgCu nanoparticles by electrodeposition of reverse microemulsion electrolyte","authors":"S. P. Foo, K. Siow, A. Jalar","doi":"10.1109/SMELEC.2014.6920911","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920911","url":null,"abstract":"Solder printing faces challenges in print definition and sustainable volume transfer as the microelectronic industry migrates to smaller footprints. Nano-sized alloy particles mitigate these issues by modifying the solder formulation and rheology. We propose an electrodeposition method using reverse microemulsion (without reducing agent) as electrolyte to synthesize Sn-Ag-Cu solder alloy nanoparticle. SnCl2.2H2O, Ag2SO4 and CuSO4 are used as the precursor. N-hexane, TritonX-100 and n-hexanol are used as oil phase, surfactant and co-surfactant, respectively. Three volume ratios of aqueous to surfactant phase, Wo are carried out namely: 0.20, 0.40 and 0.60 but only the ratio of 4.5:1.0 is able to synthesize the nano-sized SAC particles. Scanning electron microscopy shows the spherical SAC particles are well dispersed and their sizes range from 15 to 90 nm. X-ray diffraction spectra show the formation of Sn, Ag3Sn and Cu6Sn5 without any oxide peaks in the synthesized nanoparticles; their absence suggests the effectiveness of the surfactants in protecting the alloy particles from oxidation. This electrodeposition method compares favourably to the microemulsion (with reducing agent) method in producing spherical and well-distributed nanosized solder particles.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131355413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920912
Chen-Chen Chung, K. Lin, H. Yu, Nguyen-Hong Quan, C. Dee, E. Chang
A new design where ZnO nanotubes were grown on the antireflection (AR) layer coated on triple-junction (T-J) solar cell devices to enhance the light conversion efficiency. Compared to the bare T-J solar cells (without an AR layer), the performance of Si3N4 AR coated solar cell showed improvement. The sample with a layer of ZnO nanotubes grown in top of AR layer showed the lowest light reflection compared with the bare and solely AR coated T-J solar cell especially in the spectrum range of 350-500 nm. The use of ZnO nanotubes have increased the conversion efficiency by 4.9% compared with the conventional T-J solar cell. While the Si3N4 AR coated sample only increased the conversion efficiency by 3.2%. This result is quite encouraging as further refinement and variation in the experiment procedures could possibly bring more exciting performance in the future.
{"title":"Hydrothermal growth of ZnO nanotubes on InGaP/GaAs/Ge solar cells","authors":"Chen-Chen Chung, K. Lin, H. Yu, Nguyen-Hong Quan, C. Dee, E. Chang","doi":"10.1109/SMELEC.2014.6920912","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920912","url":null,"abstract":"A new design where ZnO nanotubes were grown on the antireflection (AR) layer coated on triple-junction (T-J) solar cell devices to enhance the light conversion efficiency. Compared to the bare T-J solar cells (without an AR layer), the performance of Si3N4 AR coated solar cell showed improvement. The sample with a layer of ZnO nanotubes grown in top of AR layer showed the lowest light reflection compared with the bare and solely AR coated T-J solar cell especially in the spectrum range of 350-500 nm. The use of ZnO nanotubes have increased the conversion efficiency by 4.9% compared with the conventional T-J solar cell. While the Si3N4 AR coated sample only increased the conversion efficiency by 3.2%. This result is quite encouraging as further refinement and variation in the experiment procedures could possibly bring more exciting performance in the future.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133437846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920847
Umi Milhana Jamain, Nur Hidayah Ibrahim, R. A. Rahim
This paper presents the design and analysis of MEMS piezoelectric energy harvester. Zinc oxide (ZnO) MEMS piezoelectric energy harvester has been utilized as piezoelectrically active cantilever for mechanical to electrical transduction. A COMSOL Multiphysics model was used which provide accurate information on the frequency, stress and voltage output of a ZnO piezoelectric energy harvester. Few design parameters have been studied which are rectangular cantilever, triangular cantilever, rectangular cantilever with proof mass and using different types of piezoelectric materials. The effects of varying geometrical dimensions of the device were also investigated. From simulation results, it was found out that ZnO piezoelectric energy harvester with the length of 150 μm, width 50 μm and thickness of 4 μm generates 9.9184 V electric potential under the resonance frequency of 0.71 MHz and 1 μN/m2 mechanical force applied.
{"title":"Performance analysis of zinc oxide piezoelectric MEMS energy harvester","authors":"Umi Milhana Jamain, Nur Hidayah Ibrahim, R. A. Rahim","doi":"10.1109/SMELEC.2014.6920847","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920847","url":null,"abstract":"This paper presents the design and analysis of MEMS piezoelectric energy harvester. Zinc oxide (ZnO) MEMS piezoelectric energy harvester has been utilized as piezoelectrically active cantilever for mechanical to electrical transduction. A COMSOL Multiphysics model was used which provide accurate information on the frequency, stress and voltage output of a ZnO piezoelectric energy harvester. Few design parameters have been studied which are rectangular cantilever, triangular cantilever, rectangular cantilever with proof mass and using different types of piezoelectric materials. The effects of varying geometrical dimensions of the device were also investigated. From simulation results, it was found out that ZnO piezoelectric energy harvester with the length of 150 μm, width 50 μm and thickness of 4 μm generates 9.9184 V electric potential under the resonance frequency of 0.71 MHz and 1 μN/m2 mechanical force applied.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125428353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920798
Mohd H. S. Alrashdan, A. A. Hamzah, B. Majlis, Mohd Faizal Aziz
Aluminum nitride thin film depositions at a low temperature become one of the most promising fields in micro-electro mechanical systems and in the semiconductor industry; because of its good compatibility with designs on silicon substrates, its mechanically strong, chemically stable, wide bandgap energy (≈6.2 eV), and has a large electro-mechanical coupling constant. An AlN thin film deposition using DC Magnetron sputtering have the advantage over other deposition methods due to its simplicity, better parameter control, cheapness, and requires a low deposition temperature. The NTI nano film DC sputtering system was used to deposit the AlN thin film with 99.99% pure aluminum target material and 100 silicon substrates, the working temperature is at 20C°, there is a 10Cm separation distance between the target and the substrate, 335~351 V cathode voltage, the foreline and base pressures are 2×10-2 T, 4×10-5 T respectively, and uses 200W DC power. We vary the time and nitrogen/argon gas flow ratio. Deposited film was characterized by X-ray diffraction and (002) of wurtzite hexagonal phase of AlN thin film was found with beak intensity of 800 count per second for 50% nitrogen content. Field Emission Scanning Electron Microscopy was used to study thin film cross section, film thicknesses and deposition flow rate at different times and gas flow ratio, there is inverse relationship between nitrogen gas percentage deposition and flow rate. Deposition flow rate are 4.12 nm/ min for 50% nitrogen and 2.217 nm/min for 75% of nitrogen content.
{"title":"Aluminum nitride thin film deposition using DC sputtering","authors":"Mohd H. S. Alrashdan, A. A. Hamzah, B. Majlis, Mohd Faizal Aziz","doi":"10.1109/SMELEC.2014.6920798","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920798","url":null,"abstract":"Aluminum nitride thin film depositions at a low temperature become one of the most promising fields in micro-electro mechanical systems and in the semiconductor industry; because of its good compatibility with designs on silicon substrates, its mechanically strong, chemically stable, wide bandgap energy (≈6.2 eV), and has a large electro-mechanical coupling constant. An AlN thin film deposition using DC Magnetron sputtering have the advantage over other deposition methods due to its simplicity, better parameter control, cheapness, and requires a low deposition temperature. The NTI nano film DC sputtering system was used to deposit the AlN thin film with 99.99% pure aluminum target material and 100 silicon substrates, the working temperature is at 20C°, there is a 10Cm separation distance between the target and the substrate, 335~351 V cathode voltage, the foreline and base pressures are 2×10-2 T, 4×10-5 T respectively, and uses 200W DC power. We vary the time and nitrogen/argon gas flow ratio. Deposited film was characterized by X-ray diffraction and (002) of wurtzite hexagonal phase of AlN thin film was found with beak intensity of 800 count per second for 50% nitrogen content. Field Emission Scanning Electron Microscopy was used to study thin film cross section, film thicknesses and deposition flow rate at different times and gas flow ratio, there is inverse relationship between nitrogen gas percentage deposition and flow rate. Deposition flow rate are 4.12 nm/ min for 50% nitrogen and 2.217 nm/min for 75% of nitrogen content.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125877634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920845
M. M. Noor, G. Sugandi, Mohd Faizal Aziz, B. Majlis
The material selection for membrane is important in designing a microheater. A membrane is used as an insulator layer to prevent heat dissipation from the microheater to the substrate. At the same time, the thermal characteristic of the microheater is influenced by the insulator layer. A study on the effects of material and membrane structure on the maximum temperature of the microheater for gas sensor applications has been carried out using Heat Transfer Module of COMSOL 4.2. Three different membrane materials namely silicon nitride (Si3N4), silicon dioxide (SiO2) and polyimide and two types of membrane structures namely full-membrane and bridgemembrane have been chosen for the study. Their effects on the microheater temperature are presented. The resistive meander type of microheater is used in this study. The heater material is platinum. The thickness and the area of the heater are 2 μm and 600 μm × 680 μm respectively. The thickness of each membrane is 5 μm. The area of the full-membrane and the bridgemembrane are 2500 μm × 2500 μm and 850 μm × 850 μm respectively.
{"title":"Effects of material and membrane structure on maximum temperature of microheater for gas sensor applications","authors":"M. M. Noor, G. Sugandi, Mohd Faizal Aziz, B. Majlis","doi":"10.1109/SMELEC.2014.6920845","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920845","url":null,"abstract":"The material selection for membrane is important in designing a microheater. A membrane is used as an insulator layer to prevent heat dissipation from the microheater to the substrate. At the same time, the thermal characteristic of the microheater is influenced by the insulator layer. A study on the effects of material and membrane structure on the maximum temperature of the microheater for gas sensor applications has been carried out using Heat Transfer Module of COMSOL 4.2. Three different membrane materials namely silicon nitride (Si3N4), silicon dioxide (SiO2) and polyimide and two types of membrane structures namely full-membrane and bridgemembrane have been chosen for the study. Their effects on the microheater temperature are presented. The resistive meander type of microheater is used in this study. The heater material is platinum. The thickness and the area of the heater are 2 μm and 600 μm × 680 μm respectively. The thickness of each membrane is 5 μm. The area of the full-membrane and the bridgemembrane are 2500 μm × 2500 μm and 850 μm × 850 μm respectively.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128210445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920797
N. Hadis, Asrulnizam Abd Manaf, S. H. Herman
The I-V characteristic effect of thin film TiO2 fluidic-based memristor sensor utilized in sensing various glucose concentrations is described in this paper. Four different glucose concentrations, namely, 5, 10, 20, and 30 mM, are prepared and applied to the sensor. The device is then characterized with Keithley 4200-SCS semiconductor characterization system. Results show that different concentration levels of glucose affect the I-V characteristic of the sensor device. The difference is observed at the first voltage sweep of 0 V to 3 V after glucose was applied. A uniform change in current was recorded for small voltages below 0.9 V. The current decreases as the glucose concentration increases. Analysis shows that the resistance of the memristor sensor increases with the increase in glucose concentration through a quadratic relation.
{"title":"I-V characteristic effects of fluidic-based memristor for glucose concentration detection","authors":"N. Hadis, Asrulnizam Abd Manaf, S. H. Herman","doi":"10.1109/SMELEC.2014.6920797","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920797","url":null,"abstract":"The I-V characteristic effect of thin film TiO2 fluidic-based memristor sensor utilized in sensing various glucose concentrations is described in this paper. Four different glucose concentrations, namely, 5, 10, 20, and 30 mM, are prepared and applied to the sensor. The device is then characterized with Keithley 4200-SCS semiconductor characterization system. Results show that different concentration levels of glucose affect the I-V characteristic of the sensor device. The difference is observed at the first voltage sweep of 0 V to 3 V after glucose was applied. A uniform change in current was recorded for small voltages below 0.9 V. The current decreases as the glucose concentration increases. Analysis shows that the resistance of the memristor sensor increases with the increase in glucose concentration through a quadratic relation.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130439000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920822
M. Kumngern
This study presents a new active building block for analog signal processing applications, namely fully differential current conveyor transconductance amplifier. The proposed circuit is realized using differential difference current conveyors and transconductance amplifiers. Unlike, previous building blocks, both fully differential input and electronic tuning capability can be obtained into a single new device. The proposed building block is used to realize a universal biquadratic filter as an example application. PSPICE simulation results using 0.5 μm CMOS technology from MIETEC are used to confirm the presented building block. The simulation results express that the proposed active building block can be used to realize analog signal processing circuits.
{"title":"FDCCTA: The active building block for analog signal processing applications","authors":"M. Kumngern","doi":"10.1109/SMELEC.2014.6920822","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920822","url":null,"abstract":"This study presents a new active building block for analog signal processing applications, namely fully differential current conveyor transconductance amplifier. The proposed circuit is realized using differential difference current conveyors and transconductance amplifiers. Unlike, previous building blocks, both fully differential input and electronic tuning capability can be obtained into a single new device. The proposed building block is used to realize a universal biquadratic filter as an example application. PSPICE simulation results using 0.5 μm CMOS technology from MIETEC are used to confirm the presented building block. The simulation results express that the proposed active building block can be used to realize analog signal processing circuits.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133471771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920901
Wong Goon Weng, Norhayati Binti Soin
In this paper, the theoretical configuration geometry of the layout on-chip meander line resistor was studied and investigated. Various simulation of the geometric design on-chip resistor in a range Giga Hertz frequency are performed. The effect of the quality factor of each design geometry of meander line resistor on high frequency operation was in deep studied and discussed. Besides, parameter extraction geometry of this on-chip meander line resistor was introduced. As a result, the parameter line length (h), line segment (N) and then following by spacing (d) and width (w), which are playing an important role on designing the geometry layout to improve the Q-factor. Throughout the scaling graphical method, it has been granted out optimize value combination of parameter by improving almost 70% of Q-factor and loss of resistance less than 17% of the nominal design. The result of the Design optimization configuration has low Q-factor when compared with a nominal Design nominal configuration. This is because of the large value of number segment (N) and smaller numbers of line length (h), which has less coupling effect and less resistivity effect. All result base on mathematics computation data was discussed and performed.
{"title":"Theoretical study of on-chip meander line resistor to improve Q-factor","authors":"Wong Goon Weng, Norhayati Binti Soin","doi":"10.1109/SMELEC.2014.6920901","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920901","url":null,"abstract":"In this paper, the theoretical configuration geometry of the layout on-chip meander line resistor was studied and investigated. Various simulation of the geometric design on-chip resistor in a range Giga Hertz frequency are performed. The effect of the quality factor of each design geometry of meander line resistor on high frequency operation was in deep studied and discussed. Besides, parameter extraction geometry of this on-chip meander line resistor was introduced. As a result, the parameter line length (h), line segment (N) and then following by spacing (d) and width (w), which are playing an important role on designing the geometry layout to improve the Q-factor. Throughout the scaling graphical method, it has been granted out optimize value combination of parameter by improving almost 70% of Q-factor and loss of resistance less than 17% of the nominal design. The result of the Design optimization configuration has low Q-factor when compared with a nominal Design nominal configuration. This is because of the large value of number segment (N) and smaller numbers of line length (h), which has less coupling effect and less resistivity effect. All result base on mathematics computation data was discussed and performed.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114073296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920888
A. Ishak, M. F. Malek, M. Rusop
The boron doped amorphous carbon were prepared by in-situ mixing of hydrocarbon palm oil and boron dopant and carrier gas, argon in the chamber by using bias assisted pyrolysis-CVD. The effect of substrate bias on the thickness, electrical and electronic properties of a-C:B film were investigated. The fabricated solar cell with the configuration of Au/p-C:B/n-Si/Au achieved conversion efficiency (r) of 0.453% at applied bias voltage of -20 V. This result showed the successful interstitial doping of boron in the amorphous carbon films deposited by this method and palm oil precursor as confirmed by the fill factor, open circuit voltage, and current density results.
{"title":"Properties of boron doped amorphous carbon films by carbon palm oil for carbon based solar cell applications","authors":"A. Ishak, M. F. Malek, M. Rusop","doi":"10.1109/SMELEC.2014.6920888","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920888","url":null,"abstract":"The boron doped amorphous carbon were prepared by in-situ mixing of hydrocarbon palm oil and boron dopant and carrier gas, argon in the chamber by using bias assisted pyrolysis-CVD. The effect of substrate bias on the thickness, electrical and electronic properties of a-C:B film were investigated. The fabricated solar cell with the configuration of Au/p-C:B/n-Si/Au achieved conversion efficiency (r) of 0.453% at applied bias voltage of -20 V. This result showed the successful interstitial doping of boron in the amorphous carbon films deposited by this method and palm oil precursor as confirmed by the fill factor, open circuit voltage, and current density results.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115089919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920814
Nurul Huda Abdul Rahman, M. Arshad, N. Othman, M. Fathil, M. S. Nur Humaira, U. Hashim
In this paper, we investigate the channel length (LCH) of the silicon-on-insulator (SOI) n-type tunneling field effect transistor (NTFET) with the respect of device performance. 2D-device simulation was used for simulating the devices with 30 nm gate length of SOI NTFET with 10 nm thin buried oxide (tBOX) and 7 nm thin silicon body (tsi). The device performance, such as threshold voltage (VTH), ON current (ION), OFF current (IOFF), and subthreshold swing (SS) was extracted from the current-voltage characterizations of SOI NTFET. The longer the channel length, the lower the SS value and ION/IOFF ratio obtained in these simulations. Unfortunately, the SS values obtained throughout these simulations were still higher than the typical SS value of TFET device which is supposed to be lower than 60 mV/decade. However, the SS values obtained was still lower compared to the SS value of the MOSFET. On the other hand, ION/IOFF ratio still high which is better for switching operation of the devices.
{"title":"The impact of scaled channel length in tunneling field effect transistors (TFETs)","authors":"Nurul Huda Abdul Rahman, M. Arshad, N. Othman, M. Fathil, M. S. Nur Humaira, U. Hashim","doi":"10.1109/SMELEC.2014.6920814","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920814","url":null,"abstract":"In this paper, we investigate the channel length (LCH) of the silicon-on-insulator (SOI) n-type tunneling field effect transistor (NTFET) with the respect of device performance. 2D-device simulation was used for simulating the devices with 30 nm gate length of SOI NTFET with 10 nm thin buried oxide (tBOX) and 7 nm thin silicon body (tsi). The device performance, such as threshold voltage (VTH), ON current (ION), OFF current (IOFF), and subthreshold swing (SS) was extracted from the current-voltage characterizations of SOI NTFET. The longer the channel length, the lower the SS value and ION/IOFF ratio obtained in these simulations. Unfortunately, the SS values obtained throughout these simulations were still higher than the typical SS value of TFET device which is supposed to be lower than 60 mV/decade. However, the SS values obtained was still lower compared to the SS value of the MOSFET. On the other hand, ION/IOFF ratio still high which is better for switching operation of the devices.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116715103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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