Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920824
S. Norhafiezah, R. M. Ayub, M. Arshad, A. H. Azman, M. F. Fatin, M. A. Farehanim, U. Hashim
Titanium dioxide (TiO2) thin film is deposited using Reactive Radio Frequency (RF) sputtering on Si (100) wafer and annealed in N2 for 2 hours at different temperatures i.e. 500°C, 750°C and 1100°C. The TiO2 peak is characterized using X-ray diffraction (XRD). At 500°C and 750°C, only anatase peak is observed with the grain size of 150.72 nm and 186.51 respectively. As the temperature increase to 1100°C, both anatase and rutile structures start to grow but the grain size is reduced to 67.88 nm. The confirmation of grain and the surface roughness is determined by using atomic force microscopy (AFM). The grain sizes become larger from 66.58 nm to 86.01 nm as the temperature increase from 500°C to 750°C as well as the surface roughness (0.271 nm to 1.201 nm). However, at 1100°C, grain size shows no significant different i.e. 84.41 nm (compared at 750°C) and slightly higher surface roughness of 2.194 nm. Thus, the 1100°C annealing temperature requires to attain rutile structure and the smaller particle size. The electrical properties of TiO2 film annealed at 1100°C shows small amount of current flow through the device thus will be suitable to be used in biosensor application.
{"title":"The annealing temperature effect on the structure and electrical properties of titanium dioxide (TiO2) film deposited by reactive RF sputtering","authors":"S. Norhafiezah, R. M. Ayub, M. Arshad, A. H. Azman, M. F. Fatin, M. A. Farehanim, U. Hashim","doi":"10.1109/SMELEC.2014.6920824","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920824","url":null,"abstract":"Titanium dioxide (TiO2) thin film is deposited using Reactive Radio Frequency (RF) sputtering on Si (100) wafer and annealed in N2 for 2 hours at different temperatures i.e. 500°C, 750°C and 1100°C. The TiO2 peak is characterized using X-ray diffraction (XRD). At 500°C and 750°C, only anatase peak is observed with the grain size of 150.72 nm and 186.51 respectively. As the temperature increase to 1100°C, both anatase and rutile structures start to grow but the grain size is reduced to 67.88 nm. The confirmation of grain and the surface roughness is determined by using atomic force microscopy (AFM). The grain sizes become larger from 66.58 nm to 86.01 nm as the temperature increase from 500°C to 750°C as well as the surface roughness (0.271 nm to 1.201 nm). However, at 1100°C, grain size shows no significant different i.e. 84.41 nm (compared at 750°C) and slightly higher surface roughness of 2.194 nm. Thus, the 1100°C annealing temperature requires to attain rutile structure and the smaller particle size. The electrical properties of TiO2 film annealed at 1100°C shows small amount of current flow through the device thus will be suitable to be used in biosensor application.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125464870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920910
A. Iqbal, F. Mohd-Yasin, S. Dimitrijev
In this paper we present the design and simulation of a bio-sensor for pathogens detection based on AlN/3C-SiC/Si piezoelectric cantilever. Cubic silicon carbide (3C-SiC) is chosen as the base layer due to its excellent material properties and chemical inertness over silicon in harsh environmental conditions. Aluminum nitride (AlN) is selected as piezoelectric active layer due to its similar thermal expansion coefficient with silicon carbide to reduce thermal stress. The desired resonant frequency of 157.16 KHz is optimized using Matlab and the finite element analysis is carried out using COMSOL software to verify the shift in the resonant frequency due to the added mass of the bacteria. The surface functionalizations of the SiC as biosensor, as well as the fabrication recipes are also proposed.
{"title":"Design optimization and finite element analysis of AlN/3C-SiC piezoelectric bio-sensors","authors":"A. Iqbal, F. Mohd-Yasin, S. Dimitrijev","doi":"10.1109/SMELEC.2014.6920910","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920910","url":null,"abstract":"In this paper we present the design and simulation of a bio-sensor for pathogens detection based on AlN/3C-SiC/Si piezoelectric cantilever. Cubic silicon carbide (3C-SiC) is chosen as the base layer due to its excellent material properties and chemical inertness over silicon in harsh environmental conditions. Aluminum nitride (AlN) is selected as piezoelectric active layer due to its similar thermal expansion coefficient with silicon carbide to reduce thermal stress. The desired resonant frequency of 157.16 KHz is optimized using Matlab and the finite element analysis is carried out using COMSOL software to verify the shift in the resonant frequency due to the added mass of the bacteria. The surface functionalizations of the SiC as biosensor, as well as the fabrication recipes are also proposed.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127791868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920823
F. Larki, A. Dehzangi, S. Ali, A. Jalar, M. Islam, B. Majlis, E. Saion, M. Hamidon, S. D. Hutagalung
The variation of electrical characteristics with nano size air gap variation between gates and channel of a pinch off lateral gate transistor were investigated using 3D Technology Computer Aided Design. It is found that smaller nanosize gaps which can be formed by approaching the lateral gates to the channel can improve the switching performance of the device significantly. Devices with different air gap demonstrate same on state current and maximum transconductance of 0.05 μS, however the on/off current ratio (ION/IOFF) is varied by three orders of magnitude. The parameters such as electric field and band energy variation are investigated in order to explain the variation of electrical characteristics by air gap variation.
{"title":"Dependency of electrical characteristics on nano gap variation in pinch off lateral gate transistors","authors":"F. Larki, A. Dehzangi, S. Ali, A. Jalar, M. Islam, B. Majlis, E. Saion, M. Hamidon, S. D. Hutagalung","doi":"10.1109/SMELEC.2014.6920823","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920823","url":null,"abstract":"The variation of electrical characteristics with nano size air gap variation between gates and channel of a pinch off lateral gate transistor were investigated using 3D Technology Computer Aided Design. It is found that smaller nanosize gaps which can be formed by approaching the lateral gates to the channel can improve the switching performance of the device significantly. Devices with different air gap demonstrate same on state current and maximum transconductance of 0.05 μS, however the on/off current ratio (ION/IOFF) is varied by three orders of magnitude. The parameters such as electric field and band energy variation are investigated in order to explain the variation of electrical characteristics by air gap variation.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127942805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920777
A. Nathan
Summary form only given. Oxide semiconductors are known for their optical transparency and high electron mobility even when processed at room temperature, making them a promising candidate for the next-generation thin film transistor (TFT) technology. Compared to existing well-established TFT technologies, the oxide transistor shows superiority in terms of process simplicity and cost, and stable device behaviour in the dark. While its non-uniformity over large areas is comparable to that of thin film silicon transistors, its photo-instability at low wavelengths can be an issue due to persistence in photoconductivity. This talk will discuss progress and issues related to oxide transistors for large area applications, and in particular, show how the material can be tuned for displays and imaging applications.
{"title":"Amorphous oxide electronics","authors":"A. Nathan","doi":"10.1109/SMELEC.2014.6920777","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920777","url":null,"abstract":"Summary form only given. Oxide semiconductors are known for their optical transparency and high electron mobility even when processed at room temperature, making them a promising candidate for the next-generation thin film transistor (TFT) technology. Compared to existing well-established TFT technologies, the oxide transistor shows superiority in terms of process simplicity and cost, and stable device behaviour in the dark. While its non-uniformity over large areas is comparable to that of thin film silicon transistors, its photo-instability at low wavelengths can be an issue due to persistence in photoconductivity. This talk will discuss progress and issues related to oxide transistors for large area applications, and in particular, show how the material can be tuned for displays and imaging applications.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129975063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920870
Siti Musliha Ajmal Binti Mokhtar, W. Abdullah
Locking speed and operating frequency range of DLL is limited to the delays of its VCDL. Since memristor resistance changes according to external bias, memristor can be used as programmable resistor. In this paper, memristor is applied to VCDL as variable resistor where the memristor resistance regulates total delay of the VCDL. VCDL consists of current starved inverter as the delay unit. A voltage to current converter (VCC) is used to convert control voltage from capacitor, Vc to control current, Ic. The control current, Ic with memristor resistance generates new voltage, Vr that regulates the delay. Compared to conventional DLL, the proposed DLL design offers one more control parameter which is Vr. By applying memristor to the DLL, the control voltage Vc can be further manipulated. Simulation results show that proposed DLL with memristor has higher locking speed and can lock higher input frequency compared to conventional DLL without memristor. Therefore, higher locking speed and wide operating frequency range are both achievable by proposed DLL with memristor.
{"title":"Memristor applied in delay locked loop for high lock speed and wide frequency range","authors":"Siti Musliha Ajmal Binti Mokhtar, W. Abdullah","doi":"10.1109/SMELEC.2014.6920870","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920870","url":null,"abstract":"Locking speed and operating frequency range of DLL is limited to the delays of its VCDL. Since memristor resistance changes according to external bias, memristor can be used as programmable resistor. In this paper, memristor is applied to VCDL as variable resistor where the memristor resistance regulates total delay of the VCDL. VCDL consists of current starved inverter as the delay unit. A voltage to current converter (VCC) is used to convert control voltage from capacitor, Vc to control current, Ic. The control current, Ic with memristor resistance generates new voltage, Vr that regulates the delay. Compared to conventional DLL, the proposed DLL design offers one more control parameter which is Vr. By applying memristor to the DLL, the control voltage Vc can be further manipulated. Simulation results show that proposed DLL with memristor has higher locking speed and can lock higher input frequency compared to conventional DLL without memristor. Therefore, higher locking speed and wide operating frequency range are both achievable by proposed DLL with memristor.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130015728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920791
Aqilah Binti Abdul Tahrim, M. Tan
The FinFET based Full Adder in various cell designs is investigated in terms of performance and energy efficiency. Additionally, the performance of the FinFET Full Adder in the subthreshold region reveals significant results in low power technology. The 1-bit FinFET based Full Adder is designed in four different cell designs, and while the average power dissipated, delays, power-delay-product (PDP) and energy-delay-product (EDP) of all four topologies were analyzed based on the types of transistors used i.e. conventional Field Oxide Transistor (MOSFET) and FinFET. Based on this study, FinFET based Full Adder shows an average of 94 % reduction in delay, 97 % reduction in power dissipation and 99 % reduction for both PDP and EDP over the conventional FET, giving FinFET advantages in energy efficiency.
{"title":"Design and implementation of a 1-bit FinFET Full Adder cell for ALU in subthreshold region","authors":"Aqilah Binti Abdul Tahrim, M. Tan","doi":"10.1109/SMELEC.2014.6920791","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920791","url":null,"abstract":"The FinFET based Full Adder in various cell designs is investigated in terms of performance and energy efficiency. Additionally, the performance of the FinFET Full Adder in the subthreshold region reveals significant results in low power technology. The 1-bit FinFET based Full Adder is designed in four different cell designs, and while the average power dissipated, delays, power-delay-product (PDP) and energy-delay-product (EDP) of all four topologies were analyzed based on the types of transistors used i.e. conventional Field Oxide Transistor (MOSFET) and FinFET. Based on this study, FinFET based Full Adder shows an average of 94 % reduction in delay, 97 % reduction in power dissipation and 99 % reduction for both PDP and EDP over the conventional FET, giving FinFET advantages in energy efficiency.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124343694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920783
S. Shukla, Beena Pandey
A New circuit model of two-stage small-signal amplifier using Darlington and Sziklai pairs is proposed for the first time. Proposed circuit is obtained by cascading a small-signal Darlington pair amplifier with that of Sziklai pair based small-signal amplifier with minor modifications. Proposed amplifier essentially uses two additional biasing resistances in its design. It crops considerably high voltage and current gain (345.523 and 464.357 respectively) with audible range bandwidth of 43.363 KHz for AC input signals swinging in 10-30mV range at 1KHz or lower frequency. Proposed circuit-architecture successfully removes the poor response problem of conventional Darlington pair amplifiers at higher frequencies and narrow bandwidth problem of recently announced (by authors) circuits of small-signal Sziklai pair amplifier. Variations in voltage gain with frequency and various biasing components like biasing resistances, DC supply voltage and coupling capacitors are discussed in length. Temperature sensitivity of performance parameters, THD and small-signal AC equivalent circuit analysis of the proposed circuit are elaborately studied. Proposed design can be implemented in cascadable gain blocks for receivers, 715Hz-44KHz frequency range power sources and in the circuits where reproduction of signal with simultaneously high voltage and current gain is the prime requirement.
{"title":"Two-stage small-signal amplifier with Darlington and Sziklai pairs","authors":"S. Shukla, Beena Pandey","doi":"10.1109/SMELEC.2014.6920783","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920783","url":null,"abstract":"A New circuit model of two-stage small-signal amplifier using Darlington and Sziklai pairs is proposed for the first time. Proposed circuit is obtained by cascading a small-signal Darlington pair amplifier with that of Sziklai pair based small-signal amplifier with minor modifications. Proposed amplifier essentially uses two additional biasing resistances in its design. It crops considerably high voltage and current gain (345.523 and 464.357 respectively) with audible range bandwidth of 43.363 KHz for AC input signals swinging in 10-30mV range at 1KHz or lower frequency. Proposed circuit-architecture successfully removes the poor response problem of conventional Darlington pair amplifiers at higher frequencies and narrow bandwidth problem of recently announced (by authors) circuits of small-signal Sziklai pair amplifier. Variations in voltage gain with frequency and various biasing components like biasing resistances, DC supply voltage and coupling capacitors are discussed in length. Temperature sensitivity of performance parameters, THD and small-signal AC equivalent circuit analysis of the proposed circuit are elaborately studied. Proposed design can be implemented in cascadable gain blocks for receivers, 715Hz-44KHz frequency range power sources and in the circuits where reproduction of signal with simultaneously high voltage and current gain is the prime requirement.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"8 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124592375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920776
E. Chang
Summary form only given. Wide band gap semiconductor of GaN and its related materials are promising for future power and high frequency applications. In particular, the GaN high electron mobility transistor (HEMT) grown on large-size Si substrate is suitable for low-lost and high power switching applications. The GaN HEMT could be fabricated into convertors and invertors for electrified vehicle (EV). In order to achieve GaN HEMT device with high efficiency, various issues have to be considered. These include the careful design of material structure and device layout. Furthermore, surface passivation techniques are critical for reducing dynamic on-resistance (Ron) and improving reliability. For safety purpose, a normally-off device is required. Thus, the pros and cons of normally-off device fabrication approaches such as gate-recessed, p-GaN cap and F-plasma treatment will be discussed. The possibility of using fully-copper-based metallization will also be addressed. The copper metallization can reduce the fabrication cost effectively by replacing the conventional gold metallization. Finally, power module is demonstrated by employing the GaN HEMTs and Schottky barrier diodes. For future RF power application, GaN HEMTs on SiC substrate are fabricated. The GaN material grown on SiC can achieve better crystal quality and the HEMT devices are also beneficial from better thermal dissipation due to high thermal conductivity SiC substrate. GaN HEMT on SiC could be used in future high frequency applications such as formilitary phased array radar and civilian 4th-generation base station. Besides the AlGaN/GaN HEMT structure, new material structures such as InAlN/GaN and AlN/GaN are also demonstrated. These structures have great potential for very high frequency (>300 GHz) and high power applications.
{"title":"Realization of GaN-based technology for high power and high frequency applications","authors":"E. Chang","doi":"10.1109/SMELEC.2014.6920776","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920776","url":null,"abstract":"Summary form only given. Wide band gap semiconductor of GaN and its related materials are promising for future power and high frequency applications. In particular, the GaN high electron mobility transistor (HEMT) grown on large-size Si substrate is suitable for low-lost and high power switching applications. The GaN HEMT could be fabricated into convertors and invertors for electrified vehicle (EV). In order to achieve GaN HEMT device with high efficiency, various issues have to be considered. These include the careful design of material structure and device layout. Furthermore, surface passivation techniques are critical for reducing dynamic on-resistance (Ron) and improving reliability. For safety purpose, a normally-off device is required. Thus, the pros and cons of normally-off device fabrication approaches such as gate-recessed, p-GaN cap and F-plasma treatment will be discussed. The possibility of using fully-copper-based metallization will also be addressed. The copper metallization can reduce the fabrication cost effectively by replacing the conventional gold metallization. Finally, power module is demonstrated by employing the GaN HEMTs and Schottky barrier diodes. For future RF power application, GaN HEMTs on SiC substrate are fabricated. The GaN material grown on SiC can achieve better crystal quality and the HEMT devices are also beneficial from better thermal dissipation due to high thermal conductivity SiC substrate. GaN HEMT on SiC could be used in future high frequency applications such as formilitary phased array radar and civilian 4th-generation base station. Besides the AlGaN/GaN HEMT structure, new material structures such as InAlN/GaN and AlN/GaN are also demonstrated. These structures have great potential for very high frequency (>300 GHz) and high power applications.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122573366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920846
Norazreen Abd Aziz, B. Bais, M. R. Buyong, B. Majlis, A. Nordin
In this paper, we discussed simulation of several annular surface acoustic wave (A-SAW) devices using various wavelengths to identify its effects on the focusing properties and to analyze the propagation of Rayleigh waves in piezoelectric substrate. By choosing Y-cut Z propagating Lithium Niobate as the substrate and aluminum electrodes as the IDT, we modeled the A-SAW devices using Comsol Multiphysics. We used 8 pairs of annular electrodes with thickness of 1 μm with three different design's wavelength of 100 μm, 150 μm and 200 μm, respectively. To minimize the computational time in determining the optimum frequency i.e. resonant frequency of the device, only one pair of electrode for each design is simulated under eigenfrequency analysis in 2D piezoelectric (pzd) module. To understand the Rayleigh waves behavior, simulation of the whole device structure was done under frequency domain analysis in 2D-axisymmetric piezoelectric module. From the simulation results, it can be observed that SAW displacement profiles, electric potential field and operating frequency are significantly influenced by the wavelength. The formation of focused acoustic waves at the center of A-SAW device suits them in biosensing and microfluidic actuation applications that require detection or manipulation of localized variations.
{"title":"FEM analysis of wavelength effects in piezoelectric substrate","authors":"Norazreen Abd Aziz, B. Bais, M. R. Buyong, B. Majlis, A. Nordin","doi":"10.1109/SMELEC.2014.6920846","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920846","url":null,"abstract":"In this paper, we discussed simulation of several annular surface acoustic wave (A-SAW) devices using various wavelengths to identify its effects on the focusing properties and to analyze the propagation of Rayleigh waves in piezoelectric substrate. By choosing Y-cut Z propagating Lithium Niobate as the substrate and aluminum electrodes as the IDT, we modeled the A-SAW devices using Comsol Multiphysics. We used 8 pairs of annular electrodes with thickness of 1 μm with three different design's wavelength of 100 μm, 150 μm and 200 μm, respectively. To minimize the computational time in determining the optimum frequency i.e. resonant frequency of the device, only one pair of electrode for each design is simulated under eigenfrequency analysis in 2D piezoelectric (pzd) module. To understand the Rayleigh waves behavior, simulation of the whole device structure was done under frequency domain analysis in 2D-axisymmetric piezoelectric module. From the simulation results, it can be observed that SAW displacement profiles, electric potential field and operating frequency are significantly influenced by the wavelength. The formation of focused acoustic waves at the center of A-SAW device suits them in biosensing and microfluidic actuation applications that require detection or manipulation of localized variations.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131715045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-10-13DOI: 10.1109/SMELEC.2014.6920848
Abu Hanifah Muhamad Ali, M. Ani, M. A. Mohamed
Carbon nanotubes (CNTs) are such promising material in future microelectronic devices due to their great property in conductivity, mechanical strength and light weight. Field effect transistor (FET) has already come to its most maximum efficiency because of their reduced size leads to decrease in their capability in conducting electric. It is interested to embed ballistic electron transfer capability of CNTs on FET. In this study, direct growth method of CNTs was employed to attach it on FET electrodes with various terminal gaps. The results show that CNTFET has successfully fabricated, with averaged saturation currents always lowest at the channel size of 15μm. While their highest measured threshold voltage value is 4.291 V at 15 μm gap. This phenomenon is attributed to the change of CNTs' chirality, which apparently changes the metallic type of CNTs to the semiconducting CNTs.
{"title":"Channel length effect on the saturation current and the threshold voltages of CNTFET","authors":"Abu Hanifah Muhamad Ali, M. Ani, M. A. Mohamed","doi":"10.1109/SMELEC.2014.6920848","DOIUrl":"https://doi.org/10.1109/SMELEC.2014.6920848","url":null,"abstract":"Carbon nanotubes (CNTs) are such promising material in future microelectronic devices due to their great property in conductivity, mechanical strength and light weight. Field effect transistor (FET) has already come to its most maximum efficiency because of their reduced size leads to decrease in their capability in conducting electric. It is interested to embed ballistic electron transfer capability of CNTs on FET. In this study, direct growth method of CNTs was employed to attach it on FET electrodes with various terminal gaps. The results show that CNTFET has successfully fabricated, with averaged saturation currents always lowest at the channel size of 15μm. While their highest measured threshold voltage value is 4.291 V at 15 μm gap. This phenomenon is attributed to the change of CNTs' chirality, which apparently changes the metallic type of CNTs to the semiconducting CNTs.","PeriodicalId":268203,"journal":{"name":"2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131123193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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