Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016694
V. H. Reddy, Soumya Kumari, V. Muralidharan, Karan Gigoo, B. Thakare
The ease with which food is being delivered at our doorsteps has lead to an outbreak of a major chronic disease known as obesity. As the necessity of the food arose among people, the apprehension related to their diet also simultaneously increased. In this paper we propose a calorie measurement system whereby the user is made to upload the image of food item and as a result, number of calories present in the uploaded food image will be predicted. It is a multi-task system which also displays the weekly statistics on how much calorie is consumed by the user and how more/less calories must be consumed to avoid obesity related diseases such as heart attack, cancer etc. We built a dataset of food images collected from existing datasets to detect complex images consisting of 20 classes and each class containing 500 images each. We have curated our own Convolutional Neural Network architecture of 6 layers to extract the features and classify the images. Our experimental results on food recognition showed 78.7% testing accuracy with 93.29% training accuracy.
{"title":"Food Recognition and Calorie Measurement using Image Processing and Convolutional Neural Network","authors":"V. H. Reddy, Soumya Kumari, V. Muralidharan, Karan Gigoo, B. Thakare","doi":"10.1109/RTEICT46194.2019.9016694","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016694","url":null,"abstract":"The ease with which food is being delivered at our doorsteps has lead to an outbreak of a major chronic disease known as obesity. As the necessity of the food arose among people, the apprehension related to their diet also simultaneously increased. In this paper we propose a calorie measurement system whereby the user is made to upload the image of food item and as a result, number of calories present in the uploaded food image will be predicted. It is a multi-task system which also displays the weekly statistics on how much calorie is consumed by the user and how more/less calories must be consumed to avoid obesity related diseases such as heart attack, cancer etc. We built a dataset of food images collected from existing datasets to detect complex images consisting of 20 classes and each class containing 500 images each. We have curated our own Convolutional Neural Network architecture of 6 layers to extract the features and classify the images. Our experimental results on food recognition showed 78.7% testing accuracy with 93.29% training accuracy.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126302581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016837
Shamshad Alam, A. Raman, B. Raj, Naveen Kumar
In this paper, gate all around (GAA) tunnel field effect transistor (TFET) of the p-type channel is introduced. GAA has better gate control over the channel thereby it provides high ION/IOFF ratio. Since there is horizontal tunneling in conventional GAATFET when we introduce overlapping of the source and drain inside the channel the current abruptly increases and hence ION/IOFF. Sub-threshold slop is below 20 mv/decade in case of drain overlapped GAA. In source overlapped tunneling takes place in two directions while in conventional GAATFET tunneling was at source-channel interface only. Also, we have compared the ON current and OFF current with a variation of the drain current of non-overlapped, source overlapped and Drain overlapped of GAATFET, and we got the better result of drain overlapped GAATFET. In Drain overlapped GAATFET the subthreshold slope is lowest than other two structure so it provides an abrupt increase in ION.
{"title":"Design and Analysis of Gate Underlapped/Overlapped Surround Gate Nanowire TFET for Analog Performance","authors":"Shamshad Alam, A. Raman, B. Raj, Naveen Kumar","doi":"10.1109/RTEICT46194.2019.9016837","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016837","url":null,"abstract":"In this paper, gate all around (GAA) tunnel field effect transistor (TFET) of the p-type channel is introduced. GAA has better gate control over the channel thereby it provides high ION/IOFF ratio. Since there is horizontal tunneling in conventional GAATFET when we introduce overlapping of the source and drain inside the channel the current abruptly increases and hence ION/IOFF. Sub-threshold slop is below 20 mv/decade in case of drain overlapped GAA. In source overlapped tunneling takes place in two directions while in conventional GAATFET tunneling was at source-channel interface only. Also, we have compared the ON current and OFF current with a variation of the drain current of non-overlapped, source overlapped and Drain overlapped of GAATFET, and we got the better result of drain overlapped GAATFET. In Drain overlapped GAATFET the subthreshold slope is lowest than other two structure so it provides an abrupt increase in ION.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"52 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126373288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016724
S. Gupta, G. L. Pahuja
Reliability of multiprocessing systems greatly depends upon performance of Interconnection Network (IN) employed in it. Multistage Interconnection Networks (MIN) provide cost effective communication between multiple processors and memory modules, connected in parallel. Hence to improve the performance of multiprocessing systems, reliability and fault tolerance enhancement of MIN is of paramount importance. Some of the major papers on gamma networks have been reviewed in this paper. It has been found that these networks still lack in achieving fault tolerance at input and output node, cost is high, regularity of the network has been compromised etc. In this paper a new framework of Gamma Network has been proposed, which is considerably more reliable and fault tolerant. This has been named as Modified Gamma Network (MGN). MGN demonstrates improved reliability as compared to existing MGN topologies. It has been shown that the proposed topology possesses less number of stages as compared to GIN. Additionally, it possesses more number of parallel paths with at least two totally disjoint paths between each Source Destination (S-D) node pair, hence increased reliability and fault tolerance has been achieved as compared to GIN and its variants. The proposed MGN possesses less cost with minimum latency for a packet to be transmitted from a source to required destination as it has to pass through minimum number of nodes. In this paper ST-Reliability (Source-Terminal Reliability) of proposed network has been evaluated and the results achieved are compared with most of the existing Gamma Networks in literature. MGN demonstrates 23 % improved reliability and reduction in cost with fault tolerance feature.
{"title":"Reliability Evaluation of Modified Gamma Network with Reduced number of Stages","authors":"S. Gupta, G. L. Pahuja","doi":"10.1109/RTEICT46194.2019.9016724","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016724","url":null,"abstract":"Reliability of multiprocessing systems greatly depends upon performance of Interconnection Network (IN) employed in it. Multistage Interconnection Networks (MIN) provide cost effective communication between multiple processors and memory modules, connected in parallel. Hence to improve the performance of multiprocessing systems, reliability and fault tolerance enhancement of MIN is of paramount importance. Some of the major papers on gamma networks have been reviewed in this paper. It has been found that these networks still lack in achieving fault tolerance at input and output node, cost is high, regularity of the network has been compromised etc. In this paper a new framework of Gamma Network has been proposed, which is considerably more reliable and fault tolerant. This has been named as Modified Gamma Network (MGN). MGN demonstrates improved reliability as compared to existing MGN topologies. It has been shown that the proposed topology possesses less number of stages as compared to GIN. Additionally, it possesses more number of parallel paths with at least two totally disjoint paths between each Source Destination (S-D) node pair, hence increased reliability and fault tolerance has been achieved as compared to GIN and its variants. The proposed MGN possesses less cost with minimum latency for a packet to be transmitted from a source to required destination as it has to pass through minimum number of nodes. In this paper ST-Reliability (Source-Terminal Reliability) of proposed network has been evaluated and the results achieved are compared with most of the existing Gamma Networks in literature. MGN demonstrates 23 % improved reliability and reduction in cost with fault tolerance feature.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126817689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016706
D. Uday, G. Mamatha
With the growth of machine data, logging is progressively critical. Logging helps in investigating and diagnosing the issues for the execution of ideal applications. The logs are not only used for discovering issues but also for searching the required data. The ELK stack abbreviated as Elasticsearch, Logstash, and Kibana is mainly centered around the logs. As the majority of logs are centered at one spot so that it can be able to see the procedure stream and query the questions against logs from all kind of applications from one spot. ELK underpins many log the executives and examination use cases that can get experiences from information. This finds what the information is defining all about and what needs to be done for the accomplishment of the business needs. In the current scenario the identification of the defect in the health system and system location is much difficult, So we propose a method to investigation on the log details of the health systems can give the assistance on identifying the defect on the existing safe guards using ELK stack, which in turn gives the assurance to the frameworks, by this it can have a learning from the data that was separated from the information so it can be able to assist us with keeping track of the defects in the system and the health of the system needs to be prioritized. The Log data is filtered based on system priority and country, because to identify the system state and location of the system, and this is visualized on the Kibana dashboard. This helps service engineers to identify the defect and location of system with short period of time.
{"title":"An Analysis of Health System Log Files using ELK Stack","authors":"D. Uday, G. Mamatha","doi":"10.1109/RTEICT46194.2019.9016706","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016706","url":null,"abstract":"With the growth of machine data, logging is progressively critical. Logging helps in investigating and diagnosing the issues for the execution of ideal applications. The logs are not only used for discovering issues but also for searching the required data. The ELK stack abbreviated as Elasticsearch, Logstash, and Kibana is mainly centered around the logs. As the majority of logs are centered at one spot so that it can be able to see the procedure stream and query the questions against logs from all kind of applications from one spot. ELK underpins many log the executives and examination use cases that can get experiences from information. This finds what the information is defining all about and what needs to be done for the accomplishment of the business needs. In the current scenario the identification of the defect in the health system and system location is much difficult, So we propose a method to investigation on the log details of the health systems can give the assistance on identifying the defect on the existing safe guards using ELK stack, which in turn gives the assurance to the frameworks, by this it can have a learning from the data that was separated from the information so it can be able to assist us with keeping track of the defects in the system and the health of the system needs to be prioritized. The Log data is filtered based on system priority and country, because to identify the system state and location of the system, and this is visualized on the Kibana dashboard. This helps service engineers to identify the defect and location of system with short period of time.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130660181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016966
P. Jasitha, M. Dileep, M. Divya
Plants maintain and protect life on earth by perpetuating various seasons and supplying air, food, shade, and shelter. Identification and classification of plants are inevitable for botanists, ayurvedic physicians, ayurvedic medicine manufacturers, and researchers. In this paper, we propose a fine- tuned GoogLeNet CNN model for classification of plants using leaf venation. GoogLeNet and VGG-16 CNN models are trained and tested with Dleaf, Flavia and Leaf1 datasets using CNN and Sopport Vector Machine (SVM) classifier. Fine-tuned GoogLeNet outperforms fine-tuned VGG-16 and Dleaf deep CNN model with a five-fold cross-validation accuracy of 99.2% on Leaf1 dataset using SVM classifier.
{"title":"Venation Based Plant Leaves Classification Using GoogLeNet and VGG","authors":"P. Jasitha, M. Dileep, M. Divya","doi":"10.1109/RTEICT46194.2019.9016966","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016966","url":null,"abstract":"Plants maintain and protect life on earth by perpetuating various seasons and supplying air, food, shade, and shelter. Identification and classification of plants are inevitable for botanists, ayurvedic physicians, ayurvedic medicine manufacturers, and researchers. In this paper, we propose a fine- tuned GoogLeNet CNN model for classification of plants using leaf venation. GoogLeNet and VGG-16 CNN models are trained and tested with Dleaf, Flavia and Leaf1 datasets using CNN and Sopport Vector Machine (SVM) classifier. Fine-tuned GoogLeNet outperforms fine-tuned VGG-16 and Dleaf deep CNN model with a five-fold cross-validation accuracy of 99.2% on Leaf1 dataset using SVM classifier.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133607642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016869
Umesharaddy Radder, B. Sujatha
The paper describes a method of implementing a QPSK system in FPGA, the system being contrived in a manner where it provides an improved performance in an AWGN environment. To emulate the AWGN environment, we decided to use a method that largely resembles the Box-Muller method that generates two independent random variables with a normal distribution. The generated number sequences representing noise are then separately added to the I-channel and the Q-channel. Raised Cosine Filtering is used for the smoothening of signals. To illustrate the improvement in performance that FEC codes could provide, we use (2, 1, 7) convolutional encoding after pulse shaping, then introduce the noise, and Viterbi decoding is used to correct the errors. The entire system has been simulated using ModelSim PE Student Edition 10.4a and implemented using Xilinx XC6SLX45 Spartan 6 FPGA with the aid of ChipScope Pro software.
本文描述了一种在FPGA中实现QPSK系统的方法，该系统在AWGN环境中提供了改进的性能。为了模拟AWGN环境，我们决定使用一种与Box-Muller方法非常相似的方法，该方法生成两个具有正态分布的独立随机变量。然后将生成的表示噪声的数字序列分别添加到i通道和q通道。提高余弦滤波用于信号的平滑。为了说明FEC码可以提供的性能改进，我们在脉冲整形后使用(2,1,7)卷积编码，然后引入噪声，并使用维特比解码来纠正误差。利用ModelSim PE Student Edition 10.4a对整个系统进行了仿真，并利用Xilinx XC6SLX45 Spartan 6 FPGA和ChipScope Pro软件实现了整个系统。
{"title":"Performance Improvement of QPSK MODEM in AWGN Channel Implemented in FPGA","authors":"Umesharaddy Radder, B. Sujatha","doi":"10.1109/RTEICT46194.2019.9016869","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016869","url":null,"abstract":"The paper describes a method of implementing a QPSK system in FPGA, the system being contrived in a manner where it provides an improved performance in an AWGN environment. To emulate the AWGN environment, we decided to use a method that largely resembles the Box-Muller method that generates two independent random variables with a normal distribution. The generated number sequences representing noise are then separately added to the I-channel and the Q-channel. Raised Cosine Filtering is used for the smoothening of signals. To illustrate the improvement in performance that FEC codes could provide, we use (2, 1, 7) convolutional encoding after pulse shaping, then introduce the noise, and Viterbi decoding is used to correct the errors. The entire system has been simulated using ModelSim PE Student Edition 10.4a and implemented using Xilinx XC6SLX45 Spartan 6 FPGA with the aid of ChipScope Pro software.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133105263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016857
N. Rai, Namita Palecha, Mahesh Nagarai
Semiconductor industries perform testing to ensure good performance of the device under different operating conditions. The time consumed in testing the device by traditional testing methods using multimeter is considerably high and the results are subject to manual errors. Thus, an automatic test equipment (ATE), which is a compact complex circuitry involving current/voltage forcing and measuring units, is used to reduce the test time and obtain accurate results. The paper presents a test solution development for a cable controller generation 3 (CCG3) wafer which is a type-C universal serial bus (USB). The first step is development of the test requirements document (TRD). Next, a TRD parser is developed which is a java-based tool that automatically generates the test program by using the TRD as an input. Finally, the generated test program is validated on an Advantest V93000 tester based on the Smartest8 (SMT8) platform. The TRD parser automatically generates the complete test program in 3.168s and 100% test coverage is achieved on the V93000 tester for the continuity tests. The paper thus covers the entire flow of testing a device under test (DUT) using an ATE at wafer level.
{"title":"A brief overview of Test Solution Development for Semiconductor Testing","authors":"N. Rai, Namita Palecha, Mahesh Nagarai","doi":"10.1109/RTEICT46194.2019.9016857","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016857","url":null,"abstract":"Semiconductor industries perform testing to ensure good performance of the device under different operating conditions. The time consumed in testing the device by traditional testing methods using multimeter is considerably high and the results are subject to manual errors. Thus, an automatic test equipment (ATE), which is a compact complex circuitry involving current/voltage forcing and measuring units, is used to reduce the test time and obtain accurate results. The paper presents a test solution development for a cable controller generation 3 (CCG3) wafer which is a type-C universal serial bus (USB). The first step is development of the test requirements document (TRD). Next, a TRD parser is developed which is a java-based tool that automatically generates the test program by using the TRD as an input. Finally, the generated test program is validated on an Advantest V93000 tester based on the Smartest8 (SMT8) platform. The TRD parser automatically generates the complete test program in 3.168s and 100% test coverage is achieved on the V93000 tester for the continuity tests. The paper thus covers the entire flow of testing a device under test (DUT) using an ATE at wafer level.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130976415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/rteict46194.2019.9016773
Copyright Information
{"title":"[Copyright notice]","authors":"","doi":"10.1109/rteict46194.2019.9016773","DOIUrl":"https://doi.org/10.1109/rteict46194.2019.9016773","url":null,"abstract":"Copyright Information","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125684836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016951
R. Divva, V. Prasad
Global energy challenges, increasing environmental concern, increasing power demand have led to the wide adoption of renewable energy sources like the photovoltaic systems. Standalone operation is a difficult task due to its intermittent nature. Here comes the use of an energy storage device which acts as an energy buffer. Among the energy storage devices, batteries are often preferred. Stress on battery increases when sudden fluctuations in the load profile appears. It leads to the deep discharge of batteries which damages as well as shortens its lifetime. In order to remove the stress from the batteries, supercapacitors (SC) are incorporated to form a hybrid energy storage system. Supercapacitors respond quickly to the instantaneous power demand. Hysteresis control and fuzzy logic energy management strategy have been introduced. The overall system is developed in MATLAB/Simulink environment. Simulation results prove the validity of the proposed strategy.
{"title":"Fuzzy Logic Management of Hybrid Energy Storage System","authors":"R. Divva, V. Prasad","doi":"10.1109/RTEICT46194.2019.9016951","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016951","url":null,"abstract":"Global energy challenges, increasing environmental concern, increasing power demand have led to the wide adoption of renewable energy sources like the photovoltaic systems. Standalone operation is a difficult task due to its intermittent nature. Here comes the use of an energy storage device which acts as an energy buffer. Among the energy storage devices, batteries are often preferred. Stress on battery increases when sudden fluctuations in the load profile appears. It leads to the deep discharge of batteries which damages as well as shortens its lifetime. In order to remove the stress from the batteries, supercapacitors (SC) are incorporated to form a hybrid energy storage system. Supercapacitors respond quickly to the instantaneous power demand. Hysteresis control and fuzzy logic energy management strategy have been introduced. The overall system is developed in MATLAB/Simulink environment. Simulation results prove the validity of the proposed strategy.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131081936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016937
S. Vali, V. Ganesh
This paper presents the modeling of LC resonant circuit that is popularly used in quasiresonant DC-DC converters using bond graphs. A model with bond graphs is developed for the LC resonant circuit and is simulated in MATLAB/SIMULINK. With the help of simulated waveforms, it explains the selection of switching instants for having zero power loss such as zero voltage and zero current instants for better conversion efficiency of power converters. It also explains the various advantages of bond graphs especially in quasiresonant power converters.
{"title":"Bond Graph Modelling and Simulation of LC Resonant Circuit for Quasiresonant DC-DC Power Converters","authors":"S. Vali, V. Ganesh","doi":"10.1109/RTEICT46194.2019.9016937","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016937","url":null,"abstract":"This paper presents the modeling of LC resonant circuit that is popularly used in quasiresonant DC-DC converters using bond graphs. A model with bond graphs is developed for the LC resonant circuit and is simulated in MATLAB/SIMULINK. With the help of simulated waveforms, it explains the selection of switching instants for having zero power loss such as zero voltage and zero current instants for better conversion efficiency of power converters. It also explains the various advantages of bond graphs especially in quasiresonant power converters.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115386062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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