Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016894
Suchismita Batabyal, A. A. Bazil Rai
Hardware security is of utmost importance nowadays, with the increased number of threats like modelling attacks, reverse engineering and extracting secret information from the IC's. A physical unclonable function (PUF) is a promising solution to many security related problems and can be used to produce devices or IC's that are unique and resistant to cloning attempts. A PUF is like a fingerprint for a particular physical object, it is based on many manufacturing mismatches that occur during IC fabrication or the propagation delays that are present in the wires and interconnects. Various kinds of PUF designs are possible like ring oscillator, SRAM and arbiter PUF's etc. A Ring oscillator based PUF is designed based on the delays present in the wires that leads to different frequency of oscillation and can form the basis for key generation. They are also easily implemented in field programmable gate array (FPGA).In this paper we propose a ring oscillator based design with enhanced challenge response pair (CRP) with improved reliability. Our design has more number of challenge response pair since all the possible frequency comparisons of the Ro are done. Also it provides better reliability because our approach relies on relative values and not absolute value, it incorporates the difference between the highest frequency in the present comparison and the maximum of all the measured frequencies, under varying environmental conditions even if the absolute value changes, the relative value will never change.
{"title":"Design of A Ring Oscillator Based PUF with Enhanced Challenge Response pair and Improved Reliability","authors":"Suchismita Batabyal, A. A. Bazil Rai","doi":"10.1109/RTEICT46194.2019.9016894","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016894","url":null,"abstract":"Hardware security is of utmost importance nowadays, with the increased number of threats like modelling attacks, reverse engineering and extracting secret information from the IC's. A physical unclonable function (PUF) is a promising solution to many security related problems and can be used to produce devices or IC's that are unique and resistant to cloning attempts. A PUF is like a fingerprint for a particular physical object, it is based on many manufacturing mismatches that occur during IC fabrication or the propagation delays that are present in the wires and interconnects. Various kinds of PUF designs are possible like ring oscillator, SRAM and arbiter PUF's etc. A Ring oscillator based PUF is designed based on the delays present in the wires that leads to different frequency of oscillation and can form the basis for key generation. They are also easily implemented in field programmable gate array (FPGA).In this paper we propose a ring oscillator based design with enhanced challenge response pair (CRP) with improved reliability. Our design has more number of challenge response pair since all the possible frequency comparisons of the Ro are done. Also it provides better reliability because our approach relies on relative values and not absolute value, it incorporates the difference between the highest frequency in the present comparison and the maximum of all the measured frequencies, under varying environmental conditions even if the absolute value changes, the relative value will never change.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134074796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016734
S. Patil, M. Rane, S. Bindu
A measuring system which can measure high voltage impulses is been implemented using resistive and capacitive divider network. The simulation of this resistive divider is been done in MATLAB Software with the ten stage Marx circuit and results are calculated which are then matched with both the capacitive divider network and the resistive divider network. The voltage values of resistive divider and capacitive divider are calculated and compared. It is seen that the resistive divider network has excellent response characteristics as compared to capacitive divider network. The experimental result shows that it can measure the voltage quantities up to 5000V, which has pulse width of $5mu$ -sec sheet.
{"title":"Issues with High Volatage Measurement and its Mitigation","authors":"S. Patil, M. Rane, S. Bindu","doi":"10.1109/RTEICT46194.2019.9016734","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016734","url":null,"abstract":"A measuring system which can measure high voltage impulses is been implemented using resistive and capacitive divider network. The simulation of this resistive divider is been done in MATLAB Software with the ten stage Marx circuit and results are calculated which are then matched with both the capacitive divider network and the resistive divider network. The voltage values of resistive divider and capacitive divider are calculated and compared. It is seen that the resistive divider network has excellent response characteristics as compared to capacitive divider network. The experimental result shows that it can measure the voltage quantities up to 5000V, which has pulse width of $5mu$ -sec sheet.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122197284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016808
Apoorva Raghunandan, RAVISH ARADHYA H V
A good VLSI Design is one with low area occupancy and high speed of operation. As per Moore's law the number of transistors on a chip, increase and so does the overall chip Area. Optimizing the parameters of Area and Delay is of high importance in VLSI Design. Performance analysis and comparison of Area occupancy and Delay has been performed for 4 adders - the Ripple Carry Adder (Adder 1), the Kogge Stone Adder (Adder 2), the Carry Skip Adder (Adder 3) and the Brent Kung Adder (Adder 4), each being a 16-bit adder. The Adders were designed using Verilog code and then simulated and synthesized using RTL Encounter tool. Netlists were generated using the nclaunch tool for the three technologies. The Area and Delay results have been obtained for three technologies namely 180nm, 90nm and 45nm. At 180m, the Ripple Carry Adder occupies the least area of 1118nm2and Kogge Stone Adder has the smallest Delay of 3.495ns. At 90nm, the Ripple Carry Adder occupies the smallest Area of 315nm2 and the Kogge Stone Adder has the smallest delay of 2.957ns. The Ripple Carry Adder has a delay of 3.875ns in [3]. The reduction of delay in the paper is 10.99%.. The Carry Skip Adder has a delay of 8.106ns in [3] and a reduction of 64.16% is obtained in this paper. The Kogge Stone Adder has a delay of 6.7ns in [3]. A delay reduction of 63.65% is obtained in this paper. In [3], The Brent Kung Adder has a delay of 8.094ns. A reduction of 71.14% is obtained Amongst the four adders it has been found that the Brent Kung occupies the least Area of 123nm2 at 45nm and also has the smallest delay of 2.336 ns.
{"title":"Area and Timing Analysis of Advanced Adders under changing Technologies","authors":"Apoorva Raghunandan, RAVISH ARADHYA H V","doi":"10.1109/RTEICT46194.2019.9016808","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016808","url":null,"abstract":"A good VLSI Design is one with low area occupancy and high speed of operation. As per Moore's law the number of transistors on a chip, increase and so does the overall chip Area. Optimizing the parameters of Area and Delay is of high importance in VLSI Design. Performance analysis and comparison of Area occupancy and Delay has been performed for 4 adders - the Ripple Carry Adder (Adder 1), the Kogge Stone Adder (Adder 2), the Carry Skip Adder (Adder 3) and the Brent Kung Adder (Adder 4), each being a 16-bit adder. The Adders were designed using Verilog code and then simulated and synthesized using RTL Encounter tool. Netlists were generated using the nclaunch tool for the three technologies. The Area and Delay results have been obtained for three technologies namely 180nm, 90nm and 45nm. At 180m, the Ripple Carry Adder occupies the least area of 1118nm2and Kogge Stone Adder has the smallest Delay of 3.495ns. At 90nm, the Ripple Carry Adder occupies the smallest Area of 315nm2 and the Kogge Stone Adder has the smallest delay of 2.957ns. The Ripple Carry Adder has a delay of 3.875ns in [3]. The reduction of delay in the paper is 10.99%.. The Carry Skip Adder has a delay of 8.106ns in [3] and a reduction of 64.16% is obtained in this paper. The Kogge Stone Adder has a delay of 6.7ns in [3]. A delay reduction of 63.65% is obtained in this paper. In [3], The Brent Kung Adder has a delay of 8.094ns. A reduction of 71.14% is obtained Amongst the four adders it has been found that the Brent Kung occupies the least Area of 123nm2 at 45nm and also has the smallest delay of 2.336 ns.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131727309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016776
Pragya Joshi, S. K. Jain
In this paper harmonic source identification has been done using active power direction method with the study of distortion caused by loads at the system nodes. The active power direction method is being continuously used until present date with required modifications and integration with other techniques in order to improve its application for the purpose of harmonic source detection. The effect of disturbing loads at the nodes renders significant information regarding the type of load connected to it. A comparative study of distorting and non-distorting portion of load parameters along with the power direction analysis is used as an effective tool to identify harmonic sources present in the system, better performance can be witnessed in this work on various test cases where power direction method fails. The effectiveness of the proposed technique has been tested on a modified IEEE 5 bus system and IEEE 9 bus system.
{"title":"Harmonic Source Identification Using Modified Power Direction Method","authors":"Pragya Joshi, S. K. Jain","doi":"10.1109/RTEICT46194.2019.9016776","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016776","url":null,"abstract":"In this paper harmonic source identification has been done using active power direction method with the study of distortion caused by loads at the system nodes. The active power direction method is being continuously used until present date with required modifications and integration with other techniques in order to improve its application for the purpose of harmonic source detection. The effect of disturbing loads at the nodes renders significant information regarding the type of load connected to it. A comparative study of distorting and non-distorting portion of load parameters along with the power direction analysis is used as an effective tool to identify harmonic sources present in the system, better performance can be witnessed in this work on various test cases where power direction method fails. The effectiveness of the proposed technique has been tested on a modified IEEE 5 bus system and IEEE 9 bus system.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"336 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132419240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016731
G. Vijay, M. N. Ramanarayan, A. Chavan
The number of road accidents is increasing every year due to increases in vehicle and driver negligence, and it leads to a serious issue in front of modern society. Unintended lane departure and rear end collisions are some of the main reason behind road accidents in the freeway. However, it is now possible to prevent this problem to some extent, by using Advance driver assistant system (ADAS). This paper presents a Design and integration of lane departure warning, adaptive headlight and wiper system which works on different road and illumination conditions. The system uses a raspberry pi for video processing and arduino Mega is used as processing unit for AHAWS. The algorithm of LDWS takes video input frame by frame, filters the frame detects edges using canny edge detection, the lane detection decision is done by Hough transform using OpenCV python software. Based on the position of the car inside the detected lanes the warning is raised. The AHAWS algorithm takes three inputs road curvature which is given by LDWS in case of integrated system, surrounding light intensity and rain intensity based on the input the headlight will turn along with curve, the headlight intensity is adjusted according to surrounding light and wiper frequency is set according to rain intensity. The experimental results States that the AHWAS responds quickly to change in input, the average lane detection rate and the departure warning rate are 99.8% and 92.1%, respectively. With a $720times 1280$ resolution, the average processing speed is 22.2 fp/s.
{"title":"Design and Integration of Lane Departure Warning, Adaptive Headlight and Wiper system for Automobile Safety","authors":"G. Vijay, M. N. Ramanarayan, A. Chavan","doi":"10.1109/RTEICT46194.2019.9016731","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016731","url":null,"abstract":"The number of road accidents is increasing every year due to increases in vehicle and driver negligence, and it leads to a serious issue in front of modern society. Unintended lane departure and rear end collisions are some of the main reason behind road accidents in the freeway. However, it is now possible to prevent this problem to some extent, by using Advance driver assistant system (ADAS). This paper presents a Design and integration of lane departure warning, adaptive headlight and wiper system which works on different road and illumination conditions. The system uses a raspberry pi for video processing and arduino Mega is used as processing unit for AHAWS. The algorithm of LDWS takes video input frame by frame, filters the frame detects edges using canny edge detection, the lane detection decision is done by Hough transform using OpenCV python software. Based on the position of the car inside the detected lanes the warning is raised. The AHAWS algorithm takes three inputs road curvature which is given by LDWS in case of integrated system, surrounding light intensity and rain intensity based on the input the headlight will turn along with curve, the headlight intensity is adjusted according to surrounding light and wiper frequency is set according to rain intensity. The experimental results States that the AHWAS responds quickly to change in input, the average lane detection rate and the departure warning rate are 99.8% and 92.1%, respectively. With a $720times 1280$ resolution, the average processing speed is 22.2 fp/s.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":" 105","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016768
Nandita Bangera, K. N.
Analytics plays vital role in Data Science. It involves finding trends and patterns from the huge repository of data. Scanning huge amount of data consumes lot of time, which can be reduced by sampling. In this paper we have demonstrated effectiveness of Progressive sampling wherein the sample size is gradually increased till it reaches a desired accuracy. By applying an algorithm based on Rademacher average to mine frequent datasets using Progressive sampling, we have shown that the runtime and the sampling time is considerably reduced as compared with static sampling.
{"title":"A Progressive Sampling based Approach to Reduce Sampling Time","authors":"Nandita Bangera, K. N.","doi":"10.1109/RTEICT46194.2019.9016768","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016768","url":null,"abstract":"Analytics plays vital role in Data Science. It involves finding trends and patterns from the huge repository of data. Scanning huge amount of data consumes lot of time, which can be reduced by sampling. In this paper we have demonstrated effectiveness of Progressive sampling wherein the sample size is gradually increased till it reaches a desired accuracy. By applying an algorithm based on Rademacher average to mine frequent datasets using Progressive sampling, we have shown that the runtime and the sampling time is considerably reduced as compared with static sampling.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114768213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016781
Shridhar Patil, P. Deepika
Bayer Colour Filter Array is a matrix of photosensors covered with red, green, and blue colour filters. This setup is advantageous in smartphones as only a third of the required data is captured by the sensor in the camera. The rest of the components based on the colour format can be interpolated using a suitable algorithm to arrive at a full-colour image. Increasing the resolution of the camera sensor will translate to increased bandwidth in the image signal processing pipeline, and consequently power consumption. In addition to that, the bit depth is also on the rise to enhance the colours. These two factors will create a huge impact on the data to be handled in the pertinent processor. Hence, compression of the Bayer data is of immense significance. The existing standard compression schemes can be adapted to suit the Bayer format. Also, several compression schemes, specific to Bayer format have been proposed. Two compression methods, viz. JPEG-LS and Hierarchical Prediction based compression have been tested and the corresponding results are presented in this paper. The former is a standard while the latter has been proposed keeping the Bayer format in mind. Modelling of the algorithms shows that JPEG-LS is best suited in the use cases where lossless compression is desirable, and Hierarchical Prediction based compression is the better option where some amount of loss is acceptable.
{"title":"Compression of Bayer Colour Filter Array Images","authors":"Shridhar Patil, P. Deepika","doi":"10.1109/RTEICT46194.2019.9016781","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016781","url":null,"abstract":"Bayer Colour Filter Array is a matrix of photosensors covered with red, green, and blue colour filters. This setup is advantageous in smartphones as only a third of the required data is captured by the sensor in the camera. The rest of the components based on the colour format can be interpolated using a suitable algorithm to arrive at a full-colour image. Increasing the resolution of the camera sensor will translate to increased bandwidth in the image signal processing pipeline, and consequently power consumption. In addition to that, the bit depth is also on the rise to enhance the colours. These two factors will create a huge impact on the data to be handled in the pertinent processor. Hence, compression of the Bayer data is of immense significance. The existing standard compression schemes can be adapted to suit the Bayer format. Also, several compression schemes, specific to Bayer format have been proposed. Two compression methods, viz. JPEG-LS and Hierarchical Prediction based compression have been tested and the corresponding results are presented in this paper. The former is a standard while the latter has been proposed keeping the Bayer format in mind. Modelling of the algorithms shows that JPEG-LS is best suited in the use cases where lossless compression is desirable, and Hierarchical Prediction based compression is the better option where some amount of loss is acceptable.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123664450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016771
P. Naveen, Praveen Kumar N, K. Sriganesh, T. Rajesh, K. Sushmitha
One of the most common faults experienced by the permanent magnet synchronous motor (PMSM) is stator interturn fault which account for 35-40% of the machine failure. This paper focuses on the stator inter-turn fault analysis in the stator winding of Permanent Magnet Synchronous Motor (PMSM) using Finite Element Method. The analysis is carried out for 12.5% and 25% inter-turn short in stator winding of PMSM. The analytical parameters of the motor which includes torque, winding current, induced voltage, speed and electromagnetic parameters like flux density, flux lines and radial flux density were obtained for the faulty machine and compared with the healthy machine. The simulation is done using the ANSYS Maxwell finite element analysis tool.
{"title":"Stator Fault Analysis of Permanent Magnet Synchronous Motor using Finite Element Method","authors":"P. Naveen, Praveen Kumar N, K. Sriganesh, T. Rajesh, K. Sushmitha","doi":"10.1109/RTEICT46194.2019.9016771","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016771","url":null,"abstract":"One of the most common faults experienced by the permanent magnet synchronous motor (PMSM) is stator interturn fault which account for 35-40% of the machine failure. This paper focuses on the stator inter-turn fault analysis in the stator winding of Permanent Magnet Synchronous Motor (PMSM) using Finite Element Method. The analysis is carried out for 12.5% and 25% inter-turn short in stator winding of PMSM. The analytical parameters of the motor which includes torque, winding current, induced voltage, speed and electromagnetic parameters like flux density, flux lines and radial flux density were obtained for the faulty machine and compared with the healthy machine. The simulation is done using the ANSYS Maxwell finite element analysis tool.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122734686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016906
N. Ashwini, N. Swathi, L. Prem, B. Nithin, A. N. Prajwal, G. A. S. Raghavendra
The present technology in the defence for the surveillance system is not effective. The different ways in which intruders invading to an unauthorized territory has increased over a year and thus causing a massive destruction and other violence which in turn results in life losses and, disturbs the peace of a country. There is no much advanced technology which can control the trespassers from invading, navigating on any terrain condition and on water with full time surveillance. In this paper, we have proposed a counter-foe night vision eyed robot, for monitoring and recognizing the foe activities along with authorized and unauthorized persons discernation within the premises using advanced Haar transformation and face recognition system with weapon detection capability. If robot recognizes any unusual activities, will automatically captures the scene and send the processed image to the base station. It can also transmit live video if necessary, at certain condition. Unlike recent technologies robot has also got the capability for detecting the invisible foe activities that takes place beneath the terra-firm with terrain switching mechanism.
{"title":"Integrated Secure Columnist Hexpod All- Terrain Full Time Counter-Foe Master","authors":"N. Ashwini, N. Swathi, L. Prem, B. Nithin, A. N. Prajwal, G. A. S. Raghavendra","doi":"10.1109/RTEICT46194.2019.9016906","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016906","url":null,"abstract":"The present technology in the defence for the surveillance system is not effective. The different ways in which intruders invading to an unauthorized territory has increased over a year and thus causing a massive destruction and other violence which in turn results in life losses and, disturbs the peace of a country. There is no much advanced technology which can control the trespassers from invading, navigating on any terrain condition and on water with full time surveillance. In this paper, we have proposed a counter-foe night vision eyed robot, for monitoring and recognizing the foe activities along with authorized and unauthorized persons discernation within the premises using advanced Haar transformation and face recognition system with weapon detection capability. If robot recognizes any unusual activities, will automatically captures the scene and send the processed image to the base station. It can also transmit live video if necessary, at certain condition. Unlike recent technologies robot has also got the capability for detecting the invisible foe activities that takes place beneath the terra-firm with terrain switching mechanism.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"48 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128229769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016739
Daliya Velandi Thiruvoth, A. Raj, B. P. Kumar, V. S. Kumar, R. Gupta
A dual-band reflectarray microstrip patch antenna element is presented in this paper. The concept of polarization diversity is effectively utilized in the design with the cross-polarization level obtained well below -25dB in both the principal planes. This supports the implementation of dual-band operation from the same element. The two orthogonal modes of a rectangular patch: TM01, and TM10, are exploited for the dual-band operation. The inherent narrow bandwidth of the element fulfils the requirement of the present work at both the downlink and uplink frequencies of 11.4 GHz and 13.2 GHz respectively. The bandwidth is measured to be 2% to 3%, which effectively keeps the design simple. Also, a good port isolation of 27 dB at downlink band and 20 dB at uplink band are observed. A measured return loss of 17.7 dB at 11.4 GHz and 26 dB at 13.2 GHz are obtained with an acceptable deviation of only 0.65% (75 MHz) at downlink frequency. Based on this element a configuration for dual-band reflectarray is also proposed.
{"title":"Dual-Band Shared-Aperture Reflectarray Antenna Element at Ku-Band for the TT&C Application of a Geostationary Satellite","authors":"Daliya Velandi Thiruvoth, A. Raj, B. P. Kumar, V. S. Kumar, R. Gupta","doi":"10.1109/RTEICT46194.2019.9016739","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016739","url":null,"abstract":"A dual-band reflectarray microstrip patch antenna element is presented in this paper. The concept of polarization diversity is effectively utilized in the design with the cross-polarization level obtained well below -25dB in both the principal planes. This supports the implementation of dual-band operation from the same element. The two orthogonal modes of a rectangular patch: TM01, and TM10, are exploited for the dual-band operation. The inherent narrow bandwidth of the element fulfils the requirement of the present work at both the downlink and uplink frequencies of 11.4 GHz and 13.2 GHz respectively. The bandwidth is measured to be 2% to 3%, which effectively keeps the design simple. Also, a good port isolation of 27 dB at downlink band and 20 dB at uplink band are observed. A measured return loss of 17.7 dB at 11.4 GHz and 26 dB at 13.2 GHz are obtained with an acceptable deviation of only 0.65% (75 MHz) at downlink frequency. Based on this element a configuration for dual-band reflectarray is also proposed.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130361395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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