Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016920
Lakshmi Prasad, A. Raj
This paper exercises fuzzy logic for the prediction of channel response to a two dimensional-wavelength hopping /time spreading optical code division multiple access (2D-WH/TS OCDMA) code in a passive optical network (PON). A fuzzy logic control (FLC) is employed for the reduction of bit error rate of 2D-WH/TS OCDMA PON at the receiver. This FLC predicts the environmental temperature variation effects that occur in the transmission links which impact the expected magnitude of the autocorrelation peak of 2D-WH/TS OCDMA code at the receiver. The FLC system, uses propagation distance and the temperature changes in channel which is estimated by sensors, as input variables, to predict the auto-correlation peak at the receiver. This information on the reduction of auto correlation requires to dynamically adjust the threshold level of threshold detector at the receiver. The design of the FLC demands a priory knowledge of the analytic response of the 2D-WH/TS OCDMA channels. The simulation of FLC was done by using membership functions in MATLAB using fuzzy libraries. The simulation results show that the effect of environmental temperature can be predicted with the accuracy of 92.1% from the analytic model available for channel response.
{"title":"Design of 2D-WH/TS OCDMA PON ONU Receiver with FLC Technique","authors":"Lakshmi Prasad, A. Raj","doi":"10.1109/RTEICT46194.2019.9016920","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016920","url":null,"abstract":"This paper exercises fuzzy logic for the prediction of channel response to a two dimensional-wavelength hopping /time spreading optical code division multiple access (2D-WH/TS OCDMA) code in a passive optical network (PON). A fuzzy logic control (FLC) is employed for the reduction of bit error rate of 2D-WH/TS OCDMA PON at the receiver. This FLC predicts the environmental temperature variation effects that occur in the transmission links which impact the expected magnitude of the autocorrelation peak of 2D-WH/TS OCDMA code at the receiver. The FLC system, uses propagation distance and the temperature changes in channel which is estimated by sensors, as input variables, to predict the auto-correlation peak at the receiver. This information on the reduction of auto correlation requires to dynamically adjust the threshold level of threshold detector at the receiver. The design of the FLC demands a priory knowledge of the analytic response of the 2D-WH/TS OCDMA channels. The simulation of FLC was done by using membership functions in MATLAB using fuzzy libraries. The simulation results show that the effect of environmental temperature can be predicted with the accuracy of 92.1% from the analytic model available for channel response.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130939405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016765
Sunil Kumar KN, R. Sathish, S. Vinayak, Tarkeshwor Parasad Pandit
Navigation in outdoor and indoor is certainly an challenging task for visually impaired, blind and deaf-mute people, indoor navigation itself is certainly becoming an harder task for blind, visually impaired people and dead-mute people. As far as observed for the non-visually impaired, it is even worse for the visually impaired. People with visual disabilities or blinds are often depending up on external assistance like trained dogs, humans, or special devices as support systems for making decisions. Hence blind people need an assistive device that will allow blind user to navigate freely and this requirement has become crucial. Here the interfacing of different sensors and actuators along with Braille keypad which is user friendly application to these peoples is done with ARM LPC-2148 and it helps in minimizing the problems faced by blind people by maximizing the use of technology. The walking stick used by the blind people has multiple sensors incorporated in it, with the help of which it is possible to enhance more features and technology to the walking stick. The main features are to detect the obstacle for collision avoidance, along with certain other sensors for pit whole detection, fire detection, and water detection. Panic switch is the emergency button that sends an SMS from the GSM module to the caretaker with the present particular location (GPS coordinates) of the blind, visually impaired and deaf mute person. The work goes for giving the safest route to blind persons, visually impaired person or deaf-mute person, by designing a more flexible assistance system and cost effective system that helps them in improving their navigating skills in outdoor and indoor application and also not to depend on none during walking in even unknown areas.
{"title":"Braille Assistance System for Visually Impaired, Blind & Deaf-Mute people in Indoor & Outdoor Application","authors":"Sunil Kumar KN, R. Sathish, S. Vinayak, Tarkeshwor Parasad Pandit","doi":"10.1109/RTEICT46194.2019.9016765","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016765","url":null,"abstract":"Navigation in outdoor and indoor is certainly an challenging task for visually impaired, blind and deaf-mute people, indoor navigation itself is certainly becoming an harder task for blind, visually impaired people and dead-mute people. As far as observed for the non-visually impaired, it is even worse for the visually impaired. People with visual disabilities or blinds are often depending up on external assistance like trained dogs, humans, or special devices as support systems for making decisions. Hence blind people need an assistive device that will allow blind user to navigate freely and this requirement has become crucial. Here the interfacing of different sensors and actuators along with Braille keypad which is user friendly application to these peoples is done with ARM LPC-2148 and it helps in minimizing the problems faced by blind people by maximizing the use of technology. The walking stick used by the blind people has multiple sensors incorporated in it, with the help of which it is possible to enhance more features and technology to the walking stick. The main features are to detect the obstacle for collision avoidance, along with certain other sensors for pit whole detection, fire detection, and water detection. Panic switch is the emergency button that sends an SMS from the GSM module to the caretaker with the present particular location (GPS coordinates) of the blind, visually impaired and deaf mute person. The work goes for giving the safest route to blind persons, visually impaired person or deaf-mute person, by designing a more flexible assistance system and cost effective system that helps them in improving their navigating skills in outdoor and indoor application and also not to depend on none during walking in even unknown areas.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127719889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016776
Pragya Joshi, S. K. Jain
In this paper harmonic source identification has been done using active power direction method with the study of distortion caused by loads at the system nodes. The active power direction method is being continuously used until present date with required modifications and integration with other techniques in order to improve its application for the purpose of harmonic source detection. The effect of disturbing loads at the nodes renders significant information regarding the type of load connected to it. A comparative study of distorting and non-distorting portion of load parameters along with the power direction analysis is used as an effective tool to identify harmonic sources present in the system, better performance can be witnessed in this work on various test cases where power direction method fails. The effectiveness of the proposed technique has been tested on a modified IEEE 5 bus system and IEEE 9 bus system.
{"title":"Harmonic Source Identification Using Modified Power Direction Method","authors":"Pragya Joshi, S. K. Jain","doi":"10.1109/RTEICT46194.2019.9016776","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016776","url":null,"abstract":"In this paper harmonic source identification has been done using active power direction method with the study of distortion caused by loads at the system nodes. The active power direction method is being continuously used until present date with required modifications and integration with other techniques in order to improve its application for the purpose of harmonic source detection. The effect of disturbing loads at the nodes renders significant information regarding the type of load connected to it. A comparative study of distorting and non-distorting portion of load parameters along with the power direction analysis is used as an effective tool to identify harmonic sources present in the system, better performance can be witnessed in this work on various test cases where power direction method fails. The effectiveness of the proposed technique has been tested on a modified IEEE 5 bus system and IEEE 9 bus system.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"336 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132419240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016734
S. Patil, M. Rane, S. Bindu
A measuring system which can measure high voltage impulses is been implemented using resistive and capacitive divider network. The simulation of this resistive divider is been done in MATLAB Software with the ten stage Marx circuit and results are calculated which are then matched with both the capacitive divider network and the resistive divider network. The voltage values of resistive divider and capacitive divider are calculated and compared. It is seen that the resistive divider network has excellent response characteristics as compared to capacitive divider network. The experimental result shows that it can measure the voltage quantities up to 5000V, which has pulse width of $5mu$ -sec sheet.
{"title":"Issues with High Volatage Measurement and its Mitigation","authors":"S. Patil, M. Rane, S. Bindu","doi":"10.1109/RTEICT46194.2019.9016734","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016734","url":null,"abstract":"A measuring system which can measure high voltage impulses is been implemented using resistive and capacitive divider network. The simulation of this resistive divider is been done in MATLAB Software with the ten stage Marx circuit and results are calculated which are then matched with both the capacitive divider network and the resistive divider network. The voltage values of resistive divider and capacitive divider are calculated and compared. It is seen that the resistive divider network has excellent response characteristics as compared to capacitive divider network. The experimental result shows that it can measure the voltage quantities up to 5000V, which has pulse width of $5mu$ -sec sheet.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122197284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016739
Daliya Velandi Thiruvoth, A. Raj, B. P. Kumar, V. S. Kumar, R. Gupta
A dual-band reflectarray microstrip patch antenna element is presented in this paper. The concept of polarization diversity is effectively utilized in the design with the cross-polarization level obtained well below -25dB in both the principal planes. This supports the implementation of dual-band operation from the same element. The two orthogonal modes of a rectangular patch: TM01, and TM10, are exploited for the dual-band operation. The inherent narrow bandwidth of the element fulfils the requirement of the present work at both the downlink and uplink frequencies of 11.4 GHz and 13.2 GHz respectively. The bandwidth is measured to be 2% to 3%, which effectively keeps the design simple. Also, a good port isolation of 27 dB at downlink band and 20 dB at uplink band are observed. A measured return loss of 17.7 dB at 11.4 GHz and 26 dB at 13.2 GHz are obtained with an acceptable deviation of only 0.65% (75 MHz) at downlink frequency. Based on this element a configuration for dual-band reflectarray is also proposed.
{"title":"Dual-Band Shared-Aperture Reflectarray Antenna Element at Ku-Band for the TT&C Application of a Geostationary Satellite","authors":"Daliya Velandi Thiruvoth, A. Raj, B. P. Kumar, V. S. Kumar, R. Gupta","doi":"10.1109/RTEICT46194.2019.9016739","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016739","url":null,"abstract":"A dual-band reflectarray microstrip patch antenna element is presented in this paper. The concept of polarization diversity is effectively utilized in the design with the cross-polarization level obtained well below -25dB in both the principal planes. This supports the implementation of dual-band operation from the same element. The two orthogonal modes of a rectangular patch: TM01, and TM10, are exploited for the dual-band operation. The inherent narrow bandwidth of the element fulfils the requirement of the present work at both the downlink and uplink frequencies of 11.4 GHz and 13.2 GHz respectively. The bandwidth is measured to be 2% to 3%, which effectively keeps the design simple. Also, a good port isolation of 27 dB at downlink band and 20 dB at uplink band are observed. A measured return loss of 17.7 dB at 11.4 GHz and 26 dB at 13.2 GHz are obtained with an acceptable deviation of only 0.65% (75 MHz) at downlink frequency. Based on this element a configuration for dual-band reflectarray is also proposed.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130361395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016886
Srinivas Ramavath, Balkrishna Ramavath, R. Akhil
The filter bank multicarrier (FBMC) with offset quadrature amplitude modulation (OQAM) is appreciated for its well-localization in time-frequency domain. However, the major drawbacks of FBMC is high peak to average power ratio (PAPR). In this article,we extend the idea of Discrete Fourier Transform(DFT) spreaded based FBMC scheme theoretically and address the theoretical analysis of the PAPR of the DFT-spread FBMC transmitted signal. The simulation results show that the proposed scheme achieves substantially lower PAPR, low PSD leakage and lower BER than the previous FBMC scheme. We also theoretically derive the expression of the PAPR of proposed scheme. Finally, this paper highlights the strengths and weaknesses of FBMC and DFT based FMBMC
{"title":"Theoretical Analysis of the PAPR for DFT Spreading Based FBMC","authors":"Srinivas Ramavath, Balkrishna Ramavath, R. Akhil","doi":"10.1109/RTEICT46194.2019.9016886","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016886","url":null,"abstract":"The filter bank multicarrier (FBMC) with offset quadrature amplitude modulation (OQAM) is appreciated for its well-localization in time-frequency domain. However, the major drawbacks of FBMC is high peak to average power ratio (PAPR). In this article,we extend the idea of Discrete Fourier Transform(DFT) spreaded based FBMC scheme theoretically and address the theoretical analysis of the PAPR of the DFT-spread FBMC transmitted signal. The simulation results show that the proposed scheme achieves substantially lower PAPR, low PSD leakage and lower BER than the previous FBMC scheme. We also theoretically derive the expression of the PAPR of proposed scheme. Finally, this paper highlights the strengths and weaknesses of FBMC and DFT based FMBMC","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130606672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016808
Apoorva Raghunandan, RAVISH ARADHYA H V
A good VLSI Design is one with low area occupancy and high speed of operation. As per Moore's law the number of transistors on a chip, increase and so does the overall chip Area. Optimizing the parameters of Area and Delay is of high importance in VLSI Design. Performance analysis and comparison of Area occupancy and Delay has been performed for 4 adders - the Ripple Carry Adder (Adder 1), the Kogge Stone Adder (Adder 2), the Carry Skip Adder (Adder 3) and the Brent Kung Adder (Adder 4), each being a 16-bit adder. The Adders were designed using Verilog code and then simulated and synthesized using RTL Encounter tool. Netlists were generated using the nclaunch tool for the three technologies. The Area and Delay results have been obtained for three technologies namely 180nm, 90nm and 45nm. At 180m, the Ripple Carry Adder occupies the least area of 1118nm2and Kogge Stone Adder has the smallest Delay of 3.495ns. At 90nm, the Ripple Carry Adder occupies the smallest Area of 315nm2 and the Kogge Stone Adder has the smallest delay of 2.957ns. The Ripple Carry Adder has a delay of 3.875ns in [3]. The reduction of delay in the paper is 10.99%.. The Carry Skip Adder has a delay of 8.106ns in [3] and a reduction of 64.16% is obtained in this paper. The Kogge Stone Adder has a delay of 6.7ns in [3]. A delay reduction of 63.65% is obtained in this paper. In [3], The Brent Kung Adder has a delay of 8.094ns. A reduction of 71.14% is obtained Amongst the four adders it has been found that the Brent Kung occupies the least Area of 123nm2 at 45nm and also has the smallest delay of 2.336 ns.
{"title":"Area and Timing Analysis of Advanced Adders under changing Technologies","authors":"Apoorva Raghunandan, RAVISH ARADHYA H V","doi":"10.1109/RTEICT46194.2019.9016808","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016808","url":null,"abstract":"A good VLSI Design is one with low area occupancy and high speed of operation. As per Moore's law the number of transistors on a chip, increase and so does the overall chip Area. Optimizing the parameters of Area and Delay is of high importance in VLSI Design. Performance analysis and comparison of Area occupancy and Delay has been performed for 4 adders - the Ripple Carry Adder (Adder 1), the Kogge Stone Adder (Adder 2), the Carry Skip Adder (Adder 3) and the Brent Kung Adder (Adder 4), each being a 16-bit adder. The Adders were designed using Verilog code and then simulated and synthesized using RTL Encounter tool. Netlists were generated using the nclaunch tool for the three technologies. The Area and Delay results have been obtained for three technologies namely 180nm, 90nm and 45nm. At 180m, the Ripple Carry Adder occupies the least area of 1118nm2and Kogge Stone Adder has the smallest Delay of 3.495ns. At 90nm, the Ripple Carry Adder occupies the smallest Area of 315nm2 and the Kogge Stone Adder has the smallest delay of 2.957ns. The Ripple Carry Adder has a delay of 3.875ns in [3]. The reduction of delay in the paper is 10.99%.. The Carry Skip Adder has a delay of 8.106ns in [3] and a reduction of 64.16% is obtained in this paper. The Kogge Stone Adder has a delay of 6.7ns in [3]. A delay reduction of 63.65% is obtained in this paper. In [3], The Brent Kung Adder has a delay of 8.094ns. A reduction of 71.14% is obtained Amongst the four adders it has been found that the Brent Kung occupies the least Area of 123nm2 at 45nm and also has the smallest delay of 2.336 ns.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131727309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016731
G. Vijay, M. N. Ramanarayan, A. Chavan
The number of road accidents is increasing every year due to increases in vehicle and driver negligence, and it leads to a serious issue in front of modern society. Unintended lane departure and rear end collisions are some of the main reason behind road accidents in the freeway. However, it is now possible to prevent this problem to some extent, by using Advance driver assistant system (ADAS). This paper presents a Design and integration of lane departure warning, adaptive headlight and wiper system which works on different road and illumination conditions. The system uses a raspberry pi for video processing and arduino Mega is used as processing unit for AHAWS. The algorithm of LDWS takes video input frame by frame, filters the frame detects edges using canny edge detection, the lane detection decision is done by Hough transform using OpenCV python software. Based on the position of the car inside the detected lanes the warning is raised. The AHAWS algorithm takes three inputs road curvature which is given by LDWS in case of integrated system, surrounding light intensity and rain intensity based on the input the headlight will turn along with curve, the headlight intensity is adjusted according to surrounding light and wiper frequency is set according to rain intensity. The experimental results States that the AHWAS responds quickly to change in input, the average lane detection rate and the departure warning rate are 99.8% and 92.1%, respectively. With a $720times 1280$ resolution, the average processing speed is 22.2 fp/s.
{"title":"Design and Integration of Lane Departure Warning, Adaptive Headlight and Wiper system for Automobile Safety","authors":"G. Vijay, M. N. Ramanarayan, A. Chavan","doi":"10.1109/RTEICT46194.2019.9016731","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016731","url":null,"abstract":"The number of road accidents is increasing every year due to increases in vehicle and driver negligence, and it leads to a serious issue in front of modern society. Unintended lane departure and rear end collisions are some of the main reason behind road accidents in the freeway. However, it is now possible to prevent this problem to some extent, by using Advance driver assistant system (ADAS). This paper presents a Design and integration of lane departure warning, adaptive headlight and wiper system which works on different road and illumination conditions. The system uses a raspberry pi for video processing and arduino Mega is used as processing unit for AHAWS. The algorithm of LDWS takes video input frame by frame, filters the frame detects edges using canny edge detection, the lane detection decision is done by Hough transform using OpenCV python software. Based on the position of the car inside the detected lanes the warning is raised. The AHAWS algorithm takes three inputs road curvature which is given by LDWS in case of integrated system, surrounding light intensity and rain intensity based on the input the headlight will turn along with curve, the headlight intensity is adjusted according to surrounding light and wiper frequency is set according to rain intensity. The experimental results States that the AHWAS responds quickly to change in input, the average lane detection rate and the departure warning rate are 99.8% and 92.1%, respectively. With a $720times 1280$ resolution, the average processing speed is 22.2 fp/s.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":" 105","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016760
A. Sharma
Recently, power gating technique is being adopted in many designs for minimizing power consumption (MTCMOS). This paper mounts new hybrid-logic circuit design for inverted 4–16 decoder invented using sleep transistor capable of lowering power dissipation and power-delay product(PDP). Two circuit designs are proposed here using DEC-14 topology and DEC-15 topology at supply voltage of 1V and 10MHz frequency. Also, pulse input is provided to sleep transistor for switching action at 10MHz frequency. Employing this technique, considerably reduces leakage power, benefitting circuit design by improvising its key parameters. Later, various simulations results are represented on 32nm technology showing brief comparison between distinct circuits.
{"title":"Optimizing Power and Improving Performance of 4-16 Hybrid-Logic Line Decoder using Power Gating Technique","authors":"A. Sharma","doi":"10.1109/RTEICT46194.2019.9016760","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016760","url":null,"abstract":"Recently, power gating technique is being adopted in many designs for minimizing power consumption (MTCMOS). This paper mounts new hybrid-logic circuit design for inverted 4–16 decoder invented using sleep transistor capable of lowering power dissipation and power-delay product(PDP). Two circuit designs are proposed here using DEC-14 topology and DEC-15 topology at supply voltage of 1V and 10MHz frequency. Also, pulse input is provided to sleep transistor for switching action at 10MHz frequency. Employing this technique, considerably reduces leakage power, benefitting circuit design by improvising its key parameters. Later, various simulations results are represented on 32nm technology showing brief comparison between distinct circuits.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"140 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129088963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-05-01DOI: 10.1109/RTEICT46194.2019.9016972
P. Singla, Urvashi Bansal
With bulk CMOS technology scaling below 100 nm, there is significant increase of leakage power in that. Multigate FET like FINFET and CNTFET (carbon Nano tube field effect transistor) are the devices to replace that because of improved drive strength and short channel behavior. This paper represents dual supply voltage level shifter which is capable of converting low input of voltage to high level. This proposes a comparative study of voltage level shifter at 32nm technology node of MOSFET, FINFET and CNTFET. Simulations results tells us that there is notable improvement at frequency 0.5Mz in average power and PDP of 7.50E-07 W and 3.57E-14 in FINFET and 9.58E-07 W and 2.45E − 14 in case of CNTFET with comparison of MOSFET.
{"title":"Performance Optimization of Dual supply voltage level shifter using FINFET and CNTFET at 32nm technology","authors":"P. Singla, Urvashi Bansal","doi":"10.1109/RTEICT46194.2019.9016972","DOIUrl":"https://doi.org/10.1109/RTEICT46194.2019.9016972","url":null,"abstract":"With bulk CMOS technology scaling below 100 nm, there is significant increase of leakage power in that. Multigate FET like FINFET and CNTFET (carbon Nano tube field effect transistor) are the devices to replace that because of improved drive strength and short channel behavior. This paper represents dual supply voltage level shifter which is capable of converting low input of voltage to high level. This proposes a comparative study of voltage level shifter at 32nm technology node of MOSFET, FINFET and CNTFET. Simulations results tells us that there is notable improvement at frequency 0.5Mz in average power and PDP of 7.50E-07 W and 3.57E-14 in FINFET and 9.58E-07 W and 2.45E − 14 in case of CNTFET with comparison of MOSFET.","PeriodicalId":269385,"journal":{"name":"2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128768739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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