Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870255
Christopher J. Gonzalez, E. Fluhr, D. Dreps, David Hogenmiller, R. Rao, Jose Paredes, M. Floyd, M. Sperling, Ryan Kruse, Vinod Ramadurai, R. Nett, M. S. Islam, J. Pille, D. Plass
Cognitive computing and cloud infrastructure require flexible, connectable, and scalable processors with extreme IO bandwidth. With 4 distinct chip configurations, the POWER9 family of chips delivers multiple options for memory ports, core thread counts, and accelerator options to address this need. The 24-core scale-out processor is implemented in 14nm SOI FinFET technology [1] and contains 8.0B transistors. The 695mm2 chip uses 17 levels of copper interconnect: 3–64nm, 2–80nm, 4–128nm, 2–256nm, 4–360nm pitch wiring for signals and 2– 2400nm pitch wiring levels for power and global clock distribution. Digital logic uses three thin-oxide transistor Vts to balance power and performance requirements, while analog and high-voltage circuits eliminated thick-oxide devices providing process simplification and cost reduction. By leveraging the FinFET's increased current per area, the base standard cell image shrunk from 18 tracks per bit in planar 22nm to 10 tracks per bit in 14nm providing additional area scaling.
{"title":"3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4","authors":"Christopher J. Gonzalez, E. Fluhr, D. Dreps, David Hogenmiller, R. Rao, Jose Paredes, M. Floyd, M. Sperling, Ryan Kruse, Vinod Ramadurai, R. Nett, M. S. Islam, J. Pille, D. Plass","doi":"10.1109/ISSCC.2017.7870255","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870255","url":null,"abstract":"Cognitive computing and cloud infrastructure require flexible, connectable, and scalable processors with extreme IO bandwidth. With 4 distinct chip configurations, the POWER9 family of chips delivers multiple options for memory ports, core thread counts, and accelerator options to address this need. The 24-core scale-out processor is implemented in 14nm SOI FinFET technology [1] and contains 8.0B transistors. The 695mm2 chip uses 17 levels of copper interconnect: 3–64nm, 2–80nm, 4–128nm, 2–256nm, 4–360nm pitch wiring for signals and 2– 2400nm pitch wiring levels for power and global clock distribution. Digital logic uses three thin-oxide transistor Vts to balance power and performance requirements, while analog and high-voltage circuits eliminated thick-oxide devices providing process simplification and cost reduction. By leveraging the FinFET's increased current per area, the base standard cell image shrunk from 18 tracks per bit in planar 22nm to 10 tracks per bit in 14nm providing additional area scaling.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127253511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870249
Xun Liu, Heng Zhang, Min Zhao, Xuan Chen, P. Mok, H. Luong
Long-term-evolution (LTE) communication enables high data-rates but degrades the efficiency of the power amplifiers (PAs) due to high peak-to-average power ratios of transmitted signals. Envelope tracking (ET) and envelope-elimination-and-restoration (EER) techniques have been proposed to improve the PA efficiency by adapting the PA supply voltage to the envelope. Linear PAs in ET systems are mostly implemented in non-CMOS technologies for high efficiency [1]. However, the growing demand for low-cost integrated systems has motivated the use of CMOS PAs [2]. The main drawback of this is that linear CMOS PAs have poor efficiency. The high efficiency of switching PAs makes them a promising candidate in CMOS [3]. In EER systems, where switching PAs are used, the supply modulator must satisfy stringent noise and bandwidth specifications in order to recover the amplitude information of the LTE signal. Thus, it is a challenge for supply modulators to maintain high efficiency. Recently, a number of methods have been adopted to improve supply-modulator efficiency. In [1], a dual-switching topology is proposed, but it requires an additional inductor and results in an unpredictable noise spectrum. In [4], an AC-coupling topology is adopted to reduce the supply voltage of the linear amplifier. However, due to the slow response of the switching amplifier, the efficiency is still low.
{"title":"2.4 A 2.4V 23.9dBm 35.7%-PAE -32.1dBc-ACLR LTE-20MHz envelope-shaping-and-tracking system with a multiloop-controlled AC-coupling supply modulator and a mode-switching PA","authors":"Xun Liu, Heng Zhang, Min Zhao, Xuan Chen, P. Mok, H. Luong","doi":"10.1109/ISSCC.2017.7870249","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870249","url":null,"abstract":"Long-term-evolution (LTE) communication enables high data-rates but degrades the efficiency of the power amplifiers (PAs) due to high peak-to-average power ratios of transmitted signals. Envelope tracking (ET) and envelope-elimination-and-restoration (EER) techniques have been proposed to improve the PA efficiency by adapting the PA supply voltage to the envelope. Linear PAs in ET systems are mostly implemented in non-CMOS technologies for high efficiency [1]. However, the growing demand for low-cost integrated systems has motivated the use of CMOS PAs [2]. The main drawback of this is that linear CMOS PAs have poor efficiency. The high efficiency of switching PAs makes them a promising candidate in CMOS [3]. In EER systems, where switching PAs are used, the supply modulator must satisfy stringent noise and bandwidth specifications in order to recover the amplitude information of the LTE signal. Thus, it is a challenge for supply modulators to maintain high efficiency. Recently, a number of methods have been adopted to improve supply-modulator efficiency. In [1], a dual-switching topology is proposed, but it requires an additional inductor and results in an unpredictable noise spectrum. In [4], an AC-coupling topology is adopted to reduce the supply voltage of the linear amplifier. However, due to the slow response of the switching amplifier, the efficiency is still low.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125154289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870328
Ryuji Yamashita, Sagar Magia, T. Higuchi, Kazuhide Yoneya, T. Yamamura, Hiroyuki Mizukoshi, S. Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang, Ying Yu, Yuko Utsunomiya, Yosuke Kato, Manabu Sakai, Masahide Matsumoto, H. Chibvongodze, Naoki Ookuma, Hiroki Yabe, Subodh Taigor, Rangarao Samineni, T. Kodama, Y. Kamata, Y. Namai, Jonathan Huynh, Sung-En Wang, Y. He, T. Pham, V. Saraf, Akshay Petkar, Mitsuyuki Watanabe, Koichiro Hayashi, Prashant Swarnkar, H. Miwa, Adit Pradhan, Sulagna Dey, Debasis Dwibedy, Thushara Xavier, Muralikrishna Balaga, Samiksha Agarwal, Swaroop Kulkarni, Zameer Papasaheb, Sahil Deora, Patrick Hong, Meiling Wei, G. Balakrishnan, Takuya Ariki, Kapil Verma, C. Siau, Yingda Dong, Ching-Huang Lu, Toru Miwa, F. Moogat
High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013 [1,2]). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash [3], recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density by increasing the number of stacked layers. The first 3b/cell 3D-flash used 32 layers in 2015 [4], and reached 48 layers in 2016 [5]. Also, density as high as 2.62 and 4.29Gb/mm2 [5,6] were achieved, as shown in Fig. 11.1.7. This rapid scaling of 3D-flash technologies is possible since it is free from the lithography limitation mentioned above. This paper describes a 512Gbit 3b/cell flash fabricated with a 64-word-line-layer BiCS technology. In this work, we implemented three technologies: (1) four-block even-odd-combined row decoding to effectively address the increase of stacked layers; (2) unselected string pre-charge operation to improve endurance and reliability, and; (3) shielded BL current sensing to enhance read throughput. Figure 11.1.1 shows the die photo and the summary of key features.
{"title":"11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology","authors":"Ryuji Yamashita, Sagar Magia, T. Higuchi, Kazuhide Yoneya, T. Yamamura, Hiroyuki Mizukoshi, S. Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang, Ying Yu, Yuko Utsunomiya, Yosuke Kato, Manabu Sakai, Masahide Matsumoto, H. Chibvongodze, Naoki Ookuma, Hiroki Yabe, Subodh Taigor, Rangarao Samineni, T. Kodama, Y. Kamata, Y. Namai, Jonathan Huynh, Sung-En Wang, Y. He, T. Pham, V. Saraf, Akshay Petkar, Mitsuyuki Watanabe, Koichiro Hayashi, Prashant Swarnkar, H. Miwa, Adit Pradhan, Sulagna Dey, Debasis Dwibedy, Thushara Xavier, Muralikrishna Balaga, Samiksha Agarwal, Swaroop Kulkarni, Zameer Papasaheb, Sahil Deora, Patrick Hong, Meiling Wei, G. Balakrishnan, Takuya Ariki, Kapil Verma, C. Siau, Yingda Dong, Ching-Huang Lu, Toru Miwa, F. Moogat","doi":"10.1109/ISSCC.2017.7870328","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870328","url":null,"abstract":"High floating-gate (FG) to FG coupling and lithography limitations have been preventing 2D-NAND flash from further reduction in die size, (e.g., there is no ISSCC paper discussing a 3b/cell 2D-NAND after 2013 [1,2]). Alternatively, since high-density multi-stacked 3D-flash was first introduced as BiCS flash [3], recent dramatic innovations in 3D-flash technologies are rapidly boosting bit density by increasing the number of stacked layers. The first 3b/cell 3D-flash used 32 layers in 2015 [4], and reached 48 layers in 2016 [5]. Also, density as high as 2.62 and 4.29Gb/mm2 [5,6] were achieved, as shown in Fig. 11.1.7. This rapid scaling of 3D-flash technologies is possible since it is free from the lithography limitation mentioned above. This paper describes a 512Gbit 3b/cell flash fabricated with a 64-word-line-layer BiCS technology. In this work, we implemented three technologies: (1) four-block even-odd-combined row decoding to effectively address the increase of stacked layers; (2) unselected string pre-charge operation to improve endurance and reliability, and; (3) shielded BL current sensing to enhance read throughput. Figure 11.1.1 shows the die photo and the summary of key features.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123308880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870319
N. Butzen, M. Steyaert
Over the past years, delivering power to integrated circuits has become increasingly difficult. With the current intake of many modern-day applications growing each new process generation, the Power Delivery Network (PDN) losses have increased as well. By integrating a DC-DC converter together with the load, part of the required voltage conversion can be realized on-chip, and the current intake, together with the PDN losses, can thus ideally be reduced by its Voltage Conversion Ratio (VCR). In order to be viable, though, the converter must 1) have a high efficiency and VCR such that its losses are smaller than the reduction of PDN losses, 2) limit the area overhead by achieving high power density and 3) rely only on commonly available devices to enable wide-spread use.
{"title":"10.1 A 1.1W/mm2-power-density 82%-efficiency fully integrated 3∶1 Switched-Capacitor DC-DC converter in baseline 28nm CMOS using Stage Outphasing and Multiphase Soft-Charging","authors":"N. Butzen, M. Steyaert","doi":"10.1109/ISSCC.2017.7870319","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870319","url":null,"abstract":"Over the past years, delivering power to integrated circuits has become increasingly difficult. With the current intake of many modern-day applications growing each new process generation, the Power Delivery Network (PDN) losses have increased as well. By integrating a DC-DC converter together with the load, part of the required voltage conversion can be realized on-chip, and the current intake, together with the PDN losses, can thus ideally be reduced by its Voltage Conversion Ratio (VCR). In order to be viable, though, the converter must 1) have a high efficiency and VCR such that its losses are smaller than the reduction of PDN losses, 2) limit the area overhead by achieving high power density and 3) rely only on commonly available devices to enable wide-spread use.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125277117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870425
Chang-Kyo Lee, Yoon-Joo Eom, Jin-Hee Park, Junha Lee, Hye-Ran Kim, Kihan Kim, Young-Ryeol Choi, Ho-Jun Chang, Jonghyuk Kim, Jong-Min Bang, Seungjun Shin, Hanna Park, Su-Jin Park, Young-Ryeol Choi, Hoon Lee, Kyong-Ho Jeon, Jae-Young Lee, Hyo-Joo Ahn, Kyoung-Ho Kim, Jung-Sik Kim, Soobong Chang, H. Hwang, Du-Hwi Kim, Yoon-Hwan Yoon, S. Hyun, Joonbae Park, Yoon-Gyu Song, Youn-Sik Park, H. Kwon, Seung-Jun Bae, T. Oh, Indal Song, Yong-Cheol Bae, J. Choi, Kwang-il Park, Seong-Jin Jang, G. Jin
With growing demand for low-power mobile applications, such as wearable devices, smart phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory requirement for low-power system designs. The recently developed LPDDR4 [1] is still a power efficient solution because of its architectural approaches and low-voltage-swing terminated logic (LVSTL). However, demand for enhanced power-efficiency beyond LPDDR4 is still increasing for mobile applications. In this work, a 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.
{"title":"23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme","authors":"Chang-Kyo Lee, Yoon-Joo Eom, Jin-Hee Park, Junha Lee, Hye-Ran Kim, Kihan Kim, Young-Ryeol Choi, Ho-Jun Chang, Jonghyuk Kim, Jong-Min Bang, Seungjun Shin, Hanna Park, Su-Jin Park, Young-Ryeol Choi, Hoon Lee, Kyong-Ho Jeon, Jae-Young Lee, Hyo-Joo Ahn, Kyoung-Ho Kim, Jung-Sik Kim, Soobong Chang, H. Hwang, Du-Hwi Kim, Yoon-Hwan Yoon, S. Hyun, Joonbae Park, Yoon-Gyu Song, Youn-Sik Park, H. Kwon, Seung-Jun Bae, T. Oh, Indal Song, Yong-Cheol Bae, J. Choi, Kwang-il Park, Seong-Jin Jang, G. Jin","doi":"10.1109/ISSCC.2017.7870425","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870425","url":null,"abstract":"With growing demand for low-power mobile applications, such as wearable devices, smart phones and tablet PCs, low-power mobile DRAM has been identified as a mandatory requirement for low-power system designs. The recently developed LPDDR4 [1] is still a power efficient solution because of its architectural approaches and low-voltage-swing terminated logic (LVSTL). However, demand for enhanced power-efficiency beyond LPDDR4 is still increasing for mobile applications. In this work, a 5.0Gbp/s/pin 8Gb LPDDR4X memory with power-isolated low-voltage-swing terminated logic (PI-LVSTL) and a split-die architecture is proposed to enhance power-efficiency and mass production yield.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125500109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870324
Lin Cheng, W. Ki
Fast load-transient responses are crucial for DC-DC converters to cope with the demands of modern highly integrated system-on-chip (SoC) designs. Various techniques have been proposed to improve transient responses by enhancing the speed of the controller, and/or by increasing the slew rate of the inductor current (SRL), as shown in Fig. 10.6.1. To enhance the speed of the controller, a capacitor-current-sensor (CCS) calibration technique with load-transient optimization (LTO) is proposed for current-mode control in [1], and zero-delay synchronized (ZDS) and quasi-current-mode hysteretic control are proposed in [2] and [3], respectively. Although these converters may achieve near-optimal transient responses (only limited by SRL), the circuit complexity is greatly increased. To increase SRL, multiphase topologies have been widely used [1], [2,4]. For an N-phase converter, SRL can be effectively increased by N times, at the expense of using N bulky inductors that increase both volume and cost. Hybrid schemes that comprise the parallel operation of the DC-DC converter and a linear regulator can improve the responses by injecting additional charging current (Ich) without adding extra inductors. In [5], activating and deactivating the hybrid scheme is accomplished by monitoring the output voltage Vo within the steady-state window [Vo-ΔVo, Vo]. However, a large ΔVo is needed for good noise immunity, and the slow SRL also requires a high Ich that increases loss during the transients.
{"title":"10.6 A 30MHz hybrid buck converter with 36mV droop and 125ns 1% settling time for a 1.25A/2ns load transient","authors":"Lin Cheng, W. Ki","doi":"10.1109/ISSCC.2017.7870324","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870324","url":null,"abstract":"Fast load-transient responses are crucial for DC-DC converters to cope with the demands of modern highly integrated system-on-chip (SoC) designs. Various techniques have been proposed to improve transient responses by enhancing the speed of the controller, and/or by increasing the slew rate of the inductor current (SRL), as shown in Fig. 10.6.1. To enhance the speed of the controller, a capacitor-current-sensor (CCS) calibration technique with load-transient optimization (LTO) is proposed for current-mode control in [1], and zero-delay synchronized (ZDS) and quasi-current-mode hysteretic control are proposed in [2] and [3], respectively. Although these converters may achieve near-optimal transient responses (only limited by SRL), the circuit complexity is greatly increased. To increase SRL, multiphase topologies have been widely used [1], [2,4]. For an N-phase converter, SRL can be effectively increased by N times, at the expense of using N bulky inductors that increase both volume and cost. Hybrid schemes that comprise the parallel operation of the DC-DC converter and a linear regulator can improve the responses by injecting additional charging current (Ich) without adding extra inductors. In [5], activating and deactivating the hybrid scheme is accomplished by monitoring the output voltage Vo within the steady-state window [Vo-ΔVo, Vo]. However, a large ΔVo is needed for good noise immunity, and the slow SRL also requires a high Ich that increases loss during the transients.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126640303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870372
J. Keane, N. J. Guilar, D. Stepanovic, B. Wuppermann, Charles Wu, C. Tsang, R. Neff, K. Nishimura
This paper describes an 8GS/s 16-way time-interleaved ADC for a test and measurement application. Each ADC slice is a 1b/cycle, synchronous SAR operating at 500MS/s. The ADC slice schematic is shown in Fig. 16.5.1. The input is sampled using a thick-oxide NFET driven by a 1.9V buffer. After each conversion the hold node is reset differentially using a core NFET driven by a 1.1V buffer. The 10b DAC consists of two identical 5b halves separated by a bridging capacitor, Cbridge. Cbridge is sized to provide approximately 0.8b of redundancy between the MSB and LSB halves, enabling capacitor mismatch in the MSB half to be corrected digitally. The DAC is controlled by decision latches and uses the split-capacitor switching scheme [1] to provide a constant common mode to the comparator during conversion. The DAC comprises approximately 60% of the 250fF/side hold capacitance, resulting in a 1.2Vppd full-scale range when a 1V reference is used.
{"title":"16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving −58dBFS noise and 4GHz bandwidth in 28nm CMOS","authors":"J. Keane, N. J. Guilar, D. Stepanovic, B. Wuppermann, Charles Wu, C. Tsang, R. Neff, K. Nishimura","doi":"10.1109/ISSCC.2017.7870372","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870372","url":null,"abstract":"This paper describes an 8GS/s 16-way time-interleaved ADC for a test and measurement application. Each ADC slice is a 1b/cycle, synchronous SAR operating at 500MS/s. The ADC slice schematic is shown in Fig. 16.5.1. The input is sampled using a thick-oxide NFET driven by a 1.9V buffer. After each conversion the hold node is reset differentially using a core NFET driven by a 1.1V buffer. The 10b DAC consists of two identical 5b halves separated by a bridging capacitor, Cbridge. Cbridge is sized to provide approximately 0.8b of redundancy between the MSB and LSB halves, enabling capacitor mismatch in the MSB half to be corrected digitally. The DAC is controlled by decision latches and uses the split-capacitor switching scheme [1] to provide a constant common mode to the comparator during conversion. The DAC comprises approximately 60% of the 250fF/side hold capacitance, resulting in a 1.2Vppd full-scale range when a 1V reference is used.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122798941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870380
M. Hashemi, Yiyu Shen, M. Mehrpoo, M. Acar, R. V. Leuken, M. Alavi, L. D. Vreede
To fully benefit from the progress of CMOS technologies, it is desirable to completely digitize the TX, replacing its final stage with a digitally controlled PA (DPA). The DPA consists of arrays of small sub-PAs that are digitally controlled to modulate the output amplitude, thus operating as an RF-DAC [1–6]. DPAs are normally designed in a switched mode (Classes E/D/D−1, etc.) to achieve high efficiency while using high sampling rate to attenuate and push the spectral images to higher frequencies. However, they suffer from high nonlinearity in their AM-code-word (ACW) to AM and ACW-to-PM conversion. To correct for such nonlinearities, digital pre-distortion (DPD) of the input signal is often used [1–3], typically implemented by look-up tables (LUT). Unfortunately, DPD approaches suffer from large signal-BW expansion due to their inherently nonlinear characteristics. This, combined with the already present BW regrowth in a polar TX in the AM and PM paths, yields significant hardware-speed/power constraints when the signal BW becomes large. For a Cartesian TX, the use of LUT-DPD is even more complicated since a full 2D LUT is typically required [2]. To relax the overall system complexity, it is highly desirable to have a PA with a maximum inherent linearity without compromising its power or efficiency. In this work, an ACW-AM correction based on nonlinear sizing along with controlling the peak voltage of RF clocks (overdrive voltage tuning) and a ACW-PM correction based on multiphase RF clocking are introduced to linearize the characteristic curves of a Class-E polar DPA with intent to avoid any kind of pre-distortion.
{"title":"17.5 An intrinsically linear wideband digital polar PA featuring AM-AM and AM-PM corrections through nonlinear sizing, overdrive-voltage control, and multiphase RF clocking","authors":"M. Hashemi, Yiyu Shen, M. Mehrpoo, M. Acar, R. V. Leuken, M. Alavi, L. D. Vreede","doi":"10.1109/ISSCC.2017.7870380","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870380","url":null,"abstract":"To fully benefit from the progress of CMOS technologies, it is desirable to completely digitize the TX, replacing its final stage with a digitally controlled PA (DPA). The DPA consists of arrays of small sub-PAs that are digitally controlled to modulate the output amplitude, thus operating as an RF-DAC [1–6]. DPAs are normally designed in a switched mode (Classes E/D/D−1, etc.) to achieve high efficiency while using high sampling rate to attenuate and push the spectral images to higher frequencies. However, they suffer from high nonlinearity in their AM-code-word (ACW) to AM and ACW-to-PM conversion. To correct for such nonlinearities, digital pre-distortion (DPD) of the input signal is often used [1–3], typically implemented by look-up tables (LUT). Unfortunately, DPD approaches suffer from large signal-BW expansion due to their inherently nonlinear characteristics. This, combined with the already present BW regrowth in a polar TX in the AM and PM paths, yields significant hardware-speed/power constraints when the signal BW becomes large. For a Cartesian TX, the use of LUT-DPD is even more complicated since a full 2D LUT is typically required [2]. To relax the overall system complexity, it is highly desirable to have a PA with a maximum inherent linearity without compromising its power or efficiency. In this work, an ACW-AM correction based on nonlinear sizing along with controlling the peak voltage of RF clocks (overdrive voltage tuning) and a ACW-PM correction based on multiphase RF clocking are introduced to linearize the characteristic curves of a Class-E polar DPA with intent to avoid any kind of pre-distortion.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129573784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870370
C. Erdmann, Edward Cullen, D. Brouard, R. Pelliconi, B. Verbruggen, John McGrath, Diarmuid Collins, M. D. L. Torre, Pierrick Gay, Patrick Lynch, P. Lim, A. Collins, B. Farley
Direct-RF synthesis has gained increasing attention in recent years [1] [2] as it simplifies the transmitter system by eliminating the intermediate frequency stage. It also offers the opportunity to address the extensive range of cellular bands with the same architecture and building blocks. Direct synthesis of carriers in the 5 to 6GHz unlicenced bands remains a challenge for RF-DACs operating in the 1st Nyquist band, as sampling rates in excess of 12GS/s are required. A more power efficient way to synthesize directly these frequencies is to use wideband mixing-DACs, which increase the output power in the 2nd and 3rd Nyquist bands [3]. In [3] the mixing is done using the quad-switch configuration, which doubles the number of switches and drivers, directly impacting the overall DAC width. In [4] the mixer is inserted in-line between the current cell switch and the output cascode, which requires additional headroom in the output stage. Both implementations impact the overall performance and power of the DAC even when the mixing operation is not used.
{"title":"16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving −70.8dBc ACPR in a 20MHz channel at 5.2GHz","authors":"C. Erdmann, Edward Cullen, D. Brouard, R. Pelliconi, B. Verbruggen, John McGrath, Diarmuid Collins, M. D. L. Torre, Pierrick Gay, Patrick Lynch, P. Lim, A. Collins, B. Farley","doi":"10.1109/ISSCC.2017.7870370","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870370","url":null,"abstract":"Direct-RF synthesis has gained increasing attention in recent years [1] [2] as it simplifies the transmitter system by eliminating the intermediate frequency stage. It also offers the opportunity to address the extensive range of cellular bands with the same architecture and building blocks. Direct synthesis of carriers in the 5 to 6GHz unlicenced bands remains a challenge for RF-DACs operating in the 1st Nyquist band, as sampling rates in excess of 12GS/s are required. A more power efficient way to synthesize directly these frequencies is to use wideband mixing-DACs, which increase the output power in the 2nd and 3rd Nyquist bands [3]. In [3] the mixing is done using the quad-switch configuration, which doubles the number of switches and drivers, directly impacting the overall DAC width. In [4] the mixer is inserted in-line between the current cell switch and the output cascode, which requires additional headroom in the output stage. Both implementations impact the overall performance and power of the DAC even when the mixing operation is not used.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129821498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870274
Ji-Hun Lee, Jun-Suk Bang, Kiduk Kim, Hui-Dong Gwon, Sang-Hui Park, Yeunhee Huh, K. Yoon, Jong-Beom Baek, Yong-Min Ju, Gibbeum Lee, Homin Park, Hyeon-Min Bae, G. Cho
As the portable device market tries to enhance user experience, high-power audio systems with boosted supply voltage have been the main design focus recently. Several past works have addressed issues related to boosted supply voltages [1,2]. Nevertheless, the power stage retained the classical H-bridge structure in the previous works, which resulted in aggravated electromagnetic interference (EMI) from high switching amplitude and poor efficiency due to voltage boosting. The use of multi-level pulse-width modulation (PWM) shown in Fig. 5.2.1 can naturally eliminate the complications caused by high supply voltages. Since the audio signal has a high crest factor, a multi-level Class-D amplifier draws most power directly from a low-voltage battery source, which in turn improves the power efficiency significantly [3]. Spread spectrum techniques prevent energy localization in the power spectral density [2]. Nevertheless, the diffusion of switching harmonics into the nearby frequencies complicates EMI management. However, the multi-level switching scheme suppresses EMI by reducing the switching amplitude without spreading the energy spectrum [4]. In this work, a new folded-PWM (FPWM) architecture implementing a multi-level H-bridge topology is presented.
{"title":"5.2 An 8Ω 10W 91%-power-efficiency 0.0023%-THD+N multi-level Class-D audio amplifier with folded PWM","authors":"Ji-Hun Lee, Jun-Suk Bang, Kiduk Kim, Hui-Dong Gwon, Sang-Hui Park, Yeunhee Huh, K. Yoon, Jong-Beom Baek, Yong-Min Ju, Gibbeum Lee, Homin Park, Hyeon-Min Bae, G. Cho","doi":"10.1109/ISSCC.2017.7870274","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870274","url":null,"abstract":"As the portable device market tries to enhance user experience, high-power audio systems with boosted supply voltage have been the main design focus recently. Several past works have addressed issues related to boosted supply voltages [1,2]. Nevertheless, the power stage retained the classical H-bridge structure in the previous works, which resulted in aggravated electromagnetic interference (EMI) from high switching amplitude and poor efficiency due to voltage boosting. The use of multi-level pulse-width modulation (PWM) shown in Fig. 5.2.1 can naturally eliminate the complications caused by high supply voltages. Since the audio signal has a high crest factor, a multi-level Class-D amplifier draws most power directly from a low-voltage battery source, which in turn improves the power efficiency significantly [3]. Spread spectrum techniques prevent energy localization in the power spectral density [2]. Nevertheless, the diffusion of switching harmonics into the nearby frequencies complicates EMI management. However, the multi-level switching scheme suppresses EMI by reducing the switching amplitude without spreading the energy spectrum [4]. In this work, a new folded-PWM (FPWM) architecture implementing a multi-level H-bridge topology is presented.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129947937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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