Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870482
J. V. Sinderen, D. Griffith, Ken Yamamoto, A. Liscidini, Young-sub Yuk
An overview and comparison is provided of the different emerging wireless standards and their circuit solutions, which target low data-rate IoT applications, featuring ultra-low-power and/or long-range. Different RF transceiver implementations are presented, including proprietary solutions in license-free spectrum, WLAN-based IEEE802.11ah solutions and mobile operators' alternatives based on emerging long-term evolution (LTEM) standards. The different approaches coming to the market and their circuit design aspects will be discussed.
{"title":"F4: Wireless low-power transceivers for local and wide-area networks","authors":"J. V. Sinderen, D. Griffith, Ken Yamamoto, A. Liscidini, Young-sub Yuk","doi":"10.1109/ISSCC.2017.7870482","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870482","url":null,"abstract":"An overview and comparison is provided of the different emerging wireless standards and their circuit solutions, which target low data-rate IoT applications, featuring ultra-low-power and/or long-range. Different RF transceiver implementations are presented, including proprietary solutions in license-free spectrum, WLAN-based IEEE802.11ah solutions and mobile operators' alternatives based on emerging long-term evolution (LTEM) standards. The different approaches coming to the market and their circuit design aspects will be discussed.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125047373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870336
I. Arsovski, Michael Fragano, R. Houle, A. Patil, V. Butler, Raymond Kim, R. Rodriguez, T. Maffitt, J. J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, S. Burns
Ternary Content Addressable Memory (TCAM) executes a fully parallel search of its entire memory contents and uses powerful wild-card pattern matching to return search results in a single clock cycle. This capability makes TCAM attractive for implementing fast hardware look-up tables in network routers, processor caches, and many pattern recognition applications. However, the push for higher performance and increased memory density coupled with parallel TCAM array activation during search operation creates large Ldi/dt power supply noise challenges that could result in timing fails in both TCAM and its surrounding logic.
{"title":"12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%","authors":"I. Arsovski, Michael Fragano, R. Houle, A. Patil, V. Butler, Raymond Kim, R. Rodriguez, T. Maffitt, J. J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, S. Burns","doi":"10.1109/ISSCC.2017.7870336","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870336","url":null,"abstract":"Ternary Content Addressable Memory (TCAM) executes a fully parallel search of its entire memory contents and uses powerful wild-card pattern matching to return search results in a single clock cycle. This capability makes TCAM attractive for implementing fast hardware look-up tables in network routers, processor caches, and many pattern recognition applications. However, the push for higher performance and increased memory density coupled with parallel TCAM array activation during search operation creates large Ldi/dt power supply noise challenges that could result in timing fails in both TCAM and its surrounding logic.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125329996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870437
Wei-Han Yu, Haidong Yi, Pui-in Mak, Jun Yin, R. Martins
For true mobility, wearable electronics should be self-powered by the environment. On-body thermoelectric (∼50µW/cm2) is a maturing energy source but delivers a deeply low and inconstant output voltage (0.05 to 0.3V) hindering its utility. With the limited power efficiency of ultra-low-voltage (ULV) boost converters (64% in [1]), there is a rising interest in developing ULV radios that can operate directly at the energy-harvester output, reducing the waste of energy and active-sleep latency. The 2.4GHz receiver in [2] validates 0.3V operation, but is a non-standard design without I/Q demodulation. Also, its focus is on the active power (1.6mW) assuming its 0.3V supply is constant.
{"title":"24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS","authors":"Wei-Han Yu, Haidong Yi, Pui-in Mak, Jun Yin, R. Martins","doi":"10.1109/ISSCC.2017.7870437","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870437","url":null,"abstract":"For true mobility, wearable electronics should be self-powered by the environment. On-body thermoelectric (∼50µW/cm2) is a maturing energy source but delivers a deeply low and inconstant output voltage (0.05 to 0.3V) hindering its utility. With the limited power efficiency of ultra-low-voltage (ULV) boost converters (64% in [1]), there is a rising interest in developing ULV radios that can operate directly at the energy-harvester output, reducing the waste of energy and active-sleep latency. The 2.4GHz receiver in [2] validates 0.3V operation, but is a non-standard design without I/Q demodulation. Also, its focus is on the active power (1.6mW) assuming its 0.3V supply is constant.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116842431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870303
Kaiyuan Yang, Qing Dong, D. Blaauw, D. Sylvester
Physically Unclonable Functions (PUFs) are among the most promising security primitives for low cost solutions of key storage, chip authentication, and supply chain protection. Two types of PUFs exist in literature [1–6], a “strong” PUF with a large challenge-response space [6] and a “weak” PUF providing a limited length key (chip ID) [1–5]. While the former provides better security theoretically, existing implementations are prone to modeling attacks. So-called “weak” PUFs typically have an array of identically designed PUF cells that leverage device mismatch in fabrication as static entropy source, and serve as a low-cost and more secure alternative to non-volatile-memory-based key storage. Output stability across PVT variations and area are two critical metrics directly related to security and cost of a PUF. Recent works have presented custom PUFs based on NAND gates [1], current mirrors [2], PTAT [3], and cross-coupled inverters [4–5]. These outperform conventional SRAM-based PUFs, but sacrifice other metrics, e.g., [2, 4] are large, [3, 5] has lower native stability and energy efficiency, while [1] is sensitive to supply voltage and may experience large short circuit current. Finally, IoT and wireless sensor nodes tend to use older technologies for lower cost and standby power, which is challenging for PUF design because of smaller process variations.
{"title":"8.3 A 553F2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability","authors":"Kaiyuan Yang, Qing Dong, D. Blaauw, D. Sylvester","doi":"10.1109/ISSCC.2017.7870303","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870303","url":null,"abstract":"Physically Unclonable Functions (PUFs) are among the most promising security primitives for low cost solutions of key storage, chip authentication, and supply chain protection. Two types of PUFs exist in literature [1–6], a “strong” PUF with a large challenge-response space [6] and a “weak” PUF providing a limited length key (chip ID) [1–5]. While the former provides better security theoretically, existing implementations are prone to modeling attacks. So-called “weak” PUFs typically have an array of identically designed PUF cells that leverage device mismatch in fabrication as static entropy source, and serve as a low-cost and more secure alternative to non-volatile-memory-based key storage. Output stability across PVT variations and area are two critical metrics directly related to security and cost of a PUF. Recent works have presented custom PUFs based on NAND gates [1], current mirrors [2], PTAT [3], and cross-coupled inverters [4–5]. These outperform conventional SRAM-based PUFs, but sacrifice other metrics, e.g., [2, 4] are large, [3, 5] has lower native stability and energy efficiency, while [1] is sensitive to supply voltage and may experience large short circuit current. Finally, IoT and wireless sensor nodes tend to use older technologies for lower cost and standby power, which is challenging for PUF design because of smaller process variations.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115064515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870398
H. Krishnamurthy, V. Vaidya, Sheldon Weng, K. Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, G. Matthew, J. Tschanz, V. De
Fully integrated on-die buck voltage regulators (VR) promise efficient and wide-range local power delivery and management capability with fast transient response for fine-grain DVFS domains of high power density in complex SoCs. Integration of high-quality power inductors that can support high current density with minimal losses is a major challenge.
{"title":"20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS","authors":"H. Krishnamurthy, V. Vaidya, Sheldon Weng, K. Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, G. Matthew, J. Tschanz, V. De","doi":"10.1109/ISSCC.2017.7870398","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870398","url":null,"abstract":"Fully integrated on-die buck voltage regulators (VR) promise efficient and wide-range local power delivery and management capability with fast transient response for fine-grain DVFS domains of high power density in complex SoCs. Integration of high-quality power inductors that can support high current density with minimal losses is a major challenge.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121460475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870402
Junmin Jiang, Yan Lu, W. Ki, U. Seng-Pan, R. Martins
Multicore application processors in smartphones/watches use power-saving techniques such as dynamic voltage and frequency scaling (DVFS) to extend battery cycle, and supply cores with different voltages [1]. High-efficiency fully integrated switched-capacitor (SC) power converters with no external components are promising candidates [2]. Typically, SC converters with different specifications are independently designed (Fig. 20.5.1), leading to a large area overhead, as each converter has to handle its peak output power. Recently, multi-output SC converters are reported to tackle this issue. In [3], an on-demand strategy is used to control two outputs, each with a different loading range, and the outputs are not interchangeable. In [4], the two output voltages are fixed with voltage conversion ratios (VCRs) of 2× and 3× only. In [5], the controller is integrated, but the three output voltages are still from three individual SC converters. Without reallocating the capacitors in the power stages, capacitor utilization is low, as margins have to be reserved to cater for each converter's peak output power. This paper presents a fully integrated dual-output SC converter with dynamic power-cell allocation for application processors. The power cells are shared and can be dynamically allocated according to load demands. A dual-path VCO that works independently of power-cell allocation is proposed to realize a fast and stable regulation loop. The converter can deliver a maximum current of 100mA: one output can be adjusted to deliver 100mA, while the other handles a very light load; or both outputs can be adjusted to deliver 50mA each with over 80% efficiency.
{"title":"20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS","authors":"Junmin Jiang, Yan Lu, W. Ki, U. Seng-Pan, R. Martins","doi":"10.1109/ISSCC.2017.7870402","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870402","url":null,"abstract":"Multicore application processors in smartphones/watches use power-saving techniques such as dynamic voltage and frequency scaling (DVFS) to extend battery cycle, and supply cores with different voltages [1]. High-efficiency fully integrated switched-capacitor (SC) power converters with no external components are promising candidates [2]. Typically, SC converters with different specifications are independently designed (Fig. 20.5.1), leading to a large area overhead, as each converter has to handle its peak output power. Recently, multi-output SC converters are reported to tackle this issue. In [3], an on-demand strategy is used to control two outputs, each with a different loading range, and the outputs are not interchangeable. In [4], the two output voltages are fixed with voltage conversion ratios (VCRs) of 2× and 3× only. In [5], the controller is integrated, but the three output voltages are still from three individual SC converters. Without reallocating the capacitors in the power stages, capacitor utilization is low, as margins have to be reserved to cater for each converter's peak output power. This paper presents a fully integrated dual-output SC converter with dynamic power-cell allocation for application processors. The power cells are shared and can be dynamically allocated according to load demands. A dual-path VCO that works independently of power-cell allocation is proposed to realize a fast and stable regulation loop. The converter can deliver a maximum current of 100mA: one output can be adjusted to deliver 100mA, while the other handles a very light load; or both outputs can be adjusted to deliver 50mA each with over 80% efficiency.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123494897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870406
P. Nadeau, M. Mimee, Sean Carim, T. Lu, A. Chandrakasan
Genetically engineered, re-programmable bacterial cells are fast emerging as a platform for small molecule detection in challenging environments [1]. A key barrier to widespread deployment of autonomous bacterial sensors is the detection of low-level bioluminescence, which is typically quantified with power-hungry (watt-level) detection hardware such as Photo Multiplier Tubes (PMT). Prior work has reported successful integrated mW-level detection of bioluminescence by using PN / PIN photodiodes with OTA-based [2] and active-pixel-sensor circuits [3,4]. Our goal was to develop an even lower power readout to enable harvesting as a viable source of energy for a future batteryless autonomous biological sensor node, with applications in distributed remote environmental sensing, or in vivo biochemical sensing.
{"title":"21.1 Nanowatt circuit interface to whole-cell bacterial sensors","authors":"P. Nadeau, M. Mimee, Sean Carim, T. Lu, A. Chandrakasan","doi":"10.1109/ISSCC.2017.7870406","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870406","url":null,"abstract":"Genetically engineered, re-programmable bacterial cells are fast emerging as a platform for small molecule detection in challenging environments [1]. A key barrier to widespread deployment of autonomous bacterial sensors is the detection of low-level bioluminescence, which is typically quantified with power-hungry (watt-level) detection hardware such as Photo Multiplier Tubes (PMT). Prior work has reported successful integrated mW-level detection of bioluminescence by using PN / PIN photodiodes with OTA-based [2] and active-pixel-sensor circuits [3,4]. Our goal was to develop an even lower power readout to enable harvesting as a viable source of energy for a future batteryless autonomous biological sensor node, with applications in distributed remote environmental sensing, or in vivo biochemical sensing.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125283312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870473
S. Moazeni, Sen Lin, M. Wade, L. Alloatti, Rajeev J Ram, M. Popović, V. Stojanović
Silicon photonics is a rapidly maturing technology, promising to realize low-cost and energy-efficient optical links for rack-to-rack, within-rack datacenter applications, and supercomputer interconnects. Recently, the possibility of implementing ultra-power-efficient silicon photonic links using an unmodified state-of-the-art 45nm SOI CMOS process has been demonstrated [1]. This approach enabled the fabrication of millions of transistors and hundreds of photonic devices in the same chip to improve processor-memory link bandwidth, and opened a path to solving this traditional computation bottleneck.
硅光子学是一项迅速成熟的技术，有望实现低成本和节能的光链路，用于机架到机架、机架内数据中心应用和超级计算机互连。最近，已经证明了使用未经修改的最先进的45nm SOI CMOS工艺实现超节能硅光子链路的可能性[1]。这种方法使得在同一芯片上制造数百万个晶体管和数百个光子器件，从而提高了处理器-存储器链路带宽，为解决这一传统的计算瓶颈开辟了一条道路。
{"title":"29.3 A 40Gb/s PAM-4 transmitter based on a ring-resonator optical DAC in 45nm SOI CMOS","authors":"S. Moazeni, Sen Lin, M. Wade, L. Alloatti, Rajeev J Ram, M. Popović, V. Stojanović","doi":"10.1109/ISSCC.2017.7870473","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870473","url":null,"abstract":"Silicon photonics is a rapidly maturing technology, promising to realize low-cost and energy-efficient optical links for rack-to-rack, within-rack datacenter applications, and supercomputer interconnects. Recently, the possibility of implementing ultra-power-efficient silicon photonic links using an unmodified state-of-the-art 45nm SOI CMOS process has been demonstrated [1]. This approach enabled the fabrication of millions of transistors and hundreds of photonic devices in the same chip to improve processor-memory link bandwidth, and opened a path to solving this traditional computation bottleneck.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128658500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870275
M. Ding, Yao-Hong Liu, Yan Zhang, Chuang Lu, P. Zhang, B. Busze, Christian Bachmann, K. Philips
Wireless sensor nodes (WSN) in IoT applications (e.g., Bluetooth Low Energy, BLE) rely on heavily duty-cycling the wireless transceivers to reduce the overall system power consumption [1]. This requires swift start-up behavior of the transceiver. The crystal oscillator (XO) generates a stable reference clock for the PLL to synthesize a carrier and to derive clocks for all other parts of the transceiver SoC, e.g., ADC and the digital baseband. The typical start-up time (Ts) of an XO is relatively long (∼ms) due to a high quality factor of the crystal quartz. This leads to a significant (up to 30%) power overhead for a highly duty-cycled transceiver with a short packet format, e.g., the packet length is as short as 128µs in BLE (Fig. 5.3.1). A reduction of Ts of the XO is necessary, at the same time, the power overhead to enable a fast start-up should be minimized in order to reduce the overall energy consumption (Fig. 5.3.1).
{"title":"5.3 A 95µW 24MHz digitally controlled crystal oscillator for IoT applications with 36nJ start-up energy and >13× start-up time reduction using a fully-autonomous dynamically-adjusted load","authors":"M. Ding, Yao-Hong Liu, Yan Zhang, Chuang Lu, P. Zhang, B. Busze, Christian Bachmann, K. Philips","doi":"10.1109/ISSCC.2017.7870275","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870275","url":null,"abstract":"Wireless sensor nodes (WSN) in IoT applications (e.g., Bluetooth Low Energy, BLE) rely on heavily duty-cycling the wireless transceivers to reduce the overall system power consumption [1]. This requires swift start-up behavior of the transceiver. The crystal oscillator (XO) generates a stable reference clock for the PLL to synthesize a carrier and to derive clocks for all other parts of the transceiver SoC, e.g., ADC and the digital baseband. The typical start-up time (Ts) of an XO is relatively long (∼ms) due to a high quality factor of the crystal quartz. This leads to a significant (up to 30%) power overhead for a highly duty-cycled transceiver with a short packet format, e.g., the packet length is as short as 128µs in BLE (Fig. 5.3.1). A reduction of Ts of the XO is necessary, at the same time, the power overhead to enable a fast start-up should be minimized in order to reduce the overall energy consumption (Fig. 5.3.1).","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129914888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870311
B. Yousefzadeh, K. Makinwa
This paper presents a BJT-based temperature sensor, which can be accurately trimmed in both ceramic and plastic packages, on the basis of purely electrical measurements at room temperature. This is achieved by combining the voltage-calibration technique from [1] with an on-chip heater, which can heat the sensing BJTs from room temperature to ∼85°C in 0.5s. Measurements show that the sensor can then be trimmed to an inaccuracy of ±0.3°C (3σ) over the military range (−55 to +125°C). This is similar to the inaccuracy obtained after conventional temperature calibration, i.e., at well-defined temperatures, but requires much less calibration time and infrastructure.
{"title":"9.3 A BJT-based temperature sensor with a packaging-robust inaccuracy of ±0.3°C (3σ) from −55°C to +125°C after heater-assisted voltage calibration","authors":"B. Yousefzadeh, K. Makinwa","doi":"10.1109/ISSCC.2017.7870311","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870311","url":null,"abstract":"This paper presents a BJT-based temperature sensor, which can be accurately trimmed in both ceramic and plastic packages, on the basis of purely electrical measurements at room temperature. This is achieved by combining the voltage-calibration technique from [1] with an on-chip heater, which can heat the sensing BJTs from room temperature to ∼85°C in 0.5s. Measurements show that the sensor can then be trimmed to an inaccuracy of ±0.3°C (3σ) over the military range (−55 to +125°C). This is similar to the inaccuracy obtained after conventional temperature calibration, i.e., at well-defined temperatures, but requires much less calibration time and infrastructure.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130661843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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