Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870402
Junmin Jiang, Yan Lu, W. Ki, U. Seng-Pan, R. Martins
Multicore application processors in smartphones/watches use power-saving techniques such as dynamic voltage and frequency scaling (DVFS) to extend battery cycle, and supply cores with different voltages [1]. High-efficiency fully integrated switched-capacitor (SC) power converters with no external components are promising candidates [2]. Typically, SC converters with different specifications are independently designed (Fig. 20.5.1), leading to a large area overhead, as each converter has to handle its peak output power. Recently, multi-output SC converters are reported to tackle this issue. In [3], an on-demand strategy is used to control two outputs, each with a different loading range, and the outputs are not interchangeable. In [4], the two output voltages are fixed with voltage conversion ratios (VCRs) of 2× and 3× only. In [5], the controller is integrated, but the three output voltages are still from three individual SC converters. Without reallocating the capacitors in the power stages, capacitor utilization is low, as margins have to be reserved to cater for each converter's peak output power. This paper presents a fully integrated dual-output SC converter with dynamic power-cell allocation for application processors. The power cells are shared and can be dynamically allocated according to load demands. A dual-path VCO that works independently of power-cell allocation is proposed to realize a fast and stable regulation loop. The converter can deliver a maximum current of 100mA: one output can be adjusted to deliver 100mA, while the other handles a very light load; or both outputs can be adjusted to deliver 50mA each with over 80% efficiency.
{"title":"20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS","authors":"Junmin Jiang, Yan Lu, W. Ki, U. Seng-Pan, R. Martins","doi":"10.1109/ISSCC.2017.7870402","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870402","url":null,"abstract":"Multicore application processors in smartphones/watches use power-saving techniques such as dynamic voltage and frequency scaling (DVFS) to extend battery cycle, and supply cores with different voltages [1]. High-efficiency fully integrated switched-capacitor (SC) power converters with no external components are promising candidates [2]. Typically, SC converters with different specifications are independently designed (Fig. 20.5.1), leading to a large area overhead, as each converter has to handle its peak output power. Recently, multi-output SC converters are reported to tackle this issue. In [3], an on-demand strategy is used to control two outputs, each with a different loading range, and the outputs are not interchangeable. In [4], the two output voltages are fixed with voltage conversion ratios (VCRs) of 2× and 3× only. In [5], the controller is integrated, but the three output voltages are still from three individual SC converters. Without reallocating the capacitors in the power stages, capacitor utilization is low, as margins have to be reserved to cater for each converter's peak output power. This paper presents a fully integrated dual-output SC converter with dynamic power-cell allocation for application processors. The power cells are shared and can be dynamically allocated according to load demands. A dual-path VCO that works independently of power-cell allocation is proposed to realize a fast and stable regulation loop. The converter can deliver a maximum current of 100mA: one output can be adjusted to deliver 100mA, while the other handles a very light load; or both outputs can be adjusted to deliver 50mA each with over 80% efficiency.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123494897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870467
L. Kull, D. Luu, C. Menolfi, M. Braendli, P. Francese, T. Morf, M. Kossel, Hazar Yueksel, A. Cevrero, Ilter Özkaya, T. Toifl
High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and power-efficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1Vppd, comparator noise limits the SNDR of SAR ADCs, making gain stages necessary for higher SNDR - either as comparator pre-amplifiers or between pipelined stages. Pre-amplifiers significantly reduce the conversion speed of the ADC, but they provide maximum SNDR because linearity of the amplifier is irrelevant. An interstage amplifier for pipelining best suits mid-resolution SAR ADCs, where the required linearity is limited. Moreover, pipelining results in higher conversion speeds and power efficiency because the gain stage is used only once per conversion [1]. This work presents a pipelined-SAR ADC architecture that exceeds the conversion speed of previous pipelined and single-stage SAR ADCs. The ADC achieves 50dB SNDR and 950MS/s at 2.26mW, and 1.5GS/s at 6.92mW on an area of 0.0016mm2.
{"title":"28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFET","authors":"L. Kull, D. Luu, C. Menolfi, M. Braendli, P. Francese, T. Morf, M. Kossel, Hazar Yueksel, A. Cevrero, Ilter Özkaya, T. Toifl","doi":"10.1109/ISSCC.2017.7870467","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870467","url":null,"abstract":"High-speed SAR ADCs became popular with modern CMOS technologies because of their mostly digital logic, making them highly suitable for compact and power-efficient multi-GS/s time-interleaved ADCs. As many applications cannot tolerate input swings ≥1Vppd, comparator noise limits the SNDR of SAR ADCs, making gain stages necessary for higher SNDR - either as comparator pre-amplifiers or between pipelined stages. Pre-amplifiers significantly reduce the conversion speed of the ADC, but they provide maximum SNDR because linearity of the amplifier is irrelevant. An interstage amplifier for pipelining best suits mid-resolution SAR ADCs, where the required linearity is limited. Moreover, pipelining results in higher conversion speeds and power efficiency because the gain stage is used only once per conversion [1]. This work presents a pipelined-SAR ADC architecture that exceeds the conversion speed of previous pipelined and single-stage SAR ADCs. The ADC achieves 50dB SNDR and 950MS/s at 2.26mW, and 1.5GS/s at 6.92mW on an area of 0.0016mm2.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124867820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870482
J. V. Sinderen, D. Griffith, Ken Yamamoto, A. Liscidini, Young-sub Yuk
An overview and comparison is provided of the different emerging wireless standards and their circuit solutions, which target low data-rate IoT applications, featuring ultra-low-power and/or long-range. Different RF transceiver implementations are presented, including proprietary solutions in license-free spectrum, WLAN-based IEEE802.11ah solutions and mobile operators' alternatives based on emerging long-term evolution (LTEM) standards. The different approaches coming to the market and their circuit design aspects will be discussed.
{"title":"F4: Wireless low-power transceivers for local and wide-area networks","authors":"J. V. Sinderen, D. Griffith, Ken Yamamoto, A. Liscidini, Young-sub Yuk","doi":"10.1109/ISSCC.2017.7870482","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870482","url":null,"abstract":"An overview and comparison is provided of the different emerging wireless standards and their circuit solutions, which target low data-rate IoT applications, featuring ultra-low-power and/or long-range. Different RF transceiver implementations are presented, including proprietary solutions in license-free spectrum, WLAN-based IEEE802.11ah solutions and mobile operators' alternatives based on emerging long-term evolution (LTEM) standards. The different approaches coming to the market and their circuit design aspects will be discussed.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125047373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870247
D. Chowdhury, Sraavan R. Mundlapudi, A. Afsahi
Envelope tracking (ET) has become popular for enhancing battery life in mobile communication devices that employ high peak-to-average power ratio (PAPR) signals. Most of the published ET systems have focused either on narrow-bandwidth standards, 20MHz WLAN, or LTE [1–3]. However, as the demand for higher bandwidths and data-rates increases, so does the need for wideband ET solutions. Furthermore, to support modulations with different PAPR and transmit powers, the PA will likely require seamless switching between a continuous ET mode and a fixed-supply mode (as with a low drop-out regulator, i.e. a LDO). Hence, fast reconfigurability is needed, which most published ET systems lack. This paper describes a fully integrated, reconfigurable WLAN ET system with digital baseband in a 28nm CMOS technology for bandwidths up to 40MHz. The ET modulator directly interfaces with a battery (Vbat) and is fully integrated within a complete WLAN transceiver with RF, digital, and frequency synthesizer circuitry.
{"title":"2.2 A fully integrated reconfigurable wideband envelope-tracking SoC for high-bandwidth WLAN applications in a 28nm CMOS technology","authors":"D. Chowdhury, Sraavan R. Mundlapudi, A. Afsahi","doi":"10.1109/ISSCC.2017.7870247","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870247","url":null,"abstract":"Envelope tracking (ET) has become popular for enhancing battery life in mobile communication devices that employ high peak-to-average power ratio (PAPR) signals. Most of the published ET systems have focused either on narrow-bandwidth standards, 20MHz WLAN, or LTE [1–3]. However, as the demand for higher bandwidths and data-rates increases, so does the need for wideband ET solutions. Furthermore, to support modulations with different PAPR and transmit powers, the PA will likely require seamless switching between a continuous ET mode and a fixed-supply mode (as with a low drop-out regulator, i.e. a LDO). Hence, fast reconfigurability is needed, which most published ET systems lack. This paper describes a fully integrated, reconfigurable WLAN ET system with digital baseband in a 28nm CMOS technology for bandwidths up to 40MHz. The ET modulator directly interfaces with a battery (Vbat) and is fully integrated within a complete WLAN transceiver with RF, digital, and frequency synthesizer circuitry.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123025116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870398
H. Krishnamurthy, V. Vaidya, Sheldon Weng, K. Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, G. Matthew, J. Tschanz, V. De
Fully integrated on-die buck voltage regulators (VR) promise efficient and wide-range local power delivery and management capability with fast transient response for fine-grain DVFS domains of high power density in complex SoCs. Integration of high-quality power inductors that can support high current density with minimal losses is a major challenge.
{"title":"20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS","authors":"H. Krishnamurthy, V. Vaidya, Sheldon Weng, K. Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, G. Matthew, J. Tschanz, V. De","doi":"10.1109/ISSCC.2017.7870398","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870398","url":null,"abstract":"Fully integrated on-die buck voltage regulators (VR) promise efficient and wide-range local power delivery and management capability with fast transient response for fine-grain DVFS domains of high power density in complex SoCs. Integration of high-quality power inductors that can support high current density with minimal losses is a major challenge.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121460475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870458
Man-Chia Chen, A. Perez, Sri-Rajasekhar Kothapalli, P. Cathelin, A. Cathelin, S. Gambhir, B. Murmann
A variety of emerging applications in medical ultrasound rely on 3D volumetric imaging, calling for dense 2D transducer arrays with thousands of elements. Due to this high channel count, the traditional per-element cable interface used for 1D arrays is no longer viable. To address this issue, recent work has proven the viability of flip-chip bonding [1] or direct transducer integration [2]. This shifts the burden to a CMOS substrate, which must provide dense signal conditioning and processing before the massively parallel image data can be pushed off chip. A common approach for data reduction is to employ subarray beamforming (BF), which applies delay and sum operations within a group of pixels. To implement such functionality within the tight pixel pitch, prior works have implemented the delays using simple S/H circuits [2] or analog filters [3], and typically suffer from a combination of issues related to limited delay, coarse delay resolution and limited SNR.
{"title":"27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOI","authors":"Man-Chia Chen, A. Perez, Sri-Rajasekhar Kothapalli, P. Cathelin, A. Cathelin, S. Gambhir, B. Murmann","doi":"10.1109/ISSCC.2017.7870458","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870458","url":null,"abstract":"A variety of emerging applications in medical ultrasound rely on 3D volumetric imaging, calling for dense 2D transducer arrays with thousands of elements. Due to this high channel count, the traditional per-element cable interface used for 1D arrays is no longer viable. To address this issue, recent work has proven the viability of flip-chip bonding [1] or direct transducer integration [2]. This shifts the burden to a CMOS substrate, which must provide dense signal conditioning and processing before the massively parallel image data can be pushed off chip. A common approach for data reduction is to employ subarray beamforming (BF), which applies delay and sum operations within a group of pixels. To implement such functionality within the tight pixel pitch, prior works have implemented the delays using simple S/H circuits [2] or analog filters [3], and typically suffer from a combination of issues related to limited delay, coarse delay resolution and limited SNR.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122636964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870406
P. Nadeau, M. Mimee, Sean Carim, T. Lu, A. Chandrakasan
Genetically engineered, re-programmable bacterial cells are fast emerging as a platform for small molecule detection in challenging environments [1]. A key barrier to widespread deployment of autonomous bacterial sensors is the detection of low-level bioluminescence, which is typically quantified with power-hungry (watt-level) detection hardware such as Photo Multiplier Tubes (PMT). Prior work has reported successful integrated mW-level detection of bioluminescence by using PN / PIN photodiodes with OTA-based [2] and active-pixel-sensor circuits [3,4]. Our goal was to develop an even lower power readout to enable harvesting as a viable source of energy for a future batteryless autonomous biological sensor node, with applications in distributed remote environmental sensing, or in vivo biochemical sensing.
{"title":"21.1 Nanowatt circuit interface to whole-cell bacterial sensors","authors":"P. Nadeau, M. Mimee, Sean Carim, T. Lu, A. Chandrakasan","doi":"10.1109/ISSCC.2017.7870406","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870406","url":null,"abstract":"Genetically engineered, re-programmable bacterial cells are fast emerging as a platform for small molecule detection in challenging environments [1]. A key barrier to widespread deployment of autonomous bacterial sensors is the detection of low-level bioluminescence, which is typically quantified with power-hungry (watt-level) detection hardware such as Photo Multiplier Tubes (PMT). Prior work has reported successful integrated mW-level detection of bioluminescence by using PN / PIN photodiodes with OTA-based [2] and active-pixel-sensor circuits [3,4]. Our goal was to develop an even lower power readout to enable harvesting as a viable source of energy for a future batteryless autonomous biological sensor node, with applications in distributed remote environmental sensing, or in vivo biochemical sensing.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125283312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870336
I. Arsovski, Michael Fragano, R. Houle, A. Patil, V. Butler, Raymond Kim, R. Rodriguez, T. Maffitt, J. J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, S. Burns
Ternary Content Addressable Memory (TCAM) executes a fully parallel search of its entire memory contents and uses powerful wild-card pattern matching to return search results in a single clock cycle. This capability makes TCAM attractive for implementing fast hardware look-up tables in network routers, processor caches, and many pattern recognition applications. However, the push for higher performance and increased memory density coupled with parallel TCAM array activation during search operation creates large Ldi/dt power supply noise challenges that could result in timing fails in both TCAM and its surrounding logic.
{"title":"12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%","authors":"I. Arsovski, Michael Fragano, R. Houle, A. Patil, V. Butler, Raymond Kim, R. Rodriguez, T. Maffitt, J. J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, S. Burns","doi":"10.1109/ISSCC.2017.7870336","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870336","url":null,"abstract":"Ternary Content Addressable Memory (TCAM) executes a fully parallel search of its entire memory contents and uses powerful wild-card pattern matching to return search results in a single clock cycle. This capability makes TCAM attractive for implementing fast hardware look-up tables in network routers, processor caches, and many pattern recognition applications. However, the push for higher performance and increased memory density coupled with parallel TCAM array activation during search operation creates large Ldi/dt power supply noise challenges that could result in timing fails in both TCAM and its surrounding logic.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125329996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870316
Hui Jiang, K. Makinwa, S. Nihtianov
Wheatstone bridge sensors are often used in precision instrumentation and measurement systems, e.g., for μK-resolution temperature sensing in wafer steppers [1] and mPa-resolution differential pressure sensing in precision air gauges [2]. Since they output small differential signals superimposed on a large common-mode (CM) voltage, typical bridge readout ICs (ROICs) consist of an instrumentation amplifier (IA) followed by an ADC [1]. This paper describes a low-noise energy-efficient ROIC, which achieves a 3.7nV/√Hz input-referred noise PSD and a power efficiency factor (PEF) of 44.1. The latter represents a 5× improvement on the state of the art [3].
{"title":"9.8 An energy-efficient 3.7nV/√Hz bridge-readout IC with a stable bridge offset compensation scheme","authors":"Hui Jiang, K. Makinwa, S. Nihtianov","doi":"10.1109/ISSCC.2017.7870316","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870316","url":null,"abstract":"Wheatstone bridge sensors are often used in precision instrumentation and measurement systems, e.g., for μK-resolution temperature sensing in wafer steppers [1] and mPa-resolution differential pressure sensing in precision air gauges [2]. Since they output small differential signals superimposed on a large common-mode (CM) voltage, typical bridge readout ICs (ROICs) consist of an instrumentation amplifier (IA) followed by an ADC [1]. This paper describes a low-noise energy-efficient ROIC, which achieves a 3.7nV/√Hz input-referred noise PSD and a power efficiency factor (PEF) of 44.1. The latter represents a 5× improvement on the state of the art [3].","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125783409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870474
Ashwin Ramachandran, A. Natarajan, Tejasvi Anand
Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FFE-based equalization techniques on power-efficient voltage-mode drivers have been used on the transmit end. Based on the FFE tap resolution requirement, the output driver and pre-driver are divided into multiple segments. Although such a segmented FFE implementation helps to maintain a constant output termination impedance (50Ω) across all tap settings, it comes at the cost of (a) increased signaling power, and (b) increased switching power since multiple segments are required to achieve desired linearity [1]. Phase domain equalization techniques, such as pulse width modulation (PWM), can equalize the channel without increasing signaling power or segmenting the output driver. However, PWM encoding requires the insertion of a precise narrow pulse in every data bit, which necessitates very wide bandwidth in the high-speed data path, resulting in poor energy efficiency [2] and difficulty in scaling PWM encoding to higher data rates [3]. For example, creating a 10% duty cycle on a 64Gb/s PWM data stream would require a pulse width of 1.5ps with less than 1ps of rise/fall time at the transmitter output. Other phase domain pre-emphasis techniques are ineffective for high-loss channels [4]. In view of these limitations, we present a new phase-domain equalization technique: integrated pulse width modulation (iPWM) in a 16Gb/s transceiver, which can equalize 19dB of channel loss, while consuming 57.3mW power. Compared to state-of-the-art PWM designs, the proposed iPWM scheme achieves 36× better energy efficiency for the same data rate [2], and 3.2× higher data rate for the same energy efficiency [3].
{"title":"29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOS","authors":"Ashwin Ramachandran, A. Natarajan, Tejasvi Anand","doi":"10.1109/ISSCC.2017.7870474","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870474","url":null,"abstract":"Asymmetric links such as memory interfaces and display drivers require the transmitter to perform necessary equalization, while the receiver remains simple and has minimal or no equalization capability. Traditionally, FFE-based equalization techniques on power-efficient voltage-mode drivers have been used on the transmit end. Based on the FFE tap resolution requirement, the output driver and pre-driver are divided into multiple segments. Although such a segmented FFE implementation helps to maintain a constant output termination impedance (50Ω) across all tap settings, it comes at the cost of (a) increased signaling power, and (b) increased switching power since multiple segments are required to achieve desired linearity [1]. Phase domain equalization techniques, such as pulse width modulation (PWM), can equalize the channel without increasing signaling power or segmenting the output driver. However, PWM encoding requires the insertion of a precise narrow pulse in every data bit, which necessitates very wide bandwidth in the high-speed data path, resulting in poor energy efficiency [2] and difficulty in scaling PWM encoding to higher data rates [3]. For example, creating a 10% duty cycle on a 64Gb/s PWM data stream would require a pulse width of 1.5ps with less than 1ps of rise/fall time at the transmitter output. Other phase domain pre-emphasis techniques are ineffective for high-loss channels [4]. In view of these limitations, we present a new phase-domain equalization technique: integrated pulse width modulation (iPWM) in a 16Gb/s transceiver, which can equalize 19dB of channel loss, while consuming 57.3mW power. Compared to state-of-the-art PWM designs, the proposed iPWM scheme achieves 36× better energy efficiency for the same data rate [2], and 3.2× higher data rate for the same energy efficiency [3].","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130538558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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