Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870432
T.-K.J. Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chunyan Wang, C. Lo, Li-Chin Tien, D. Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, D. Kwai, Zhe Wang, Wei Wu, S. Tomishima, Patrick Stolt, Shih-Lien Lu
In recent years, the demand for memory performance has grown rapidly due to the increasing number of cores on a single CPU, along with the integration of graphics processing units and other accelerators. Caching has been a very effective way to relieve bandwidth demand and to reduce average memory latency. As shown by the cache feature table in Fig. 23.9.1, there is a big latency gap between SRAM caches in the CPU and the external DRAM main memory. As a key element for future computing systems, the last level cache (LLC) should have a high random access bandwidth, a low random access latency, a density of 1 to 8Gb, and all signal pads located on one side of the chip [1]. A logic-process-based solution was proposed [2], but it is not scalable, and has a high standby current due to its need for frequent refresh. HBM2 was also proposed [3], but its row latency is not better than conventional DRAM, and its random-access bandwidth is still limited by tFAW, as shown in Fig. 23.9.1. This paper describes the high-bandwidth low-latency (HBLL) RAM design: how it overcomes these challenges and meets requirements in a cost-effective way.
{"title":"23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache","authors":"T.-K.J. Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chunyan Wang, C. Lo, Li-Chin Tien, D. Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, D. Kwai, Zhe Wang, Wei Wu, S. Tomishima, Patrick Stolt, Shih-Lien Lu","doi":"10.1109/ISSCC.2017.7870432","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870432","url":null,"abstract":"In recent years, the demand for memory performance has grown rapidly due to the increasing number of cores on a single CPU, along with the integration of graphics processing units and other accelerators. Caching has been a very effective way to relieve bandwidth demand and to reduce average memory latency. As shown by the cache feature table in Fig. 23.9.1, there is a big latency gap between SRAM caches in the CPU and the external DRAM main memory. As a key element for future computing systems, the last level cache (LLC) should have a high random access bandwidth, a low random access latency, a density of 1 to 8Gb, and all signal pads located on one side of the chip [1]. A logic-process-based solution was proposed [2], but it is not scalable, and has a high standby current due to its need for frequent refresh. HBM2 was also proposed [3], but its row latency is not better than conventional DRAM, and its random-access bandwidth is still limited by tFAW, as shown in Fig. 23.9.1. This paper describes the high-bandwidth low-latency (HBLL) RAM design: how it overcomes these challenges and meets requirements in a cost-effective way.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129886562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870454
H. Chandrakumar, D. Markovic
Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to administer therapy in patients suffering from drug-resistant neurological ailments. However, stimulation generates large artifacts at the recording sites, which saturate traditional front-ends. The common-mode (CM) artifact can be ∼500mV, and the differential-mode (DM) artifact is 50 to 100mV. This work presents a neural recording chopper amplifier that can tolerate 80mVpp DM and 650mVpp CM artifacts in a signal band of 1Hz to 5kHz. To digitize a 2mVpp neural signal to 8b accompanied by an 80mVpp DM artifact requires a linearity of 80dB. Neural recording front-ends also need to function within a power budget of 3 to 5µW/ch, input-referred noise of 4 to 8µVrms, DC input impedance Zin>1GΩ and high-pass cutoff of 1Hz [1,2]. Prior work has addressed power and noise [2–6], but has low Zin and limited input signal range, making them incapable of performing true closed-loop operation.
{"title":"27.1 A 2.8µW 80mVpp-linear-input-range 1.6GΩ-input impedance bio-signal chopper amplifier tolerant to common-mode interference up to 650mVpp","authors":"H. Chandrakumar, D. Markovic","doi":"10.1109/ISSCC.2017.7870454","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870454","url":null,"abstract":"Closed-loop neuromodulation with simultaneous stimulation and sensing is desired to administer therapy in patients suffering from drug-resistant neurological ailments. However, stimulation generates large artifacts at the recording sites, which saturate traditional front-ends. The common-mode (CM) artifact can be ∼500mV, and the differential-mode (DM) artifact is 50 to 100mV. This work presents a neural recording chopper amplifier that can tolerate 80mV<inf>pp</inf> DM and 650mV<inf>pp</inf> CM artifacts in a signal band of 1Hz to 5kHz. To digitize a 2mV<inf>pp</inf> neural signal to 8b accompanied by an 80mV<inf>pp</inf> DM artifact requires a linearity of 80dB. Neural recording front-ends also need to function within a power budget of 3 to 5µW/ch, input-referred noise of 4 to 8µV<inf>rms</inf>, DC input impedance Z<inf>in</inf>>1GΩ and high-pass cutoff of 1Hz [1,2]. Prior work has addressed power and noise [2–6], but has low Z<inf>in</inf> and limited input signal range, making them incapable of performing true closed-loop operation.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126818374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870278
Anand Savanth, James Myers, A. Weddell, D. Flynn, B. Al-Hashimi
RC Relaxation Oscillators (RxO) are attractive for integrated clock sources compared to LC and ring oscillators (RO), as LC oscillators pose integration challenges and RO designs have limited voltage and temperature (V-T) stability. RxOs generate a clock whose time period (TP) depends only on the timing resistor (R) and capacitor (C). Ideally, TP is independent of V-T; however, most RxOs use a reference voltage (VREF) against which the voltage of C (Vc) is compared. Generating a V-T-independent VREF is non-trivial and causes variations in RxO frequency. A common approach is the use of VDD-independent current sources or band-gap or device-Vt-based VREF [1]. The former are generally high-power options [2] while the latter is subject to process and V-T variations. A correct-by-design approach was adopted in [3] demonstrating VDD-independent operation by cancelling variations through differential sampling of VDD. Further, the power overhead of a supply-independent VREF is overcome by exploiting differential-integrator virtual ground. However, 4V2/R power in the RC tank and high-power VCO increase the energy/cycle.
{"title":"5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability","authors":"Anand Savanth, James Myers, A. Weddell, D. Flynn, B. Al-Hashimi","doi":"10.1109/ISSCC.2017.7870278","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870278","url":null,"abstract":"RC Relaxation Oscillators (RxO) are attractive for integrated clock sources compared to LC and ring oscillators (RO), as LC oscillators pose integration challenges and RO designs have limited voltage and temperature (V-T) stability. RxOs generate a clock whose time period (TP) depends only on the timing resistor (R) and capacitor (C). Ideally, TP is independent of V-T; however, most RxOs use a reference voltage (VREF) against which the voltage of C (Vc) is compared. Generating a V-T-independent VREF is non-trivial and causes variations in RxO frequency. A common approach is the use of VDD-independent current sources or band-gap or device-Vt-based VREF [1]. The former are generally high-power options [2] while the latter is subject to process and V-T variations. A correct-by-design approach was adopted in [3] demonstrating VDD-independent operation by cancelling variations through differential sampling of VDD. Further, the power overhead of a supply-independent VREF is overcome by exploiting differential-integrator virtual ground. However, 4V2/R power in the RC tank and high-power VCO increase the energy/cycle.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116370891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870295
Chinq-Shiun Chiu, Shih-Chieh Yen, Chi-Yao Yu, Tzung-Han Wu, C. Chou, S. Tseng, Chih-Hsien Shen, Yu Lu, Hsinhung Chen, Song-Yu Yang, Yen-Tso Chen, G. Dehng, Yangjian Chen, C. Beghein, D. Nalbantis, M. Collados, B. Tenbroek, J. Strange, Caiyi Wang
The demand of higher data-rates for mobile communication has driven the LTE standard to adopt methods to increase channel bandwidth by Carrier Aggregation (CA), this is known as LTE-Advanced (LTE-A). Due to regional spectrum allocation, these carriers can be inter-band, or intra-band with contiguous (CCA) or non-contiguous (NCCA) channels. The band combinations create a major challenge for an LTE-A transceiver (TRX) in dealing with the intermodulation (IM) of aggregated channels. These IM sources include fundamental and harmonics of LOs, VCOs, and the transmitter (TX) modulated signals. In addition, when multiple receivers (RXs) and synthesizers (SXs) are needed to support CA, power consumption becomes a key challenge. This work describes an adaptive RX that can adjust trade-offs between power consumption and RX performance, allowing significant power reduction under normal field conditions. Additionally several techniques are described for mitigation of CA IM spurs.
{"title":"7.3 A 40nm low-power transceiver for LTE-A Carrier Aggregation","authors":"Chinq-Shiun Chiu, Shih-Chieh Yen, Chi-Yao Yu, Tzung-Han Wu, C. Chou, S. Tseng, Chih-Hsien Shen, Yu Lu, Hsinhung Chen, Song-Yu Yang, Yen-Tso Chen, G. Dehng, Yangjian Chen, C. Beghein, D. Nalbantis, M. Collados, B. Tenbroek, J. Strange, Caiyi Wang","doi":"10.1109/ISSCC.2017.7870295","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870295","url":null,"abstract":"The demand of higher data-rates for mobile communication has driven the LTE standard to adopt methods to increase channel bandwidth by Carrier Aggregation (CA), this is known as LTE-Advanced (LTE-A). Due to regional spectrum allocation, these carriers can be inter-band, or intra-band with contiguous (CCA) or non-contiguous (NCCA) channels. The band combinations create a major challenge for an LTE-A transceiver (TRX) in dealing with the intermodulation (IM) of aggregated channels. These IM sources include fundamental and harmonics of LOs, VCOs, and the transmitter (TX) modulated signals. In addition, when multiple receivers (RXs) and synthesizers (SXs) are needed to support CA, power consumption becomes a key challenge. This work describes an adaptive RX that can adjust trade-offs between power consumption and RX performance, allowing significant power reduction under normal field conditions. Additionally several techniques are described for mitigation of CA IM spurs.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"25 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113967850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870381
Cheng Wang, R. Han
Millimeter-wave/terahertz rotational spectroscopy offers ultra-wide-detection range of gas molecules for chemical and biomedical sensing. Therefore, wideband, energy-efficient, and fast-scanning CMOS spectrometers are in demand. Spectrometers using narrow-pulse sources and electromagnetic scattering [1] are broadband, but their resolutions do not meet the requirement (<10kHz) of the absolute specificity. Alternatively, a scheme using a single tunable tone exhibits significant trade-off between bandwidth and performance. The 245GHz spectrometer in [2] presents 4mW radiated power, but only has a 14GHz bandwidth. In [3] and [4], broader bandwidths are achieved at the expense of degraded radiated power (0.1mW) and noise figure (NF=18.4 to ∼23.5dB). In addition, given a typical 10kHz resolution and 1ms integration time, scanning a 100GHz bandwidth with a single tone takes as long as 3 hours. This paper reports a rapid, energy-efficient spectrometer architecture based on dual-frequency-comb scanning. A 220-to-320GHz CMOS spectrometer prototype based on this architecture is demonstrated with a total radiated power of 5.2mW and a NF of 14.6 to ∼19.5dB.
{"title":"17.6 Rapid and energy-efficient molecular sensing using dual mm-Wave combs in 65nm CMOS: A 220-to-320GHz spectrometer with 5.2mW radiated power and 14.6-to-19.5dB noise figure","authors":"Cheng Wang, R. Han","doi":"10.1109/ISSCC.2017.7870381","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870381","url":null,"abstract":"Millimeter-wave/terahertz rotational spectroscopy offers ultra-wide-detection range of gas molecules for chemical and biomedical sensing. Therefore, wideband, energy-efficient, and fast-scanning CMOS spectrometers are in demand. Spectrometers using narrow-pulse sources and electromagnetic scattering [1] are broadband, but their resolutions do not meet the requirement (<10kHz) of the absolute specificity. Alternatively, a scheme using a single tunable tone exhibits significant trade-off between bandwidth and performance. The 245GHz spectrometer in [2] presents 4mW radiated power, but only has a 14GHz bandwidth. In [3] and [4], broader bandwidths are achieved at the expense of degraded radiated power (0.1mW) and noise figure (NF=18.4 to ∼23.5dB). In addition, given a typical 10kHz resolution and 1ms integration time, scanning a 100GHz bandwidth with a single tone takes as long as 3 hours. This paper reports a rapid, energy-efficient spectrometer architecture based on dual-frequency-comb scanning. A 220-to-320GHz CMOS spectrometer prototype based on this architecture is demonstrated with a total radiated power of 5.2mW and a NF of 14.6 to ∼19.5dB.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126479631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870281
Y. Hsu, C. Tai, Mei-Chen Chuang, A. Roth, E. Soenen
The temperature sensing of a chip becomes more critical with the increment of the process and circuit complexity. In advanced processes, the heating effect becomes more severe due to the thermal accumulation within the small chip dimension. In order to provide precise and on-chip local thermal sensing, some structures have been demonstrated [1–7]. The paper presents an ultra-low-power, compact and accurate temperature sensor without trimming for the local heat monitors of SOCs. The approach of the dynamic-distributing-bias temperature sensor efficiently reduces the power consumption and chip area simultaneously with accurate digital outputs. The overall area of the circuit is 0.00946mm2, which shows larger than 2× area reduction compared with the prior art [1–3]. The prototype performs state-of-the-art power consumption of 18.75µW and untrimmed relative 3σ inaccuracy [8] achieving 1.64% among the previous compact temperature sensors with process scales smaller than 40nm [3–7].
{"title":"5.9 An 18.75µW dynamic-distributing-bias temperature sensor with 0.87°C(3σ) untrimmed inaccuracy and 0.00946mm2 area","authors":"Y. Hsu, C. Tai, Mei-Chen Chuang, A. Roth, E. Soenen","doi":"10.1109/ISSCC.2017.7870281","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870281","url":null,"abstract":"The temperature sensing of a chip becomes more critical with the increment of the process and circuit complexity. In advanced processes, the heating effect becomes more severe due to the thermal accumulation within the small chip dimension. In order to provide precise and on-chip local thermal sensing, some structures have been demonstrated [1–7]. The paper presents an ultra-low-power, compact and accurate temperature sensor without trimming for the local heat monitors of SOCs. The approach of the dynamic-distributing-bias temperature sensor efficiently reduces the power consumption and chip area simultaneously with accurate digital outputs. The overall area of the circuit is 0.00946mm2, which shows larger than 2× area reduction compared with the prior art [1–3]. The prototype performs state-of-the-art power consumption of 18.75µW and untrimmed relative 3σ inaccuracy [8] achieving 1.64% among the previous compact temperature sensors with process scales smaller than 40nm [3–7].","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130436883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870257
D. Greenhill, Ron Ho, D. Lewis, H. Schmit, Kok Hong Chan, Andy Tong, Sean Atsatt, D. How, Peter McElheny, Keith Duwel, J. Schulz, Darren Faulkner, Gopal Iyer, George Chen, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Ty Garibay
A Field Programmable Gate Array (FPGA) family was designed to match a programmable fabric die built in 14nm process technology with 28Gb/s transceiver dice. The 2.5D packaging (Fig. 3.3.1) uses embedded interconnect bridges (EMIB) [1]. 20nm transceivers were reused enabling a transceiver roadmap independent of FPGA fabric. Fig. 3.3.2 shows a 560mm2 fabric die and six transceiver dice. The programmable fabric contains 2.8M logic elements, DSP, memory components, and routing interconnect operating at up to 1GHz. Applications drove the need for improved flexibility and security of the FPGA configuration system. A triple-modular redundant microprocessor-based secure device manager (SDM) was designed and is programmed by embedded software.
{"title":"3.3 A 14nm 1GHz FPGA with 2.5D transceiver integration","authors":"D. Greenhill, Ron Ho, D. Lewis, H. Schmit, Kok Hong Chan, Andy Tong, Sean Atsatt, D. How, Peter McElheny, Keith Duwel, J. Schulz, Darren Faulkner, Gopal Iyer, George Chen, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Ty Garibay","doi":"10.1109/ISSCC.2017.7870257","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870257","url":null,"abstract":"A Field Programmable Gate Array (FPGA) family was designed to match a programmable fabric die built in 14nm process technology with 28Gb/s transceiver dice. The 2.5D packaging (Fig. 3.3.1) uses embedded interconnect bridges (EMIB) [1]. 20nm transceivers were reused enabling a transceiver roadmap independent of FPGA fabric. Fig. 3.3.2 shows a 560mm2 fabric die and six transceiver dice. The programmable fabric contains 2.8M logic elements, DSP, memory components, and routing interconnect operating at up to 1GHz. Applications drove the need for improved flexibility and security of the FPGA configuration system. A triple-modular redundant microprocessor-based secure device manager (SDM) was designed and is programmed by embedded software.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133989913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870243
J. Rothberg
Since Watson and Crick's 1953 landmark discovery that biological information was encoded in DNA as a sequence of chemical building-block “letters”, developing technology for reading (or “sequencing”) this chemical code has been fundamental to advances in biology and medicine. Techniques that first enabled this were invented by Sanger in 1978, and were taken to massively parallel form by 454 Life Sciences in 2003 [1]. This ushered in the current or “next-gen” era of genome sequencing technologies for research, medicine, and the emerging field of Genomic-Personalized Medicine, in which healthcare is more fully informed by the individuals' personal genetic makeup.
{"title":"1.3 The development of high-speed DNA sequencing: Jurassic Park, Neanderthal, Moore, and you","authors":"J. Rothberg","doi":"10.1109/ISSCC.2017.7870243","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870243","url":null,"abstract":"Since Watson and Crick's 1953 landmark discovery that biological information was encoded in DNA as a sequence of chemical building-block “letters”, developing technology for reading (or “sequencing”) this chemical code has been fundamental to advances in biology and medicine. Techniques that first enabled this were invented by Sanger in 1978, and were taken to massively parallel form by 454 Life Sciences in 2003 [1]. This ushered in the current or “next-gen” era of genome sequencing technologies for research, medicine, and the emerging field of Genomic-Personalized Medicine, in which healthcare is more fully informed by the individuals' personal genetic makeup.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130719819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870287
J. Im, D. Freitas, A. Roldan, R. Casey, S. Chen, Adam Chou, T. Cronin, Kevin Geary, S. McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, P. Upadhyaya, Geoff Zhang, Y. Frans, Ken Chang
The increasing bandwidth demand in data centers and telecommunication infrastructures had prompted new electrical interface standards capable of operating up to 56Gb/s per-lane. The CEI-56G-VSR-PAM4 standard [1] defines PAM-4 signaling at 56Gb/s targeting chip-to-module interconnect. Figure 6.3.1 shows the measured S21 of a channel resembling such interconnects and the corresponding single-pulse response after TX-FIR and RX CTLE. Although the S21 is merely ∼10dB at 14GHz, the single-pulse response exhibits significant reflections from impedance discontinuities, mainly between package and PCB traces. These reflections are detrimental to PAM-4 signaling and cannot be equalized effectively by RX CTLE and/or a few taps of TX feed-forward equalization. This paper presents the design of a PAM-4 receiver using 10-tap direct decision-feedback equalization (DFE) targeting such VSR channels.
{"title":"6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFET","authors":"J. Im, D. Freitas, A. Roldan, R. Casey, S. Chen, Adam Chou, T. Cronin, Kevin Geary, S. McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, P. Upadhyaya, Geoff Zhang, Y. Frans, Ken Chang","doi":"10.1109/ISSCC.2017.7870287","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870287","url":null,"abstract":"The increasing bandwidth demand in data centers and telecommunication infrastructures had prompted new electrical interface standards capable of operating up to 56Gb/s per-lane. The CEI-56G-VSR-PAM4 standard [1] defines PAM-4 signaling at 56Gb/s targeting chip-to-module interconnect. Figure 6.3.1 shows the measured S21 of a channel resembling such interconnects and the corresponding single-pulse response after TX-FIR and RX CTLE. Although the S21 is merely ∼10dB at 14GHz, the single-pulse response exhibits significant reflections from impedance discontinuities, mainly between package and PCB traces. These reflections are detrimental to PAM-4 signaling and cannot be equalized effectively by RX CTLE and/or a few taps of TX feed-forward equalization. This paper presents the design of a PAM-4 receiver using 10-tap direct decision-feedback equalization (DFE) targeting such VSR channels.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132718298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870422
Yuan Gao, Lisong Li, P. Mok
Light-emitting diodes (LEDs) are becoming the dominant lighting source over their conventional counterparts. Besides the benefits of high efficiency and long lifetime, LEDs also show great potential for high-speed data transmission because of their wide bandwidth (BW). In addition to offering general lighting, the light output can be modulated with fast-switched LEDs to achieve visible light communication (VLC). Though over 100Mb/s data-rate has been demonstrated with white LEDs in the laboratory, the high-frequency modulation is hardly supported by commonly used dimmable drivers with switching converters to regulate LED current. In these drivers, the changing slope of LED current is limited by both low loop BW and large inductors and capacitors [1]. The linear multiple-string LED drivers [2], free of inductors and big capacitors, theoretically can provide higher turn on/off speed. However, the light output of these drivers usually varies significantly at the double-line-frequency, which not only is considered as a harmful optical flicker, but also greatly affects the effectiveness of data transmission. The linear driver in [3] regulates the product of LED current and LED voltage to mitigate the optical variation, but a multiplier has to be added in the regulation loop, resulting in limited BW.
{"title":"22.8 An AC-input inductorless LED driver for visible-light-communication applications with 8Mb/s data-rate and 6.4% low-frequency flicker","authors":"Yuan Gao, Lisong Li, P. Mok","doi":"10.1109/ISSCC.2017.7870422","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870422","url":null,"abstract":"Light-emitting diodes (LEDs) are becoming the dominant lighting source over their conventional counterparts. Besides the benefits of high efficiency and long lifetime, LEDs also show great potential for high-speed data transmission because of their wide bandwidth (BW). In addition to offering general lighting, the light output can be modulated with fast-switched LEDs to achieve visible light communication (VLC). Though over 100Mb/s data-rate has been demonstrated with white LEDs in the laboratory, the high-frequency modulation is hardly supported by commonly used dimmable drivers with switching converters to regulate LED current. In these drivers, the changing slope of LED current is limited by both low loop BW and large inductors and capacitors [1]. The linear multiple-string LED drivers [2], free of inductors and big capacitors, theoretically can provide higher turn on/off speed. However, the light output of these drivers usually varies significantly at the double-line-frequency, which not only is considered as a harmful optical flicker, but also greatly affects the effectiveness of data transmission. The linear driver in [3] regulates the product of LED current and LED voltage to mitigate the optical variation, but a multiplier has to be added in the regulation loop, resulting in limited BW.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115226904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：