Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870305
H. Ngo, K. Nakata, Toru Yoshioka, Y. Terashima, K. Okada, A. Matsuzawa
This paper presents a supply regulated synthesizable injection-locked PLL (IL-PLL), using a noise-isolation LDO. The noise-isolation LDO realizes a time-shift operation to isolate the PLL from both supply and LDO noise, so the IL-PLL operation remains robust, even within a noisy SoC. The core layout of the PLL is implemented using solely a foundry provided standard-cell library for a 65nm CMOS process with standard digital design tools. Among synthesizable PLLs, jitter performance of 0.42ps is achieved with 3.8mW power consumption at 0.9GHz oscillation.
{"title":"8.5 A 0.42ps-jitter −241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO","authors":"H. Ngo, K. Nakata, Toru Yoshioka, Y. Terashima, K. Okada, A. Matsuzawa","doi":"10.1109/ISSCC.2017.7870305","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870305","url":null,"abstract":"This paper presents a supply regulated synthesizable injection-locked PLL (IL-PLL), using a noise-isolation LDO. The noise-isolation LDO realizes a time-shift operation to isolate the PLL from both supply and LDO noise, so the IL-PLL operation remains robust, even within a noisy SoC. The core layout of the PLL is implemented using solely a foundry provided standard-cell library for a 65nm CMOS process with standard digital design tools. Among synthesizable PLLs, jitter performance of 0.42ps is achieved with 3.8mW power consumption at 0.9GHz oscillation.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114469555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870468
Hongda Xu, Y. Cai, L. Du, Yuan Zhou, Benwei Xu, D. Gong, J. Ye, Y. Chiu
High-resolution, low-power radiation-tolerant ADCs are under great demand from medical, aerospace and high-energy physics applications. In the ATLAS Liquid Argon Calorimeter of the LHC experiment at CERN, the radiation operation condition coupled with the large dynamic range (>12b ENOB), 40-80MS/s sample rate and low power (for cooling system requirement) specs [1] make the design of such ADCs a very challenging task.
{"title":"28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOS","authors":"Hongda Xu, Y. Cai, L. Du, Yuan Zhou, Benwei Xu, D. Gong, J. Ye, Y. Chiu","doi":"10.1109/ISSCC.2017.7870468","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870468","url":null,"abstract":"High-resolution, low-power radiation-tolerant ADCs are under great demand from medical, aerospace and high-energy physics applications. In the ATLAS Liquid Argon Calorimeter of the LHC experiment at CERN, the radiation operation condition coupled with the large dynamic range (>12b ENOB), 40-80MS/s sample rate and low power (for cooling system requirement) specs [1] make the design of such ADCs a very challenging task.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114471836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870368
B. Vaz, A. Lynam, B. Verbruggen, Asma Laraba, Conrado Mesadri, Ali Boumaalif, John McGrath, Umanath Kamath, R. D. L. Torre, A. Manlapat, D. Breathnach, C. Erdmann, B. Farley
In recent years, the need for high performance RF sampling ADCs has driven impressive developments of pipelined-SAR and pipelined ADCs, all supported by time-interleaving [1–4]. All these designs use a closed loop MDAC amplifier in the first stage and digital calibration/equalization to alleviate finite gain, settling and memory effects, but the closed-loop amplifier remains a scaling bottleneck. In this work, a three-stage asynchronous pipelined-SAR with open-loop integrator-based amplifiers is used to maximize the sampling frequency, resolution and linearity. The solution is mostly supported by dynamic circuits and multiple calibration loops to reduce cost, power and noise, maximize process portability and support production testability.
{"title":"16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC","authors":"B. Vaz, A. Lynam, B. Verbruggen, Asma Laraba, Conrado Mesadri, Ali Boumaalif, John McGrath, Umanath Kamath, R. D. L. Torre, A. Manlapat, D. Breathnach, C. Erdmann, B. Farley","doi":"10.1109/ISSCC.2017.7870368","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870368","url":null,"abstract":"In recent years, the need for high performance RF sampling ADCs has driven impressive developments of pipelined-SAR and pipelined ADCs, all supported by time-interleaving [1–4]. All these designs use a closed loop MDAC amplifier in the first stage and digital calibration/equalization to alleviate finite gain, settling and memory effects, but the closed-loop amplifier remains a scaling bottleneck. In this work, a three-stage asynchronous pipelined-SAR with open-loop integrator-based amplifiers is used to maximize the sampling frequency, resolution and linearity. The solution is mostly supported by dynamic circuits and multiple calibration loops to reduce cost, power and noise, maximize process portability and support production testability.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114517447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870302
Eunhwan Kim, Minah Lee, Jae-Joon Kim
On-chip true random number generators (TRNG) have been gaining attention as an important component for building secure systems [1]. CMOS TRNGs typically exploit device-level noise, such as thermal or flicker noise to generate random bits [2]. Among various types of CMOS TRNGs, the meta-stability-based TRNG is known to have very high throughput for random bit generation, but it requires sophisticated control and calibration circuits to suppress bias [6]. Another popular type is the ring oscillator (RO)-based TRNG, which utilizes timing jitter [1–5]. Relatively simple circuits make it an attractive option, but there remains a need to improve the tolerance against power supply attacks and process/environmental variations [3]. Recently, selective use of a certain set of inverter chains based on pre-tuning was proposed to mitigate process variation effects [2].
{"title":"8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors","authors":"Eunhwan Kim, Minah Lee, Jae-Joon Kim","doi":"10.1109/ISSCC.2017.7870302","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870302","url":null,"abstract":"On-chip true random number generators (TRNG) have been gaining attention as an important component for building secure systems [1]. CMOS TRNGs typically exploit device-level noise, such as thermal or flicker noise to generate random bits [2]. Among various types of CMOS TRNGs, the meta-stability-based TRNG is known to have very high throughput for random bit generation, but it requires sophisticated control and calibration circuits to suppress bias [6]. Another popular type is the ring oscillator (RO)-based TRNG, which utilizes timing jitter [1–5]. Relatively simple circuits make it an attractive option, but there remains a need to improve the tolerance against power supply attacks and process/environmental variations [3]. Recently, selective use of a certain set of inverter chains based on pre-tuning was proposed to mitigate process variation effects [2].","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"51 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116293338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870325
Bumkil Lee, Minkyu Song, A. Maity, D. Ma
Switching power converters with fast load transients are crucial for application processors (APs) to facilitate system-level power adaptability with high current slew rate. While current-mode hysteretic control has been popularly employed in switching converters for simple structure, robust operation and fast transient response [1], it still does not suffice for the unprecedented 1A/ns current slew rate required by modern APs [2]. Meanwhile, current slew rate can be improved by extending single-phase to multiphase operation. However, when a converter powers light load, power loss caused by added phases adversely affects the efficiency. Active phase count (APC) was thus proposed to manage the number of active phases judiciously to load by sensing average inductor current [3,4]. However, the inherent sensing delay drastically slows down the phase adding/dropping actions and degrades load transient response. On the other hand, phase current imbalance among phase sub-converters could cause hot spots, jeopardizing system reliability. Upgrading from conventional current-mode hysteretic control, we propose a simple synchronized adaptive window (SAW) hysteretic control which automatically adjusts the hysteretic window to speed up the transient response. Inherent clock synchronization makes it a natural fit to multiphase operation, where APC can be accomplished within one switching cycle through an internal current sensing mechanism in the control.
{"title":"10.7 A 25MHz 4-phase SAW hysteretic DC-DC converter with 1-cycle APC achieving 190ns tsettle to 4A load transient and above 80% efficiency in 96.7% of the power range","authors":"Bumkil Lee, Minkyu Song, A. Maity, D. Ma","doi":"10.1109/ISSCC.2017.7870325","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870325","url":null,"abstract":"Switching power converters with fast load transients are crucial for application processors (APs) to facilitate system-level power adaptability with high current slew rate. While current-mode hysteretic control has been popularly employed in switching converters for simple structure, robust operation and fast transient response [1], it still does not suffice for the unprecedented 1A/ns current slew rate required by modern APs [2]. Meanwhile, current slew rate can be improved by extending single-phase to multiphase operation. However, when a converter powers light load, power loss caused by added phases adversely affects the efficiency. Active phase count (APC) was thus proposed to manage the number of active phases judiciously to load by sensing average inductor current [3,4]. However, the inherent sensing delay drastically slows down the phase adding/dropping actions and degrades load transient response. On the other hand, phase current imbalance among phase sub-converters could cause hot spots, jeopardizing system reliability. Upgrading from conventional current-mode hysteretic control, we propose a simple synchronized adaptive window (SAW) hysteretic control which automatically adjusts the hysteretic window to speed up the transient response. Inherent clock synchronization makes it a natural fit to multiphase operation, where APC can be accomplished within one switching cycle through an internal current sensing mechanism in the control.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124754656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870419
Sandip Uprety, Hoi Lee
With more and more functions in modern battery-powered mobile devices, enabling light-harvesting in the power management system can extend battery usage time [1]. For both indoor and outdoor operations of mobile devices, the output power range of the solar panel with the size of a touchscreen can vary from 100s of µW to a Watt due to the irradiance-level variation. An energy harvester is thus essential to achieve high maximum power-point tracking efficiency (ηT) over this wide power range. However, state-of-the-art energy harvesters only use one maximum power-point tracking (MPPT) method under different irradiance levels as shown in Fig. 22.5.1 [2–5]. Those energy harvesters with power-computation-based MPPT schemes for portable [2,3] and standalone [4] systems suffer from low ηT under low input power due to the limited input dynamic range of the MPPT circuitry. Other low-power energy harvesters with the fractional open-cell voltage (FOCV) MPPT scheme are confined by the fractional-constant accuracy to only offer high ηT across a narrow power range [5]. Additionally, the conventional FOCV MPPT scheme requires long transient time of 250ms to identify MPP [5], thereby significantly reducing energy capture from the solar panel. To address the above issues, this paper presents an energy harvester with an irradiance-aware hybrid algorithm (IAHA) to automatically switch between an auto-zeroed pulse-integration based MPPT (AZ PI-MPPT) and a slew-rate-enhanced FOCV (SRE-FOCV) MPPT scheme for maximizing ηT under different irradiance levels. The SRE-FOCV MPPT scheme also enables the energy harvester to shorten the MPPT transient time to 2.9ms in low irradiance levels.
随着现代电池供电的移动设备的功能越来越多，在电源管理系统中启用光收集可以延长电池的使用时间[1]。对于移动设备的室内和室外操作，由于辐照水平的变化，带有触摸屏大小的太阳能电池板的输出功率范围可以从100 μ W到1瓦特不等。因此，能量收集器对于在如此宽的功率范围内实现高最大功率点跟踪效率(ηT)至关重要。然而，目前最先进的能量采集器在不同辐照度下只使用一种最大功率点跟踪(MPPT)方法，如图22.5.1所示[2-5]。便携式[2,3]和独立式[4]系统中基于功率计算的MPPT方案的能量采集器，由于MPPT电路的输入动态范围有限，在低输入功率下存在低ηT。其他采用分数开槽电压(FOCV) MPPT方案的低功率能量采集器受到分数常数精度的限制，只能在较窄的功率范围内提供高ηT[5]。此外，传统的FOCV MPPT方案需要250ms长的瞬态时间来识别MPP[5]，从而大大减少了太阳能电池板的能量捕获。为了解决上述问题，本文提出了一种具有辐照感知混合算法(IAHA)的能量采集器，该算法可以在基于自动归零脉冲积分的MPPT (AZ PI-MPPT)和旋转速率增强的FOCV (SRE-FOCV) MPPT方案之间自动切换，从而在不同辐照水平下最大化ηT。SRE-FOCV MPPT方案还使能量采集器能够在低辐照水平下将MPPT瞬态时间缩短至2.9ms。
{"title":"22.5 A 93%-power-efficiency photovoltaic energy harvester with irradiance-aware auto-reconfigurable MPPT scheme achieving >95% MPPT efficiency across 650µW to 1W and 2.9ms FOCV MPPT transient time","authors":"Sandip Uprety, Hoi Lee","doi":"10.1109/ISSCC.2017.7870419","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870419","url":null,"abstract":"With more and more functions in modern battery-powered mobile devices, enabling light-harvesting in the power management system can extend battery usage time [1]. For both indoor and outdoor operations of mobile devices, the output power range of the solar panel with the size of a touchscreen can vary from 100s of µW to a Watt due to the irradiance-level variation. An energy harvester is thus essential to achieve high maximum power-point tracking efficiency (ηT) over this wide power range. However, state-of-the-art energy harvesters only use one maximum power-point tracking (MPPT) method under different irradiance levels as shown in Fig. 22.5.1 [2–5]. Those energy harvesters with power-computation-based MPPT schemes for portable [2,3] and standalone [4] systems suffer from low ηT under low input power due to the limited input dynamic range of the MPPT circuitry. Other low-power energy harvesters with the fractional open-cell voltage (FOCV) MPPT scheme are confined by the fractional-constant accuracy to only offer high ηT across a narrow power range [5]. Additionally, the conventional FOCV MPPT scheme requires long transient time of 250ms to identify MPP [5], thereby significantly reducing energy capture from the solar panel. To address the above issues, this paper presents an energy harvester with an irradiance-aware hybrid algorithm (IAHA) to automatically switch between an auto-zeroed pulse-integration based MPPT (AZ PI-MPPT) and a slew-rate-enhanced FOCV (SRE-FOCV) MPPT scheme for maximizing ηT under different irradiance levels. The SRE-FOCV MPPT scheme also enables the energy harvester to shorten the MPPT transient time to 2.9ms in low irradiance levels.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128501595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870240
Cliff Hou
Industry application trends are driving more 3D circuitry both at the chip and system level. These technology trends are inducing new design challenges that require the semiconductor design community to go beyond existing approaches and to come up with new methods to address the challenges of smarter chips. A new design paradigm is becoming imperative to handle end-market demand for more product functionality and the corresponding increase in the complexity of the design task. To address products' distinct technological and design requirements while keeping design cycles within appropriate time-to-market windows, chip designers must leverage solutions that can be supplied by the expertise and assets of semiconductor ecosystems. At the same time, these ecosystems must evolve beyond technology-centric solutions to provide application-specific platform solutions required to meet unique product needs. This paper provides initial direction for the innovation required to realize a smart-chip design paradigm that encompasses design solutions at the chip and system level.
{"title":"1.1 A smart design paradigm for smart chips","authors":"Cliff Hou","doi":"10.1109/ISSCC.2017.7870240","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870240","url":null,"abstract":"Industry application trends are driving more 3D circuitry both at the chip and system level. These technology trends are inducing new design challenges that require the semiconductor design community to go beyond existing approaches and to come up with new methods to address the challenges of smarter chips. A new design paradigm is becoming imperative to handle end-market demand for more product functionality and the corresponding increase in the complexity of the design task. To address products' distinct technological and design requirements while keeping design cycles within appropriate time-to-market windows, chip designers must leverage solutions that can be supplied by the expertise and assets of semiconductor ecosystems. At the same time, these ecosystems must evolve beyond technology-centric solutions to provide application-specific platform solutions required to meet unique product needs. This paper provides initial direction for the innovation required to realize a smart-chip design paradigm that encompasses design solutions at the chip and system level.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129649586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870251
Junlei Zhao, Elham Rahimi, F. Svelto, A. Mazzanti
Several spectrum portions at mm-waves are considered for Gb/s data-rates in 5G cellular wireless backhaul and access networks, further motivating innovation in circuits and systems for efficient transceivers [1,2]. Small or pico-cell networks are required for spatial diversity and propagation-loss compensation, suggesting silicon solutions also for backhauling where the E-band is a candidate. Techniques for spectral and power efficiency are being investigated, key for capacity improvements over LTE and deployment of the large number of required cells. A transmitter power amplifier (PA), delivering near 20dBm, is a key block for power saving. With the high peak-to-average ratio of QAM modulations, PAs are operated at 5-to-8dB back-off [2], where the efficiency of reported silicon E-band PAs is in the order of a few percent only [3–5].
{"title":"2.6 A SiGe BiCMOS E-band power amplifier with 22% PAE at 18dBm OP1dB and 8.5% at 6dB back-off leveraging current clamping in a common-base stage","authors":"Junlei Zhao, Elham Rahimi, F. Svelto, A. Mazzanti","doi":"10.1109/ISSCC.2017.7870251","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870251","url":null,"abstract":"Several spectrum portions at mm-waves are considered for Gb/s data-rates in 5G cellular wireless backhaul and access networks, further motivating innovation in circuits and systems for efficient transceivers [1,2]. Small or pico-cell networks are required for spatial diversity and propagation-loss compensation, suggesting silicon solutions also for backhauling where the E-band is a candidate. Techniques for spectral and power efficiency are being investigated, key for capacity improvements over LTE and deployment of the large number of required cells. A transmitter power amplifier (PA), delivering near 20dBm, is a key block for power saving. With the high peak-to-average ratio of QAM modulations, PAs are operated at 5-to-8dB back-off [2], where the efficiency of reported silicon E-band PAs is in the order of a few percent only [3–5].","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130564605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870244
L. Vandersypen, A. Leeuwenhoek
The challenge of quantum computing is that quantum bits are extremely fragile and their state is easily perturbed by environmental fluctuations. However, recent theoretical and experimental advances have made it clear that the resulting errors can in principle be corrected. What it takes is a system containing thousands or millions of quantum bits operating at ultra-low temperatures, that must be interfaced using complex classical mixed-signal and microwave circuits for read-out and control. By comparison, today’s practical demonstrations involve no more than a dozen quantum bits controlled by bulky instrumentation that is not scalable.
{"title":"1.4 Quantum computing - the next challenge in circuit and system design","authors":"L. Vandersypen, A. Leeuwenhoek","doi":"10.1109/ISSCC.2017.7870244","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870244","url":null,"abstract":"The challenge of quantum computing is that quantum bits are extremely fragile and their state is easily perturbed by environmental fluctuations. However, recent theoretical and experimental advances have made it clear that the resulting errors can in principle be corrected. What it takes is a system containing thousands or millions of quantum bits operating at ultra-low temperatures, that must be interfaced using complex classical mixed-signal and microwave circuits for read-out and control. By comparison, today’s practical demonstrations involve no more than a dozen quantum bits controlled by bulky instrumentation that is not scalable.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132458894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-01DOI: 10.1109/ISSCC.2017.7870285
Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee
Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power consumption. This paper presents a highly parallelized TRX at 56Gb/s with integrated serializer/deserializer, FFE/CTLE/DFE, CDR, and eye-monitoring circuits. It achieves BER<10−12 under 24dB loss at 14GHz while dissipating 602mW of power.
{"title":"6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS","authors":"Pen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee","doi":"10.1109/ISSCC.2017.7870285","DOIUrl":"https://doi.org/10.1109/ISSCC.2017.7870285","url":null,"abstract":"Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power consumption. This paper presents a highly parallelized TRX at 56Gb/s with integrated serializer/deserializer, FFE/CTLE/DFE, CDR, and eye-monitoring circuits. It achieves BER<10−12 under 24dB loss at 14GHz while dissipating 602mW of power.","PeriodicalId":269679,"journal":{"name":"2017 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125351381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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